38#ifndef __CPU_TRACE_TRACE_CPU_HH__
39#define __CPU_TRACE_TRACE_CPU_HH__
45#include <unordered_map>
48#include "debug/TraceCPUData.hh"
49#include "debug/TraceCPUInst.hh"
53#include "params/TraceCPU.hh"
54#include "proto/inst_dep_record.pb.h"
55#include "proto/packet.pb.h"
150 void init()
override;
394 const std::string& trace_file) :
501 const std::string&
_name);
534 typedef ProtoMessage::InstDepRecord
Record;
777 const double time_multiplier);
807 const std::string& trace_file,
808 const TraceCPUParams &
params) :
822 DPRINTF(TraceCPUData,
"Window size in the trace is %d.\n",
928 bool checkAndIssue(
const GraphNode* node_ptr,
bool first=
true);
979 std::unordered_map<NodeSeqNum, GraphNode*>
depGraph;
999 const std::string&
_name);
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Ports are used to interface objects to each other.
const std::string name() const
Return port name (for DPRINTF).
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
DcachePort class that interfaces with L1 Data Cache.
bool isSnooping() const
Required functionally.
void recvFunctionalSnoop(PacketPtr pkt)
Required functionally but do nothing.
DcachePort(TraceCPU *_cpu)
Default constructor.
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completi...
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
void recvReqRetry()
Handle a retry signalled by the cache if data access failed in the first attempt.
The struct GraphNode stores an instruction in the trace file.
bool isLoad() const
Is the node a load.
bool isComp() const
Is the node a compute (non load/store) node.
RecordType type
Type of the node corresponding to the instruction modeled by it.
bool isStrictlyOrdered() const
Return true if node has a request which is strictly ordered.
bool removeDepOnInst(NodeSeqNum done_seq_num)
Check for all dependencies on completed inst.
std::vector< GraphNode * > dependents
A vector of nodes dependent (outgoing) on this node.
std::list< NodeSeqNum > RobDepList
Typedef for the list containing the ROB dependencies.
bool removeRobDep(NodeSeqNum rob_dep)
Remove completed instruction from order dependency array.
std::list< NodeSeqNum > RegDepList
Typedef for the list containing the register dependencies.
Request::Flags flags
Request flags if any.
RegDepList regDep
List of register dependencies (incoming) if any.
uint32_t size
Size of request if any.
NodeRobNum robNum
ROB occupancy number.
std::string typeToStr() const
Return string specifying the type of the node.
void writeElementAsTrace() const
Write out element in trace-compatible format using debug flag TraceCPUData.
RobDepList robDep
List of order dependencies.
Addr physAddr
The address for the request if any.
Addr virtAddr
The virtual address for the request if any.
bool isStore() const
Is the node a store.
uint64_t compDelay
Computational delay.
NodeSeqNum seqNum
Instruction sequence number.
bool removeRegDep(NodeSeqNum reg_dep)
Remove completed instruction from register dependency array.
The HardwareResource class models structures that hold the in-flight nodes.
uint16_t numInFlightStores
Number of ready stores for which request may or may not be sent.
const uint16_t sizeStoreBuffer
The size of store buffer.
void occupy(const GraphNode *new_node)
Occupy appropriate structures for an issued node.
void release(const GraphNode *done_node)
Release appropriate structures for a completed node.
uint16_t numInFlightLoads
Number of ready loads for which request may or may not be sent.
bool awaitingResponse() const
Check if there are any outstanding requests, i.e.
NodeRobNum oldestInFlightRobNum
The ROB number of the oldest in-flight node.
std::map< NodeSeqNum, NodeRobNum > inFlightNodes
A map from the sequence number to the ROB number of the in- flight nodes.
void printOccupancy()
Print resource occupancy for debugging.
const uint16_t sizeROB
The size of the ROB used to throttle the max.
HardwareResource(uint16_t max_rob, uint16_t max_stores, uint16_t max_loads)
Constructor that initializes the sizes of the structures.
const uint16_t sizeLoadBuffer
The size of load buffer.
void releaseStoreBuffer()
Release store buffer entry for a completed store.
bool isAvailable(const GraphNode *new_node) const
Check if structures required to issue a node are free.
The elastic data memory request generator to read protobuf trace containing execution trace annotated...
const uint32_t windowSize
Window size within which to check for dependencies.
uint64_t NodeRobNum
Node ROB number type.
bool readNextWindow()
Reads a line of the trace file.
PacketPtr executeMemReq(GraphNode *node_ptr)
Creates a new request for a load or store assigning the request parameters.
ProtoMessage::InstDepRecord::RecordType RecordType
void printReadyList()
Print readyList for debugging using debug flag TraceCPUData.
bool isExecComplete() const
Returns the execComplete variable which is set when the last node is executed.
TraceCPU & owner
Reference of the TraceCPU.
const RequestorID requestorId
RequestorID used for the requests being sent.
Tick init()
Called from TraceCPU init().
ProtoMessage::InstDepRecord Record
uint64_t NodeSeqNum
Node sequence number type.
void adjustInitTraceOffset(Tick &offset)
Adjust traceOffset based on what TraceCPU init() determines on comparing the offsets in the fetch req...
bool checkAndIssue(const GraphNode *node_ptr, bool first=true)
Attempts to issue a node once the node's source dependencies are complete.
std::list< ReadyNode > readyList
List of nodes that are ready to execute.
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
const std::string & name() const
Returns name of the ElasticDataGen instance.
bool traceComplete
Set to true when end of trace is reached.
void exit()
Exit the ElasticDataGen.
ElasticDataGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file, const TraceCPUParams ¶ms)
bool nextRead
Set to true when the next window of instructions need to be read.
std::queue< const GraphNode * > depFreeQueue
Queue of dependency-free nodes that are pending issue because resources are not available.
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup elasticStats
std::unordered_map< NodeSeqNum, GraphNode * > depGraph
Store the depGraph of GraphNodes.
uint64_t getMicroOpCount() const
Get number of micro-ops modelled in the TraceCPU replay.
std::string genName
String to store the name of the FixedRetryGen.
void addDepsOnParent(GraphNode *new_node, T &dep_list)
Iterate over the dependencies of a new node and add the new node to the list of dependents of the par...
bool execComplete
Set true when execution of trace is complete.
RequestPort & port
Reference of the port to be used to issue memory requests.
HardwareResource hwResource
Hardware resources required to contain in-flight nodes and to throttle issuing of new nodes when reso...
void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick)
Add a ready node to the readyList.
InputStream trace
Input stream used for reading the input trace file.
void execute()
This is the main execute function which consumes nodes from the sorted readyList.
void completeMemAccess(PacketPtr pkt)
When a load writeback is received, that is when the load completes, release the dependents on it.
Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control...
TraceCPU & owner
Reference of the TraceCPU.
int64_t delta
Stores the difference in the send ticks of the current and last packets.
Tick init()
Called from TraceCPU init().
const RequestorID requestorId
RequestorID used for the requests being sent.
FixedRetryGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file)
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup fixedStats
TraceElement currElement
Store an element read from the trace to send as the next packet.
bool nextExecute()
Reads a line of the trace file.
bool traceComplete
Set to true when end of trace is reached.
const std::string & name() const
Returns name of the FixedRetryGen instance.
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
bool isTraceComplete()
Returns the traceComplete variable which is set when end of the input trace file is reached.
std::string genName
String to store the name of the FixedRetryGen.
void exit()
Exit the FixedRetryGen.
RequestPort & port
Reference of the port to be used to issue memory requests.
InputStream trace
Input stream used for reading the input trace file.
bool send(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags, Addr pc)
Creates a new request assigning the request parameters passed by the arguments.
bool tryNext()
This tries to send current or retry packet and returns true if successfull.
IcachePort class that interfaces with L1 Instruction Cache.
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
IcachePort(TraceCPU *_cpu)
Default constructor.
void recvReqRetry()
Handle a retry signalled by the cache if instruction read failed in the first attempt.
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and simply delete the packet since instruction fetch requests are issued a...
The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.
const uint64_t progressMsgInterval
Interval of committed instructions specified by the user at which a progress info message is printed.
Port & getDataPort()
Used to get a reference to the dcache port.
DcachePort dcachePort
Port to connect to L1 data cache.
const bool enableEarlyExit
Exit when any one Trace CPU completes its execution.
IcachePort icachePort
Port to connect to L1 instruction cache.
const RequestorID instRequestorID
Requestor id for instruction read requests.
bool oneTraceComplete
Set to true when one of the generators finishes replaying its trace.
void dcacheRetryRecvd()
When data cache port receives a retry, schedule event dcacheNextEvent.
Port & getInstPort()
Used to get a reference to the icache port.
Tick traceOffset
This stores the time offset in the trace, which is taken away from the ready times of requests.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
gem5::TraceCPU::TraceStats traceStats
ElasticDataGen dcacheGen
Instance of ElasticDataGen to replay data read and write requests.
std::string instTraceFile
File names for input instruction and data traces.
const RequestorID dataRequestorID
Requestor id for data read and write requests.
Counter totalOps() const
Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are mod...
FixedRetryGen icacheGen
Instance of FixedRetryGen to replay instruction read requests.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
TraceCPU(const TraceCPUParams ¶ms)
void updateNumOps(uint64_t rob_num)
std::string dataTraceFile
uint64_t progressMsgThreshold
const Addr cacheLineSize
Cache the cache line size that we get from the system.
void dcacheRecvTimingResp(PacketPtr pkt)
When data cache port receives a response, this calls the dcache generator method handle to complete t...
void icacheRetryRecvd()
When instruction cache port receives a retry, schedule event icacheNextEvent.
EventFunctionWrapper dcacheNextEvent
Event for the control flow method schedDcacheNext()
static int numTraceCPUs
Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event...
EventFunctionWrapper icacheNextEvent
Event for the control flow method schedIcacheNext()
void schedDcacheNextEvent(Tick when)
Schedule event dcacheNextEvent at the given tick.
CountedExitEvent * execCompleteEvent
A CountedExitEvent which when serviced decrements the counter.
void checkAndSchedExitEvent()
This is called when either generator finishes executing from the trace.
void schedDcacheNext()
This is the control flow that uses the functionality of the dcacheGen to replay the trace.
void schedIcacheNext()
This is the control flow that uses the functionality of the icacheGen to replay the trace.
Counter value() const
Return the current value of this stat as its base type.
This is a simple scalar statistic, like a counter.
ClockedObject declaration and implementation.
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
const Params & params() const
double Counter
All counters are of 64-bit values.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
const PortID InvalidPortID
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
uint64_t Tick
Tick count type.
Declaration of the Packet class.
Declaration of a wrapper for protobuf output streams and input streams.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Declaration of Statistics objects.
statistics::Scalar numSplitReqs
statistics::Scalar numSendFailed
statistics::Scalar maxDependents
Stats for data memory accesses replayed.
statistics::Scalar numRetrySucceeded
statistics::Scalar numSendSucceeded
statistics::Scalar dataLastTick
Tick when ElasticDataGen completes execution.
ElasticDataGenStatGroup(statistics::Group *parent, const std::string &_name)
name is the extension to the name for these stats
statistics::Scalar numSOLoads
statistics::Scalar numSendAttempted
statistics::Scalar numSOStores
statistics::Scalar maxReadyListSize
Struct to store a ready-to-execute node and its execution tick.
Tick execTick
The tick at which the ready node must be executed.
NodeSeqNum seqNum
The sequence number of the ready node.
statistics::Scalar numSendFailed
statistics::Scalar numSendSucceeded
statistics::Scalar numSendAttempted
Stats for instruction accesses replayed.
FixedRetryGenStatGroup(statistics::Group *parent, const std::string &_name)
name is the extension to the name for these stats
statistics::Scalar numRetrySucceeded
statistics::Scalar instLastTick
Last simulated tick by the FixedRetryGen.
This struct stores a line in the trace file.
void clear()
Make this element invalid.
MemCmd cmd
Specifies if the request is to be a read or a write.
Addr addr
The address for the request.
Addr blocksize
The size of the access for the request.
Request::FlagsType flags
Potential request flags to use.
Tick tick
The time at which the request should be sent.
bool isValid() const
Check validity of this element.
statistics::Scalar numSchedDcacheEvent
statistics::Scalar numSchedIcacheEvent
statistics::Formula cpi
Stat for the CPI.
statistics::Scalar numCycles
Number of CPU cycles simulated.
TraceStats(TraceCPU *trace)
statistics::Scalar numOps
Stat for number of simulated micro-ops.