gem5  v21.1.0.2
trace_cpu.hh
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37 
38 #ifndef __CPU_TRACE_TRACE_CPU_HH__
39 #define __CPU_TRACE_TRACE_CPU_HH__
40 
41 #include <cstdint>
42 #include <list>
43 #include <queue>
44 #include <set>
45 #include <unordered_map>
46 
47 #include "base/statistics.hh"
48 #include "cpu/base.hh"
49 #include "debug/TraceCPUData.hh"
50 #include "debug/TraceCPUInst.hh"
51 #include "params/TraceCPU.hh"
52 #include "proto/inst_dep_record.pb.h"
53 #include "proto/packet.pb.h"
54 #include "proto/protoio.hh"
55 #include "sim/sim_events.hh"
56 
57 namespace gem5
58 {
59 
142 class TraceCPU : public BaseCPU
143 {
144 
145  public:
146  TraceCPU(const TraceCPUParams &params);
147 
148  void init();
149 
157  Counter totalInsts() const { return 0; }
158 
165  Counter totalOps() const { return traceStats.numOps.value(); }
166 
167  /*
168  * Set the no. of ops when elastic data generator completes executing a
169  * node.
170  */
171  void updateNumOps(uint64_t rob_num);
172 
173  /* Pure virtual function in BaseCPU. Do nothing. */
174  void wakeup(ThreadID tid=0) { return; }
175 
176  /*
177  * When resuming from checkpoint in FS mode, the TraceCPU takes over from
178  * the old cpu. This function overrides the takeOverFrom() function in the
179  * BaseCPU. It unbinds the ports of the old CPU and binds the ports of the
180  * TraceCPU.
181  */
182  void takeOverFrom(BaseCPU *oldCPU);
183 
188  void icacheRetryRecvd();
189 
194  void dcacheRetryRecvd();
195 
203 
209  void schedDcacheNextEvent(Tick when);
210 
211  protected:
212 
216  class IcachePort : public RequestPort
217  {
218  public:
221  RequestPort(_cpu->name() + ".icache_port", _cpu), owner(_cpu)
222  {}
223 
224  public:
233  bool recvTimingResp(PacketPtr pkt);
234 
241 
246  void recvReqRetry();
247 
248  private:
250  };
251 
255  class DcachePort : public RequestPort
256  {
257 
258  public:
261  RequestPort(_cpu->name() + ".dcache_port", _cpu), owner(_cpu)
262  {}
263 
264  public:
265 
273  bool recvTimingResp(PacketPtr pkt);
274 
281 
288 
293  void recvReqRetry();
294 
300  bool isSnooping() const { return true; }
301 
302  private:
304  };
305 
308 
311 
314 
317 
320 
328  {
329 
330  private:
331 
336  {
337 
340 
343 
346 
349 
352 
355 
361  bool isValid() const { return cmd != MemCmd::InvalidCmd; }
362 
367  };
368 
375  {
376  private:
377  // Input file stream for the protobuf trace
379 
380  public:
386  InputStream(const std::string& filename);
387 
392  void reset();
393 
402  bool read(TraceElement* element);
403  };
404 
405  public:
406  /* Constructor */
407  FixedRetryGen(TraceCPU& _owner, const std::string& _name,
408  RequestPort& _port, RequestorID requestor_id,
409  const std::string& trace_file) :
410  owner(_owner),
411  port(_port),
412  requestorId(requestor_id),
413  trace(trace_file),
414  genName(owner.name() + ".fixedretry." + _name),
415  retryPkt(nullptr),
416  delta(0),
417  traceComplete(false), fixedStats(&_owner, _name)
418  {
419  }
420 
427  Tick init();
428 
435  bool tryNext();
436 
438  const std::string& name() const { return genName; }
439 
453  bool send(Addr addr, unsigned size, const MemCmd& cmd,
454  Request::FlagsType flags, Addr pc);
455 
457  void exit();
458 
466  bool nextExecute();
467 
474  bool isTraceComplete() { return traceComplete; }
475 
476  int64_t tickDelta() { return delta; }
477 
478  private:
481 
484 
487 
490 
492  std::string genName;
493 
496 
502  int64_t delta;
503 
508 
511  protected:
513  {
516  const std::string& _name);
524  } fixedStats;
525 
526  };
527 
540  {
541  private:
543  typedef uint64_t NodeSeqNum;
544 
546  typedef uint64_t NodeRobNum;
547 
548  typedef ProtoMessage::InstDepRecord::RecordType RecordType;
549  typedef ProtoMessage::InstDepRecord Record;
550 
557  class GraphNode
558  {
559  public:
562 
565 
568 
571 
577 
580 
583 
585  uint32_t size;
586 
589 
592 
595 
597  uint64_t compDelay;
598 
604 
611 
613  bool isLoad() const { return (type == Record::LOAD); }
614 
616  bool isStore() const { return (type == Record::STORE); }
617 
619  bool isComp() const { return (type == Record::COMP); }
620 
622  bool removeRegDep(NodeSeqNum reg_dep);
623 
625  bool removeRobDep(NodeSeqNum rob_dep);
626 
628  bool removeDepOnInst(NodeSeqNum done_seq_num);
629 
631  bool
633  {
635  }
640  void writeElementAsTrace() const;
641 
643  std::string typeToStr() const;
644  };
645 
647  struct ReadyNode
648  {
651 
654  };
655 
662  {
663  public:
671  HardwareResource(uint16_t max_rob, uint16_t max_stores,
672  uint16_t max_loads);
673 
679  void occupy(const GraphNode* new_node);
680 
686  void release(const GraphNode* done_node);
687 
689  void releaseStoreBuffer();
690 
697  bool isAvailable(const GraphNode* new_node) const;
698 
706  bool awaitingResponse() const;
707 
709  void printOccupancy();
710 
711  private:
716  const uint16_t sizeROB;
717 
722  const uint16_t sizeStoreBuffer;
723 
728  const uint16_t sizeLoadBuffer;
729 
740  std::map<NodeSeqNum, NodeRobNum> inFlightNodes;
741 
744 
749 
754  };
755 
762  {
763  private:
766 
773  const double timeMultiplier;
774 
776  uint64_t microOpCount;
777 
782  uint32_t windowSize;
783 
784  public:
791  InputStream(const std::string& filename,
792  const double time_multiplier);
793 
798  void reset();
799 
809  bool read(GraphNode* element);
810 
812  uint32_t getWindowSize() const { return windowSize; }
813 
815  uint64_t getMicroOpCount() const { return microOpCount; }
816  };
817 
818  public:
819  /* Constructor */
820  ElasticDataGen(TraceCPU& _owner, const std::string& _name,
821  RequestPort& _port, RequestorID requestor_id,
822  const std::string& trace_file,
823  const TraceCPUParams &params) :
824  owner(_owner),
825  port(_port),
826  requestorId(requestor_id),
827  trace(trace_file, 1.0 / params.freqMultiplier),
828  genName(owner.name() + ".elastic." + _name),
829  retryPkt(nullptr),
830  traceComplete(false),
831  nextRead(false),
832  execComplete(false),
833  windowSize(trace.getWindowSize()),
834  hwResource(params.sizeROB, params.sizeStoreBuffer,
835  params.sizeLoadBuffer), elasticStats(&_owner, _name)
836  {
837  DPRINTF(TraceCPUData, "Window size in the trace is %d.\n",
838  windowSize);
839  }
840 
847  Tick init();
848 
856 
858  const std::string& name() const { return genName; }
859 
861  void exit();
862 
870  bool readNextWindow();
871 
880  template<typename T>
881  void addDepsOnParent(GraphNode *new_node, T& dep_list);
882 
892  void execute();
893 
904  PacketPtr executeMemReq(GraphNode* node_ptr);
905 
913  void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick);
914 
916  void printReadyList();
917 
923  void completeMemAccess(PacketPtr pkt);
924 
931  bool isExecComplete() const { return execComplete; }
932 
943  bool checkAndIssue(const GraphNode* node_ptr, bool first=true);
944 
946  uint64_t getMicroOpCount() const { return trace.getMicroOpCount(); }
947 
948  private:
951 
954 
957 
960 
962  std::string genName;
963 
966 
969 
971  bool nextRead;
972 
975 
985  const uint32_t windowSize;
986 
992 
994  std::unordered_map<NodeSeqNum, GraphNode*> depGraph;
995 
1003  std::queue<const GraphNode*> depFreeQueue;
1004 
1007 
1008  protected:
1009  // Defining the a stat group
1011  {
1014  const std::string& _name);
1027  } elasticStats;
1028  };
1029 
1032 
1035 
1042  void schedIcacheNext();
1043 
1049  void schedDcacheNext();
1050 
1053 
1056 
1061  void checkAndSchedExitEvent();
1062 
1065 
1073 
1080  static int numTraceCPUs;
1081 
1088 
1093  const bool enableEarlyExit;
1094 
1099  const uint64_t progressMsgInterval;
1100 
1101  /*
1102  * The progress msg threshold is kept updated to the next multiple of the
1103  * progress msg interval. As soon as the threshold is reached, an info
1104  * message is printed.
1105  */
1108  {
1109  TraceStats(TraceCPU *trace);
1112 
1118  } traceStats;
1119 
1120  public:
1121 
1123  Port &getInstPort() { return icachePort; }
1124 
1126  Port &getDataPort() { return dcachePort; }
1127 
1128 };
1129 
1130 } // namespace gem5
1131 
1132 #endif // __CPU_TRACE_TRACE_CPU_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::TraceCPU::ElasticDataGen::GraphNode::isLoad
bool isLoad() const
Is the node a load.
Definition: trace_cpu.hh:613
gem5::TraceCPU::dcacheRecvTimingResp
void dcacheRecvTimingResp(PacketPtr pkt)
When data cache port receives a response, this calls the dcache generator method handle to complete t...
Definition: trace_cpu.cc:1172
gem5::TraceCPU::ElasticDataGen::addToSortedReadyList
void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick)
Add a ready node to the readyList.
Definition: trace_cpu.cc:754
gem5::TraceCPU::FixedRetryGen::InputStream::trace
ProtoInputStream trace
Definition: trace_cpu.hh:378
gem5::TraceCPU::totalOps
Counter totalOps() const
Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are mod...
Definition: trace_cpu.hh:165
gem5::TraceCPU::TraceStats::TraceStats
TraceStats(TraceCPU *trace)
Definition: trace_cpu.cc:207
gem5::TraceCPU::ElasticDataGen::GraphNode::removeRegDep
bool removeRegDep(NodeSeqNum reg_dep)
Remove completed instruction from register dependency array.
Definition: trace_cpu.cc:1296
gem5::TraceCPU::FixedRetryGen::InputStream::read
bool read(TraceElement *element)
Attempt to read a trace element from the stream, and also notify the caller if the end of the file wa...
Definition: trace_cpu.cc:1403
gem5::TraceCPU::traceStats
gem5::TraceCPU::TraceStats traceStats
gem5::TraceCPU::checkAndSchedExitEvent
void checkAndSchedExitEvent()
This is called when either generator finishes executing from the trace.
Definition: trace_cpu.cc:188
gem5::TraceCPU::ElasticDataGen::GraphNode::removeRobDep
bool removeRobDep(NodeSeqNum rob_dep)
Remove completed instruction from order dependency array.
Definition: trace_cpu.cc:1314
gem5::TraceCPU::instTraceFile
std::string instTraceFile
File names for input instruction and data traces.
Definition: trace_cpu.hh:319
gem5::TraceCPU::FixedRetryGen::tickDelta
int64_t tickDelta()
Definition: trace_cpu.hh:476
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::dataLastTick
statistics::Scalar dataLastTick
Tick when ElasticDataGen completes execution.
Definition: trace_cpu.hh:1026
gem5::TraceCPU::ElasticDataGen::getMicroOpCount
uint64_t getMicroOpCount() const
Get number of micro-ops modelled in the TraceCPU replay.
Definition: trace_cpu.hh:946
gem5::TraceCPU::FixedRetryGen::init
Tick init()
Called from TraceCPU init().
Definition: trace_cpu.cc:989
gem5::TraceCPU::FixedRetryGen::retryPkt
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
Definition: trace_cpu.hh:495
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::maxReadyListSize
statistics::Scalar maxReadyListSize
Definition: trace_cpu.hh:1017
gem5::TraceCPU::ElasticDataGen::elasticStats
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup elasticStats
gem5::Port::name
const std::string name() const
Return port name (for DPRINTF).
Definition: port.hh:111
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::TraceCPU::schedDcacheNextEvent
void schedDcacheNextEvent(Tick when)
Schedule event dcacheNextEvent at the given tick.
Definition: trace_cpu.cc:1140
gem5::TraceCPU::ElasticDataGen::windowSize
const uint32_t windowSize
Window size within which to check for dependencies.
Definition: trace_cpu.hh:985
gem5::TraceCPU::ElasticDataGen::GraphNode::seqNum
NodeSeqNum seqNum
Instruction sequence number.
Definition: trace_cpu.hh:567
gem5::TraceCPU::getInstPort
Port & getInstPort()
Used to get a reference to the icache port.
Definition: trace_cpu.hh:1123
gem5::TraceCPU::totalInsts
Counter totalInsts() const
This is a pure virtual function in BaseCPU.
Definition: trace_cpu.hh:157
gem5::TraceCPU::ElasticDataGen::GraphNode::RegDepList
std::list< NodeSeqNum > RegDepList
Typedef for the list containing the register dependencies.
Definition: trace_cpu.hh:564
gem5::TraceCPU::ElasticDataGen::HardwareResource::occupy
void occupy(const GraphNode *new_node)
Occupy appropriate structures for an issued node.
Definition: trace_cpu.cc:842
gem5::TraceCPU::ElasticDataGen::NodeSeqNum
uint64_t NodeSeqNum
Node sequence number type.
Definition: trace_cpu.hh:543
gem5::TraceCPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU)
Load the state of a CPU from the previous CPU object, invoked on all new CPUs that are about to be sw...
Definition: trace_cpu.cc:97
gem5::TraceCPU::FixedRetryGen::exit
void exit()
Exit the FixedRetryGen.
Definition: trace_cpu.cc:1051
sim_events.hh
gem5::TraceCPU::FixedRetryGen::InputStream::reset
void reset()
Reset the stream such that it can be played once again.
Definition: trace_cpu.cc:1397
gem5::TraceCPU::ElasticDataGen::GraphNode::removeDepOnInst
bool removeDepOnInst(NodeSeqNum done_seq_num)
Check for all dependencies on completed inst.
Definition: trace_cpu.cc:1330
gem5::TraceCPU::FixedRetryGen::TraceElement::cmd
MemCmd cmd
Specifies if the request is to be a read or a write.
Definition: trace_cpu.hh:339
gem5::TraceCPU::FixedRetryGen::trace
InputStream trace
Input stream used for reading the input trace file.
Definition: trace_cpu.hh:489
gem5::TraceCPU::FixedRetryGen::TraceElement::pc
Addr pc
Instruction PC.
Definition: trace_cpu.hh:354
gem5::TraceCPU::ElasticDataGen::HardwareResource::numInFlightStores
uint16_t numInFlightStores
Number of ready stores for which request may or may not be sent.
Definition: trace_cpu.hh:753
gem5::TraceCPU::ElasticDataGen::InputStream::getWindowSize
uint32_t getWindowSize() const
Get window size from trace.
Definition: trace_cpu.hh:812
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numSOStores
statistics::Scalar numSOStores
Definition: trace_cpu.hh:1024
gem5::TraceCPU::IcachePort::IcachePort
IcachePort(TraceCPU *_cpu)
Default constructor.
Definition: trace_cpu.hh:220
gem5::TraceCPU::ElasticDataGen::InputStream::windowSize
uint32_t windowSize
The window size that is read from the header of the protobuf trace and used to process the dependency...
Definition: trace_cpu.hh:782
gem5::TraceCPU::DcachePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completi...
Definition: trace_cpu.cc:1179
gem5::TraceCPU::ElasticDataGen::readyList
std::list< ReadyNode > readyList
List of nodes that are ready to execute.
Definition: trace_cpu.hh:1006
gem5::TraceCPU::DcachePort::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
Definition: trace_cpu.hh:280
gem5::TraceCPU::FixedRetryGen::InputStream::InputStream
InputStream(const std::string &filename)
Create a trace input stream for a given file name.
Definition: trace_cpu.cc:1381
gem5::TraceCPU::ElasticDataGen::GraphNode::typeToStr
std::string typeToStr() const
Return string specifying the type of the node.
Definition: trace_cpu.cc:1376
gem5::TraceCPU::wakeup
void wakeup(ThreadID tid=0)
Definition: trace_cpu.hh:174
protoio.hh
gem5::TraceCPU::FixedRetryGen::TraceElement::addr
Addr addr
The address for the request.
Definition: trace_cpu.hh:342
gem5::TraceCPU::FixedRetryGen::TraceElement::isValid
bool isValid() const
Check validity of this element.
Definition: trace_cpu.hh:361
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup
Definition: trace_cpu.hh:512
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numSplitReqs
statistics::Scalar numSplitReqs
Definition: trace_cpu.hh:1022
gem5::TraceCPU::ElasticDataGen::Record
ProtoMessage::InstDepRecord Record
Definition: trace_cpu.hh:549
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
std::vector
STL vector class.
Definition: stl.hh:37
gem5::TraceCPU::ElasticDataGen::retryPkt
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
Definition: trace_cpu.hh:965
gem5::TraceCPU::TraceStats
Definition: trace_cpu.hh:1107
gem5::TraceCPU::ElasticDataGen::ReadyNode::seqNum
NodeSeqNum seqNum
The sequence number of the ready node.
Definition: trace_cpu.hh:650
gem5::TraceCPU::ElasticDataGen::completeMemAccess
void completeMemAccess(PacketPtr pkt)
When a load writeback is received, that is when the load completes, release the dependents on it.
Definition: trace_cpu.cc:687
gem5::TraceCPU::DcachePort::isSnooping
bool isSnooping() const
Required functionally.
Definition: trace_cpu.hh:300
gem5::TraceCPU::ElasticDataGen::addDepsOnParent
void addDepsOnParent(GraphNode *new_node, T &dep_list)
Iterate over the dependencies of a new node and add the new node to the list of dependents of the par...
Definition: trace_cpu.cc:350
gem5::TraceCPU::FixedRetryGen::TraceElement::blocksize
Addr blocksize
The size of the access for the request.
Definition: trace_cpu.hh:345
gem5::TraceCPU::ElasticDataGen::NodeRobNum
uint64_t NodeRobNum
Node ROB number type.
Definition: trace_cpu.hh:546
gem5::TraceCPU::ElasticDataGen::isExecComplete
bool isExecComplete() const
Returns the execComplete variable which is set when the last node is executed.
Definition: trace_cpu.hh:931
gem5::Request::FlagsType
uint64_t FlagsType
Definition: request.hh:100
gem5::TraceCPU::ElasticDataGen::exit
void exit()
Exit the ElasticDataGen.
Definition: trace_cpu.cc:291
gem5::TraceCPU::icacheRetryRecvd
void icacheRetryRecvd()
When instruction cache port receives a retry, schedule event icacheNextEvent.
Definition: trace_cpu.cc:1120
gem5::TraceCPU::ElasticDataGen::name
const std::string & name() const
Returns name of the ElasticDataGen instance.
Definition: trace_cpu.hh:858
gem5::TraceCPU::ElasticDataGen::HardwareResource::isAvailable
bool isAvailable(const GraphNode *new_node) const
Check if structures required to issue a node are free.
Definition: trace_cpu.cc:911
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numSendSucceeded
statistics::Scalar numSendSucceeded
Definition: trace_cpu.hh:1019
gem5::TraceCPU::schedIcacheNext
void schedIcacheNext()
This is the control flow that uses the functionality of the icacheGen to replay the trace.
Definition: trace_cpu.cc:148
gem5::TraceCPU::traceOffset
Tick traceOffset
This stores the time offset in the trace, which is taken away from the ready times of requests.
Definition: trace_cpu.hh:1072
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:77
gem5::TraceCPU::ElasticDataGen::HardwareResource::sizeStoreBuffer
const uint16_t sizeStoreBuffer
The size of store buffer.
Definition: trace_cpu.hh:722
gem5::MemCmd
Definition: packet.hh:75
gem5::TraceCPU::TraceStats::cpi
statistics::Formula cpi
Stat for the CPI.
Definition: trace_cpu.hh:1117
gem5::TraceCPU::ElasticDataGen::owner
TraceCPU & owner
Reference of the TraceCPU.
Definition: trace_cpu.hh:950
gem5::TraceCPU::ElasticDataGen::hwResource
HardwareResource hwResource
Hardware resources required to contain in-flight nodes and to throttle issuing of new nodes when reso...
Definition: trace_cpu.hh:991
gem5::TraceCPU::ElasticDataGen::InputStream::getMicroOpCount
uint64_t getMicroOpCount() const
Get number of micro-ops modelled in the TraceCPU replay.
Definition: trace_cpu.hh:815
gem5::TraceCPU::icacheNextEvent
EventFunctionWrapper icacheNextEvent
Event for the control flow method schedIcacheNext()
Definition: trace_cpu.hh:1052
gem5::Flags< FlagsType >
gem5::TraceCPU::ElasticDataGen::traceComplete
bool traceComplete
Set to true when end of trace is reached.
Definition: trace_cpu.hh:968
gem5::TraceCPU::FixedRetryGen::nextExecute
bool nextExecute()
Reads a line of the trace file.
Definition: trace_cpu.cc:1057
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup::numRetrySucceeded
statistics::Scalar numRetrySucceeded
Definition: trace_cpu.hh:521
gem5::TraceCPU::dcacheGen
ElasticDataGen dcacheGen
Instance of ElasticDataGen to replay data read and write requests.
Definition: trace_cpu.hh:1034
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup::numSendFailed
statistics::Scalar numSendFailed
Definition: trace_cpu.hh:520
gem5::TraceCPU::FixedRetryGen::genName
std::string genName
String to store the name of the FixedRetryGen.
Definition: trace_cpu.hh:492
gem5::TraceCPU::ElasticDataGen::GraphNode::virtAddr
Addr virtAddr
The virtual address for the request if any.
Definition: trace_cpu.hh:582
gem5::TraceCPU::ElasticDataGen::HardwareResource::release
void release(const GraphNode *done_node)
Release appropriate structures for a completed node.
Definition: trace_cpu.cc:861
gem5::TraceCPU::ElasticDataGen::executeMemReq
PacketPtr executeMemReq(GraphNode *node_ptr)
Creates a new request for a load or store assigning the request parameters.
Definition: trace_cpu.cc:571
gem5::TraceCPU::icacheGen
FixedRetryGen icacheGen
Instance of FixedRetryGen to replay instruction read requests.
Definition: trace_cpu.hh:1031
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::maxDependents
statistics::Scalar maxDependents
Stats for data memory accesses replayed.
Definition: trace_cpu.hh:1016
gem5::TraceCPU::ElasticDataGen::HardwareResource::numInFlightLoads
uint16_t numInFlightLoads
Number of ready loads for which request may or may not be sent.
Definition: trace_cpu.hh:748
gem5::TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace
void writeElementAsTrace() const
Write out element in trace-compatible format using debug flag TraceCPUData.
Definition: trace_cpu.cc:1345
gem5::TraceCPU::ElasticDataGen::GraphNode
The struct GraphNode stores an instruction in the trace file.
Definition: trace_cpu.hh:557
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::TraceCPU::ElasticDataGen::GraphNode::RobDepList
std::list< NodeSeqNum > RobDepList
Typedef for the list containing the ROB dependencies.
Definition: trace_cpu.hh:561
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::TraceCPU::FixedRetryGen::InputStream
The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based ...
Definition: trace_cpu.hh:374
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::TraceCPU::ElasticDataGen::InputStream::read
bool read(GraphNode *element)
Attempt to read a trace element from the stream, and also notify the caller if the end of the file wa...
Definition: trace_cpu.cc:1226
gem5::TraceCPU::ElasticDataGen::HardwareResource
The HardwareResource class models structures that hold the in-flight nodes.
Definition: trace_cpu.hh:661
gem5::TraceCPU::ElasticDataGen::GraphNode::robNum
NodeRobNum robNum
ROB occupancy number.
Definition: trace_cpu.hh:570
gem5::TraceCPU::ElasticDataGen::ReadyNode
Struct to store a ready-to-execute node and its execution tick.
Definition: trace_cpu.hh:647
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup::FixedRetryGenStatGroup
FixedRetryGenStatGroup(statistics::Group *parent, const std::string &_name)
name is the extension to the name for these stats
Definition: trace_cpu.cc:971
statistics.hh
gem5::TraceCPU::ElasticDataGen::GraphNode::type
RecordType type
Type of the node corresponding to the instruction modeled by it.
Definition: trace_cpu.hh:576
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::TraceCPU::FixedRetryGen::port
RequestPort & port
Reference of the port to be used to issue memory requests.
Definition: trace_cpu.hh:483
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup::numSendSucceeded
statistics::Scalar numSendSucceeded
Definition: trace_cpu.hh:519
gem5::TraceCPU::icachePort
IcachePort icachePort
Port to connect to L1 instruction cache.
Definition: trace_cpu.hh:307
gem5::TraceCPU::ElasticDataGen::adjustInitTraceOffset
void adjustInitTraceOffset(Tick &offset)
Adjust traceOffset based on what TraceCPU init() determines on comparing the offsets in the fetch req...
Definition: trace_cpu.cc:283
gem5::TraceCPU::ElasticDataGen::readNextWindow
bool readNextWindow()
Reads a line of the trace file.
Definition: trace_cpu.cc:297
gem5::TraceCPU::updateNumOps
void updateNumOps(uint64_t rob_num)
Definition: trace_cpu.cc:86
gem5::TraceCPU::instRequestorID
const RequestorID instRequestorID
Requestor id for instruction read requests.
Definition: trace_cpu.hh:313
gem5::TraceCPU::init
void init()
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: trace_cpu.cc:105
gem5::TraceCPU::DcachePort::recvReqRetry
void recvReqRetry()
Handle a retry signalled by the cache if data access failed in the first attempt.
Definition: trace_cpu.cc:1192
gem5::TraceCPU::ElasticDataGen::GraphNode::compDelay
uint64_t compDelay
Computational delay.
Definition: trace_cpu.hh:597
gem5::TraceCPU::ElasticDataGen::HardwareResource::releaseStoreBuffer
void releaseStoreBuffer()
Release store buffer entry for a completed store.
Definition: trace_cpu.cc:904
gem5::TraceCPU::ElasticDataGen::ReadyNode::execTick
Tick execTick
The tick at which the ready node must be executed.
Definition: trace_cpu.hh:653
gem5::TraceCPU::TraceStats::numOps
statistics::Scalar numOps
Stat for number of simulated micro-ops.
Definition: trace_cpu.hh:1114
gem5::TraceCPU::ElasticDataGen::GraphNode::isStrictlyOrdered
bool isStrictlyOrdered() const
Return true if node has a request which is strictly ordered.
Definition: trace_cpu.hh:632
gem5::TraceCPU::ElasticDataGen::trace
InputStream trace
Input stream used for reading the input trace file.
Definition: trace_cpu.hh:959
gem5::TraceCPU::ElasticDataGen::InputStream::microOpCount
uint64_t microOpCount
Count of committed ops read from trace plus the filtered ops.
Definition: trace_cpu.hh:776
gem5::TraceCPU::FixedRetryGen::tryNext
bool tryNext()
This tries to send current or retry packet and returns true if successfull.
Definition: trace_cpu.cc:1004
gem5::TraceCPU::FixedRetryGen::requestorId
const RequestorID requestorId
RequestorID used for the requests being sent.
Definition: trace_cpu.hh:486
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::BaseCPU
Definition: base.hh:107
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup::instLastTick
statistics::Scalar instLastTick
Last simulated tick by the FixedRetryGen.
Definition: trace_cpu.hh:523
gem5::TraceCPU::FixedRetryGen::TraceElement::clear
void clear()
Make this element invalid.
Definition: trace_cpu.hh:366
gem5::TraceCPU::FixedRetryGen::TraceElement
This struct stores a line in the trace file.
Definition: trace_cpu.hh:335
gem5::TraceCPU::IcachePort::recvTimingResp
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and simply delete the packet since instruction fetch requests are issued a...
Definition: trace_cpu.cc:1156
gem5::TraceCPU::ElasticDataGen::depGraph
std::unordered_map< NodeSeqNum, GraphNode * > depGraph
Store the depGraph of GraphNodes.
Definition: trace_cpu.hh:994
gem5::TraceCPU::FixedRetryGen::fixedStats
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup fixedStats
gem5::TraceCPU::IcachePort::recvTimingSnoopReq
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
Definition: trace_cpu.hh:240
gem5::TraceCPU::ElasticDataGen::GraphNode::flags
Request::Flags flags
Request flags if any.
Definition: trace_cpu.hh:588
gem5::TraceCPU::ElasticDataGen::InputStream::reset
void reset()
Reset the stream such that it can be played once again.
Definition: trace_cpu.cc:1220
gem5::CountedExitEvent
Definition: sim_events.hh:104
gem5::TraceCPU::FixedRetryGen::currElement
TraceElement currElement
Store an element read from the trace to send as the next packet.
Definition: trace_cpu.hh:510
gem5::TraceCPU::getDataPort
Port & getDataPort()
Used to get a reference to the dcache port.
Definition: trace_cpu.hh:1126
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup
Definition: trace_cpu.hh:1010
gem5::TraceCPU::FixedRetryGen::TraceElement::flags
Request::FlagsType flags
Potential request flags to use.
Definition: trace_cpu.hh:351
gem5::TraceCPU::ElasticDataGen::init
Tick init()
Called from TraceCPU init().
Definition: trace_cpu.cc:252
gem5::TraceCPU::ElasticDataGen::HardwareResource::sizeLoadBuffer
const uint16_t sizeLoadBuffer
The size of load buffer.
Definition: trace_cpu.hh:728
gem5::TraceCPU::FixedRetryGen::traceComplete
bool traceComplete
Set to true when end of trace is reached.
Definition: trace_cpu.hh:507
gem5::TraceCPU::TraceStats::numSchedIcacheEvent
statistics::Scalar numSchedIcacheEvent
Definition: trace_cpu.hh:1111
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numSOLoads
statistics::Scalar numSOLoads
Definition: trace_cpu.hh:1023
gem5::TraceCPU::FixedRetryGen::isTraceComplete
bool isTraceComplete()
Returns the traceComplete variable which is set when end of the input trace file is reached.
Definition: trace_cpu.hh:474
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup::numSendAttempted
statistics::Scalar numSendAttempted
Stats for instruction accesses replayed.
Definition: trace_cpu.hh:518
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::TraceCPU::enableEarlyExit
const bool enableEarlyExit
Exit when any one Trace CPU completes its execution.
Definition: trace_cpu.hh:1093
gem5::TraceCPU::ElasticDataGen::nextRead
bool nextRead
Set to true when the next window of instructions need to be read.
Definition: trace_cpu.hh:971
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numSendFailed
statistics::Scalar numSendFailed
Definition: trace_cpu.hh:1020
gem5::TraceCPU::FixedRetryGen
Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control...
Definition: trace_cpu.hh:327
gem5::TraceCPU::dcacheNextEvent
EventFunctionWrapper dcacheNextEvent
Event for the control flow method schedDcacheNext()
Definition: trace_cpu.hh:1055
gem5::TraceCPU::DcachePort::DcachePort
DcachePort(TraceCPU *_cpu)
Default constructor.
Definition: trace_cpu.hh:260
gem5::TraceCPU::ElasticDataGen::GraphNode::dependents
std::vector< GraphNode * > dependents
A vector of nodes dependent (outgoing) on this node.
Definition: trace_cpu.hh:610
gem5::TraceCPU::numTraceCPUs
static int numTraceCPUs
Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event...
Definition: trace_cpu.hh:1080
gem5::TraceCPU::ElasticDataGen::depFreeQueue
std::queue< const GraphNode * > depFreeQueue
Queue of dependency-free nodes that are pending issue because resources are not available.
Definition: trace_cpu.hh:1003
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::TraceCPU::schedDcacheNext
void schedDcacheNext()
This is the control flow that uses the functionality of the dcacheGen to replay the trace.
Definition: trace_cpu.cc:174
gem5::TraceCPU::FixedRetryGen::owner
TraceCPU & owner
Reference of the TraceCPU.
Definition: trace_cpu.hh:480
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numSendAttempted
statistics::Scalar numSendAttempted
Definition: trace_cpu.hh:1018
gem5::TraceCPU::DcachePort
DcachePort class that interfaces with L1 Data Cache.
Definition: trace_cpu.hh:255
gem5::TraceCPU::ElasticDataGen::ElasticDataGen
ElasticDataGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file, const TraceCPUParams &params)
Definition: trace_cpu.hh:820
gem5::TraceCPU::FixedRetryGen::TraceElement::tick
Tick tick
The time at which the request should be sent.
Definition: trace_cpu.hh:348
gem5::TraceCPU::ElasticDataGen::InputStream
The InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on ...
Definition: trace_cpu.hh:761
gem5::TraceCPU::ElasticDataGen::InputStream::trace
ProtoInputStream trace
Input file stream for the protobuf trace.
Definition: trace_cpu.hh:765
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::TraceCPU::IcachePort
IcachePort class that interfaces with L1 Instruction Cache.
Definition: trace_cpu.hh:216
gem5::TraceCPU::ElasticDataGen::HardwareResource::sizeROB
const uint16_t sizeROB
The size of the ROB used to throttle the max.
Definition: trace_cpu.hh:716
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::TraceCPU::ElasticDataGen::HardwareResource::awaitingResponse
bool awaitingResponse() const
Check if there are any outstanding requests, i.e.
Definition: trace_cpu.cc:955
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::TraceCPU::ElasticDataGen::GraphNode::pc
Addr pc
Instruction PC.
Definition: trace_cpu.hh:591
gem5::TraceCPU::DcachePort::owner
TraceCPU * owner
Definition: trace_cpu.hh:303
gem5::TraceCPU::ElasticDataGen::requestorId
const RequestorID requestorId
RequestorID used for the requests being sent.
Definition: trace_cpu.hh:956
gem5::TraceCPU::dataRequestorID
const RequestorID dataRequestorID
Requestor id for data read and write requests.
Definition: trace_cpu.hh:316
gem5::TraceCPU::execCompleteEvent
CountedExitEvent * execCompleteEvent
A CountedExitEvent which when serviced decrements the counter.
Definition: trace_cpu.hh:1087
gem5::TraceCPU::ElasticDataGen::genName
std::string genName
String to store the name of the FixedRetryGen.
Definition: trace_cpu.hh:962
gem5::TraceCPU::ElasticDataGen::execute
void execute()
This is the main execute function which consumes nodes from the sorted readyList.
Definition: trace_cpu.cc:375
gem5::TraceCPU::progressMsgThreshold
uint64_t progressMsgThreshold
Definition: trace_cpu.hh:1106
gem5::TraceCPU::dcacheRetryRecvd
void dcacheRetryRecvd()
When data cache port receives a retry, schedule event dcacheNextEvent.
Definition: trace_cpu.cc:1130
gem5::TraceCPU::progressMsgInterval
const uint64_t progressMsgInterval
Interval of committed instructions specified by the user at which a progress info message is printed.
Definition: trace_cpu.hh:1099
gem5::TraceCPU::ElasticDataGen
The elastic data memory request generator to read protobuf trace containing execution trace annotated...
Definition: trace_cpu.hh:539
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::TraceCPU::ElasticDataGen::HardwareResource::HardwareResource
HardwareResource(uint16_t max_rob, uint16_t max_stores, uint16_t max_loads)
Constructor that initializes the sizes of the structures.
Definition: trace_cpu.cc:831
gem5::TraceCPU::ElasticDataGen::HardwareResource::printOccupancy
void printOccupancy()
Print resource occupancy for debugging.
Definition: trace_cpu.cc:962
gem5::TraceCPU::oneTraceComplete
bool oneTraceComplete
Set to true when one of the generators finishes replaying its trace.
Definition: trace_cpu.hh:1064
gem5::TraceCPU::FixedRetryGen::send
bool send(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags, Addr pc)
Creates a new request assigning the request parameters passed by the arguments.
Definition: trace_cpu.cc:1088
gem5::TraceCPU::ElasticDataGen::InputStream::timeMultiplier
const double timeMultiplier
A multiplier for the compute delays in the trace to modulate the Trace CPU frequency either up or dow...
Definition: trace_cpu.hh:773
gem5::TraceCPU::IcachePort::recvReqRetry
void recvReqRetry()
Handle a retry signalled by the cache if instruction read failed in the first attempt.
Definition: trace_cpu.cc:1166
std::list< NodeSeqNum >
gem5::TraceCPU
The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.
Definition: trace_cpu.hh:142
gem5::TraceCPU::ElasticDataGen::InputStream::InputStream
InputStream(const std::string &filename, const double time_multiplier)
Create a trace input stream for a given file name.
Definition: trace_cpu.cc:1197
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MemCmd::InvalidCmd
@ InvalidCmd
Definition: packet.hh:85
gem5::TraceCPU::ElasticDataGen::checkAndIssue
bool checkAndIssue(const GraphNode *node_ptr, bool first=true)
Attempts to issue a node once the node's source dependencies are complete.
Definition: trace_cpu.cc:647
gem5::TraceCPU::TraceStats::numSchedDcacheEvent
statistics::Scalar numSchedDcacheEvent
Definition: trace_cpu.hh:1110
gem5::TraceCPU::ElasticDataGen::RecordType
ProtoMessage::InstDepRecord::RecordType RecordType
Definition: trace_cpu.hh:548
gem5::TraceCPU::ElasticDataGen::GraphNode::regDep
RegDepList regDep
List of register dependencies (incoming) if any.
Definition: trace_cpu.hh:603
gem5::TraceCPU::TraceCPU
TraceCPU(const TraceCPUParams &params)
Definition: trace_cpu.cc:49
gem5::TraceCPU::dataTraceFile
std::string dataTraceFile
Definition: trace_cpu.hh:319
gem5::TraceCPU::ElasticDataGen::GraphNode::size
uint32_t size
Size of request if any.
Definition: trace_cpu.hh:585
gem5::TraceCPU::ElasticDataGen::port
RequestPort & port
Reference of the port to be used to issue memory requests.
Definition: trace_cpu.hh:953
ProtoInputStream
A ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file...
Definition: protoio.hh:140
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::ElasticDataGenStatGroup
ElasticDataGenStatGroup(statistics::Group *parent, const std::string &_name)
name is the extension to the name for these stats
Definition: trace_cpu.cc:225
gem5::TraceCPU::ElasticDataGen::HardwareResource::inFlightNodes
std::map< NodeSeqNum, NodeRobNum > inFlightNodes
A map from the sequence number to the ROB number of the in- flight nodes.
Definition: trace_cpu.hh:740
gem5::TraceCPU::FixedRetryGen::name
const std::string & name() const
Returns name of the FixedRetryGen instance.
Definition: trace_cpu.hh:438
gem5::TraceCPU::FixedRetryGen::FixedRetryGen
FixedRetryGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file)
Definition: trace_cpu.hh:407
gem5::TraceCPU::ElasticDataGen::execComplete
bool execComplete
Set true when execution of trace is complete.
Definition: trace_cpu.hh:974
gem5::TraceCPU::ElasticDataGen::HardwareResource::oldestInFlightRobNum
NodeRobNum oldestInFlightRobNum
The ROB number of the oldest in-flight node.
Definition: trace_cpu.hh:743
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup::numRetrySucceeded
statistics::Scalar numRetrySucceeded
Definition: trace_cpu.hh:1021
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::TraceCPU::ElasticDataGen::GraphNode::robDep
RobDepList robDep
List of order dependencies.
Definition: trace_cpu.hh:594
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::TraceCPU::ElasticDataGen::printReadyList
void printReadyList()
Print readyList for debugging using debug flag TraceCPUData.
Definition: trace_cpu.cc:814
gem5::TraceCPU::ElasticDataGen::GraphNode::physAddr
Addr physAddr
The address for the request if any.
Definition: trace_cpu.hh:579
gem5::TraceCPU::ElasticDataGen::GraphNode::isStore
bool isStore() const
Is the node a store.
Definition: trace_cpu.hh:616
gem5::TraceCPU::DcachePort::recvFunctionalSnoop
void recvFunctionalSnoop(PacketPtr pkt)
Required functionally but do nothing.
Definition: trace_cpu.hh:287
gem5::TraceCPU::IcachePort::owner
TraceCPU * owner
Definition: trace_cpu.hh:249
gem5::TraceCPU::ElasticDataGen::GraphNode::isComp
bool isComp() const
Is the node a compute (non load/store) node.
Definition: trace_cpu.hh:619
gem5::TraceCPU::FixedRetryGen::delta
int64_t delta
Stores the difference in the send ticks of the current and last packets.
Definition: trace_cpu.hh:502
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::statistics::ScalarBase::value
Counter value() const
Return the current value of this stat as its base type.
Definition: statistics.hh:619
gem5::TraceCPU::dcachePort
DcachePort dcachePort
Port to connect to L1 data cache.
Definition: trace_cpu.hh:310

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