gem5 v24.0.0.0
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trace_cpu.hh
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1/*
2 * Copyright (c) 2013 - 2016, 2023 Arm Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __CPU_TRACE_TRACE_CPU_HH__
39#define __CPU_TRACE_TRACE_CPU_HH__
40
41#include <cstdint>
42#include <list>
43#include <queue>
44#include <set>
45#include <unordered_map>
46
47#include "base/statistics.hh"
48#include "debug/TraceCPUData.hh"
49#include "debug/TraceCPUInst.hh"
50#include "mem/packet.hh"
51#include "mem/port.hh"
52#include "mem/request.hh"
53#include "params/TraceCPU.hh"
54#include "proto/inst_dep_record.pb.h"
55#include "proto/packet.pb.h"
56#include "proto/protoio.hh"
57#include "sim/clocked_object.hh"
58#include "sim/sim_events.hh"
59
60namespace gem5
61{
62
145{
146
147 public:
148 TraceCPU(const TraceCPUParams &params);
149
150 void init() override;
151
158 Counter totalOps() const { return traceStats.numOps.value(); }
159
160 /*
161 * Set the no. of ops when elastic data generator completes executing a
162 * node.
163 */
164 void updateNumOps(uint64_t rob_num);
165
170 void icacheRetryRecvd();
171
176 void dcacheRetryRecvd();
177
185
191 void schedDcacheNextEvent(Tick when);
192
193 protected:
194
198 class IcachePort : public RequestPort
199 {
200 public:
203 RequestPort(_cpu->name() + ".icache_port"), owner(_cpu)
204 {}
205
206 public:
215 bool recvTimingResp(PacketPtr pkt);
216
223
228 void recvReqRetry();
229
230 private:
232 };
233
237 class DcachePort : public RequestPort
238 {
239
240 public:
243 RequestPort(_cpu->name() + ".dcache_port"), owner(_cpu)
244 {}
245
246 public:
247
255 bool recvTimingResp(PacketPtr pkt);
256
263
270
275 void recvReqRetry();
276
282 bool isSnooping() const { return true; }
283
284 private:
286 };
287
290
293
296
299
302
305
313 {
314
315 private:
316
321 {
322
325
328
331
334
337
340
346 bool isValid() const { return cmd != MemCmd::InvalidCmd; }
347
352 };
353
360 {
361 private:
362 // Input file stream for the protobuf trace
364
365 public:
371 InputStream(const std::string& filename);
372
377 void reset();
378
387 bool read(TraceElement* element);
388 };
389
390 public:
391 /* Constructor */
392 FixedRetryGen(TraceCPU& _owner, const std::string& _name,
393 RequestPort& _port, RequestorID requestor_id,
394 const std::string& trace_file) :
395 owner(_owner),
396 port(_port),
397 requestorId(requestor_id),
398 trace(trace_file),
399 genName(owner.name() + ".fixedretry." + _name),
400 retryPkt(nullptr),
401 delta(0),
402 traceComplete(false), fixedStats(&_owner, _name)
403 {
404 }
405
412 Tick init();
413
420 bool tryNext();
421
423 const std::string& name() const { return genName; }
424
438 bool send(Addr addr, unsigned size, const MemCmd& cmd,
440
442 void exit();
443
451 bool nextExecute();
452
460
461 int64_t tickDelta() { return delta; }
462
463 private:
466
469
472
475
477 std::string genName;
478
481
487 int64_t delta;
488
493
496 protected:
510
511 };
512
525 {
526 private:
528 typedef uint64_t NodeSeqNum;
529
531 typedef uint64_t NodeRobNum;
532
533 typedef ProtoMessage::InstDepRecord::RecordType RecordType;
534 typedef ProtoMessage::InstDepRecord Record;
535
543 {
544 public:
547
550
553
556
562
565
568
570 uint32_t size;
571
574
577
580
582 uint64_t compDelay;
583
589
596
598 bool isLoad() const { return (type == Record::LOAD); }
599
601 bool isStore() const { return (type == Record::STORE); }
602
604 bool isComp() const { return (type == Record::COMP); }
605
607 bool removeRegDep(NodeSeqNum reg_dep);
608
610 bool removeRobDep(NodeSeqNum rob_dep);
611
613 bool removeDepOnInst(NodeSeqNum done_seq_num);
614
616 bool
618 {
620 }
625 void writeElementAsTrace() const;
626
628 std::string typeToStr() const;
629 };
630
640
647 {
648 public:
656 HardwareResource(uint16_t max_rob, uint16_t max_stores,
657 uint16_t max_loads);
658
664 void occupy(const GraphNode* new_node);
665
671 void release(const GraphNode* done_node);
672
674 void releaseStoreBuffer();
675
682 bool isAvailable(const GraphNode* new_node) const;
683
691 bool awaitingResponse() const;
692
694 void printOccupancy();
695
696 private:
701 const uint16_t sizeROB;
702
707 const uint16_t sizeStoreBuffer;
708
713 const uint16_t sizeLoadBuffer;
714
725 std::map<NodeSeqNum, NodeRobNum> inFlightNodes;
726
729
734
739 };
740
747 {
748 private:
751
758 const double timeMultiplier;
759
761 uint64_t microOpCount;
762
767 uint32_t windowSize;
768
769 public:
776 InputStream(const std::string& filename,
777 const double time_multiplier);
778
783 void reset();
784
794 bool read(GraphNode* element);
795
797 uint32_t getWindowSize() const { return windowSize; }
798
800 uint64_t getMicroOpCount() const { return microOpCount; }
801 };
802
803 public:
804 /* Constructor */
805 ElasticDataGen(TraceCPU& _owner, const std::string& _name,
806 RequestPort& _port, RequestorID requestor_id,
807 const std::string& trace_file,
808 const TraceCPUParams &params) :
809 owner(_owner),
810 port(_port),
811 requestorId(requestor_id),
812 trace(trace_file, 1.0 / params.freqMultiplier),
813 genName(owner.name() + ".elastic." + _name),
814 retryPkt(nullptr),
815 traceComplete(false),
816 nextRead(false),
817 execComplete(false),
818 windowSize(trace.getWindowSize()),
819 hwResource(params.sizeROB, params.sizeStoreBuffer,
820 params.sizeLoadBuffer), elasticStats(&_owner, _name)
821 {
822 DPRINTF(TraceCPUData, "Window size in the trace is %d.\n",
823 windowSize);
824 }
825
832 Tick init();
833
841
843 const std::string& name() const { return genName; }
844
846 void exit();
847
855 bool readNextWindow();
856
865 template<typename T>
866 void addDepsOnParent(GraphNode *new_node, T& dep_list);
867
877 void execute();
878
889 PacketPtr executeMemReq(GraphNode* node_ptr);
890
898 void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick);
899
901 void printReadyList();
902
909
916 bool isExecComplete() const { return execComplete; }
917
928 bool checkAndIssue(const GraphNode* node_ptr, bool first=true);
929
931 uint64_t getMicroOpCount() const { return trace.getMicroOpCount(); }
932
933 private:
936
939
942
945
947 std::string genName;
948
951
954
957
960
970 const uint32_t windowSize;
971
977
979 std::unordered_map<NodeSeqNum, GraphNode*> depGraph;
980
988 std::queue<const GraphNode*> depFreeQueue;
989
992
993 protected:
994 // Defining the a stat group
1013 };
1014
1017
1020
1027 void schedIcacheNext();
1028
1034 void schedDcacheNext();
1035
1038
1041
1047
1050
1058
1065 static int numTraceCPUs;
1066
1073
1079
1084 const uint64_t progressMsgInterval;
1085
1086 /*
1087 * The progress msg threshold is kept updated to the next multiple of the
1088 * progress msg interval. As soon as the threshold is reached, an info
1089 * message is printed.
1090 */
1106
1107 public:
1108
1111
1114
1125 Port &getPort(const std::string &if_name,
1126 PortID idx=InvalidPortID) override;
1127};
1128
1129} // namespace gem5
1130
1131#endif // __CPU_TRACE_TRACE_CPU_HH__
#define DPRINTF(x,...)
Definition trace.hh:210
A ProtoInputStream wraps a coded stream, potentially with decompression, based on looking at the file...
Definition protoio.hh:141
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
const std::string _name
Definition named.hh:41
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Ports are used to interface objects to each other.
Definition port.hh:62
const std::string name() const
Return port name (for DPRINTF).
Definition port.hh:111
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition port.hh:136
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition request.hh:135
uint64_t FlagsType
Definition request.hh:100
DcachePort class that interfaces with L1 Data Cache.
Definition trace_cpu.hh:238
bool isSnooping() const
Required functionally.
Definition trace_cpu.hh:282
void recvFunctionalSnoop(PacketPtr pkt)
Required functionally but do nothing.
Definition trace_cpu.hh:269
DcachePort(TraceCPU *_cpu)
Default constructor.
Definition trace_cpu.hh:242
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and call dcacheRecvTimingResp() method of the dcacheGen to handle completi...
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
Definition trace_cpu.hh:262
void recvReqRetry()
Handle a retry signalled by the cache if data access failed in the first attempt.
The struct GraphNode stores an instruction in the trace file.
Definition trace_cpu.hh:543
bool isLoad() const
Is the node a load.
Definition trace_cpu.hh:598
bool isComp() const
Is the node a compute (non load/store) node.
Definition trace_cpu.hh:604
RecordType type
Type of the node corresponding to the instruction modeled by it.
Definition trace_cpu.hh:561
bool isStrictlyOrdered() const
Return true if node has a request which is strictly ordered.
Definition trace_cpu.hh:617
bool removeDepOnInst(NodeSeqNum done_seq_num)
Check for all dependencies on completed inst.
std::vector< GraphNode * > dependents
A vector of nodes dependent (outgoing) on this node.
Definition trace_cpu.hh:595
std::list< NodeSeqNum > RobDepList
Typedef for the list containing the ROB dependencies.
Definition trace_cpu.hh:546
bool removeRobDep(NodeSeqNum rob_dep)
Remove completed instruction from order dependency array.
std::list< NodeSeqNum > RegDepList
Typedef for the list containing the register dependencies.
Definition trace_cpu.hh:549
Request::Flags flags
Request flags if any.
Definition trace_cpu.hh:573
RegDepList regDep
List of register dependencies (incoming) if any.
Definition trace_cpu.hh:588
uint32_t size
Size of request if any.
Definition trace_cpu.hh:570
NodeRobNum robNum
ROB occupancy number.
Definition trace_cpu.hh:555
std::string typeToStr() const
Return string specifying the type of the node.
void writeElementAsTrace() const
Write out element in trace-compatible format using debug flag TraceCPUData.
RobDepList robDep
List of order dependencies.
Definition trace_cpu.hh:579
Addr physAddr
The address for the request if any.
Definition trace_cpu.hh:564
Addr virtAddr
The virtual address for the request if any.
Definition trace_cpu.hh:567
bool isStore() const
Is the node a store.
Definition trace_cpu.hh:601
uint64_t compDelay
Computational delay.
Definition trace_cpu.hh:582
NodeSeqNum seqNum
Instruction sequence number.
Definition trace_cpu.hh:552
bool removeRegDep(NodeSeqNum reg_dep)
Remove completed instruction from register dependency array.
The HardwareResource class models structures that hold the in-flight nodes.
Definition trace_cpu.hh:647
uint16_t numInFlightStores
Number of ready stores for which request may or may not be sent.
Definition trace_cpu.hh:738
const uint16_t sizeStoreBuffer
The size of store buffer.
Definition trace_cpu.hh:707
void occupy(const GraphNode *new_node)
Occupy appropriate structures for an issued node.
Definition trace_cpu.cc:836
void release(const GraphNode *done_node)
Release appropriate structures for a completed node.
Definition trace_cpu.cc:855
uint16_t numInFlightLoads
Number of ready loads for which request may or may not be sent.
Definition trace_cpu.hh:733
bool awaitingResponse() const
Check if there are any outstanding requests, i.e.
Definition trace_cpu.cc:949
NodeRobNum oldestInFlightRobNum
The ROB number of the oldest in-flight node.
Definition trace_cpu.hh:728
std::map< NodeSeqNum, NodeRobNum > inFlightNodes
A map from the sequence number to the ROB number of the in- flight nodes.
Definition trace_cpu.hh:725
void printOccupancy()
Print resource occupancy for debugging.
Definition trace_cpu.cc:956
const uint16_t sizeROB
The size of the ROB used to throttle the max.
Definition trace_cpu.hh:701
HardwareResource(uint16_t max_rob, uint16_t max_stores, uint16_t max_loads)
Constructor that initializes the sizes of the structures.
Definition trace_cpu.cc:825
const uint16_t sizeLoadBuffer
The size of load buffer.
Definition trace_cpu.hh:713
void releaseStoreBuffer()
Release store buffer entry for a completed store.
Definition trace_cpu.cc:898
bool isAvailable(const GraphNode *new_node) const
Check if structures required to issue a node are free.
Definition trace_cpu.cc:905
The InputStream encapsulates a trace file and the internal buffers and populates GraphNodes based on ...
Definition trace_cpu.hh:747
const double timeMultiplier
A multiplier for the compute delays in the trace to modulate the Trace CPU frequency either up or dow...
Definition trace_cpu.hh:758
ProtoInputStream trace
Input file stream for the protobuf trace.
Definition trace_cpu.hh:750
InputStream(const std::string &filename, const double time_multiplier)
Create a trace input stream for a given file name.
bool read(GraphNode *element)
Attempt to read a trace element from the stream, and also notify the caller if the end of the file wa...
uint32_t getWindowSize() const
Get window size from trace.
Definition trace_cpu.hh:797
uint32_t windowSize
The window size that is read from the header of the protobuf trace and used to process the dependency...
Definition trace_cpu.hh:767
void reset()
Reset the stream such that it can be played once again.
uint64_t microOpCount
Count of committed ops read from trace plus the filtered ops.
Definition trace_cpu.hh:761
uint64_t getMicroOpCount() const
Get number of micro-ops modelled in the TraceCPU replay.
Definition trace_cpu.hh:800
The elastic data memory request generator to read protobuf trace containing execution trace annotated...
Definition trace_cpu.hh:525
const uint32_t windowSize
Window size within which to check for dependencies.
Definition trace_cpu.hh:970
uint64_t NodeRobNum
Node ROB number type.
Definition trace_cpu.hh:531
bool readNextWindow()
Reads a line of the trace file.
Definition trace_cpu.cc:291
PacketPtr executeMemReq(GraphNode *node_ptr)
Creates a new request for a load or store assigning the request parameters.
Definition trace_cpu.cc:565
ProtoMessage::InstDepRecord::RecordType RecordType
Definition trace_cpu.hh:533
void printReadyList()
Print readyList for debugging using debug flag TraceCPUData.
Definition trace_cpu.cc:808
bool isExecComplete() const
Returns the execComplete variable which is set when the last node is executed.
Definition trace_cpu.hh:916
TraceCPU & owner
Reference of the TraceCPU.
Definition trace_cpu.hh:935
const RequestorID requestorId
RequestorID used for the requests being sent.
Definition trace_cpu.hh:941
Tick init()
Called from TraceCPU init().
Definition trace_cpu.cc:246
ProtoMessage::InstDepRecord Record
Definition trace_cpu.hh:534
uint64_t NodeSeqNum
Node sequence number type.
Definition trace_cpu.hh:528
void adjustInitTraceOffset(Tick &offset)
Adjust traceOffset based on what TraceCPU init() determines on comparing the offsets in the fetch req...
Definition trace_cpu.cc:277
bool checkAndIssue(const GraphNode *node_ptr, bool first=true)
Attempts to issue a node once the node's source dependencies are complete.
Definition trace_cpu.cc:641
std::list< ReadyNode > readyList
List of nodes that are ready to execute.
Definition trace_cpu.hh:991
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
Definition trace_cpu.hh:950
const std::string & name() const
Returns name of the ElasticDataGen instance.
Definition trace_cpu.hh:843
bool traceComplete
Set to true when end of trace is reached.
Definition trace_cpu.hh:953
void exit()
Exit the ElasticDataGen.
Definition trace_cpu.cc:285
ElasticDataGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file, const TraceCPUParams &params)
Definition trace_cpu.hh:805
bool nextRead
Set to true when the next window of instructions need to be read.
Definition trace_cpu.hh:956
std::queue< const GraphNode * > depFreeQueue
Queue of dependency-free nodes that are pending issue because resources are not available.
Definition trace_cpu.hh:988
gem5::TraceCPU::ElasticDataGen::ElasticDataGenStatGroup elasticStats
std::unordered_map< NodeSeqNum, GraphNode * > depGraph
Store the depGraph of GraphNodes.
Definition trace_cpu.hh:979
uint64_t getMicroOpCount() const
Get number of micro-ops modelled in the TraceCPU replay.
Definition trace_cpu.hh:931
std::string genName
String to store the name of the FixedRetryGen.
Definition trace_cpu.hh:947
void addDepsOnParent(GraphNode *new_node, T &dep_list)
Iterate over the dependencies of a new node and add the new node to the list of dependents of the par...
Definition trace_cpu.cc:344
bool execComplete
Set true when execution of trace is complete.
Definition trace_cpu.hh:959
RequestPort & port
Reference of the port to be used to issue memory requests.
Definition trace_cpu.hh:938
HardwareResource hwResource
Hardware resources required to contain in-flight nodes and to throttle issuing of new nodes when reso...
Definition trace_cpu.hh:976
void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick)
Add a ready node to the readyList.
Definition trace_cpu.cc:748
InputStream trace
Input stream used for reading the input trace file.
Definition trace_cpu.hh:944
void execute()
This is the main execute function which consumes nodes from the sorted readyList.
Definition trace_cpu.cc:369
void completeMemAccess(PacketPtr pkt)
When a load writeback is received, that is when the load completes, release the dependents on it.
Definition trace_cpu.cc:681
The InputStream encapsulates a trace file and the internal buffers and populates TraceElements based ...
Definition trace_cpu.hh:360
InputStream(const std::string &filename)
Create a trace input stream for a given file name.
bool read(TraceElement *element)
Attempt to read a trace element from the stream, and also notify the caller if the end of the file wa...
void reset()
Reset the stream such that it can be played once again.
Generator to read protobuf trace containing memory requests at fixed timestamps, perform flow control...
Definition trace_cpu.hh:313
TraceCPU & owner
Reference of the TraceCPU.
Definition trace_cpu.hh:465
int64_t delta
Stores the difference in the send ticks of the current and last packets.
Definition trace_cpu.hh:487
Tick init()
Called from TraceCPU init().
Definition trace_cpu.cc:983
const RequestorID requestorId
RequestorID used for the requests being sent.
Definition trace_cpu.hh:471
FixedRetryGen(TraceCPU &_owner, const std::string &_name, RequestPort &_port, RequestorID requestor_id, const std::string &trace_file)
Definition trace_cpu.hh:392
gem5::TraceCPU::FixedRetryGen::FixedRetryGenStatGroup fixedStats
TraceElement currElement
Store an element read from the trace to send as the next packet.
Definition trace_cpu.hh:495
bool nextExecute()
Reads a line of the trace file.
bool traceComplete
Set to true when end of trace is reached.
Definition trace_cpu.hh:492
const std::string & name() const
Returns name of the FixedRetryGen instance.
Definition trace_cpu.hh:423
PacketPtr retryPkt
PacketPtr used to store the packet to retry.
Definition trace_cpu.hh:480
bool isTraceComplete()
Returns the traceComplete variable which is set when end of the input trace file is reached.
Definition trace_cpu.hh:459
std::string genName
String to store the name of the FixedRetryGen.
Definition trace_cpu.hh:477
void exit()
Exit the FixedRetryGen.
RequestPort & port
Reference of the port to be used to issue memory requests.
Definition trace_cpu.hh:468
InputStream trace
Input stream used for reading the input trace file.
Definition trace_cpu.hh:474
bool send(Addr addr, unsigned size, const MemCmd &cmd, Request::FlagsType flags, Addr pc)
Creates a new request assigning the request parameters passed by the arguments.
bool tryNext()
This tries to send current or retry packet and returns true if successfull.
Definition trace_cpu.cc:998
IcachePort class that interfaces with L1 Instruction Cache.
Definition trace_cpu.hh:199
void recvTimingSnoopReq(PacketPtr pkt)
Required functionally but do nothing.
Definition trace_cpu.hh:222
IcachePort(TraceCPU *_cpu)
Default constructor.
Definition trace_cpu.hh:202
void recvReqRetry()
Handle a retry signalled by the cache if instruction read failed in the first attempt.
bool recvTimingResp(PacketPtr pkt)
Receive the timing reponse and simply delete the packet since instruction fetch requests are issued a...
The trace cpu replays traces generated using the elastic trace probe attached to the O3 CPU model.
Definition trace_cpu.hh:145
const uint64_t progressMsgInterval
Interval of committed instructions specified by the user at which a progress info message is printed.
Port & getDataPort()
Used to get a reference to the dcache port.
DcachePort dcachePort
Port to connect to L1 data cache.
Definition trace_cpu.hh:295
const bool enableEarlyExit
Exit when any one Trace CPU completes its execution.
IcachePort icachePort
Port to connect to L1 instruction cache.
Definition trace_cpu.hh:292
const RequestorID instRequestorID
Requestor id for instruction read requests.
Definition trace_cpu.hh:298
bool oneTraceComplete
Set to true when one of the generators finishes replaying its trace.
void dcacheRetryRecvd()
When data cache port receives a retry, schedule event dcacheNextEvent.
Port & getInstPort()
Used to get a reference to the icache port.
Tick traceOffset
This stores the time offset in the trace, which is taken away from the ready times of requests.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition trace_cpu.cc:99
gem5::TraceCPU::TraceStats traceStats
ElasticDataGen dcacheGen
Instance of ElasticDataGen to replay data read and write requests.
std::string instTraceFile
File names for input instruction and data traces.
Definition trace_cpu.hh:304
const RequestorID dataRequestorID
Requestor id for data read and write requests.
Definition trace_cpu.hh:301
Counter totalOps() const
Return totalOps as the number of committed micro-ops plus the speculatively issued loads that are mod...
Definition trace_cpu.hh:158
FixedRetryGen icacheGen
Instance of FixedRetryGen to replay instruction read requests.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port on this CPU.
TraceCPU(const TraceCPUParams &params)
Definition trace_cpu.cc:50
void updateNumOps(uint64_t rob_num)
Definition trace_cpu.cc:88
std::string dataTraceFile
Definition trace_cpu.hh:304
uint64_t progressMsgThreshold
const Addr cacheLineSize
Cache the cache line size that we get from the system.
Definition trace_cpu.hh:289
void dcacheRecvTimingResp(PacketPtr pkt)
When data cache port receives a response, this calls the dcache generator method handle to complete t...
void icacheRetryRecvd()
When instruction cache port receives a retry, schedule event icacheNextEvent.
EventFunctionWrapper dcacheNextEvent
Event for the control flow method schedDcacheNext()
static int numTraceCPUs
Number of Trace CPUs in the system used as a shared variable and passed to the CountedExitEvent event...
EventFunctionWrapper icacheNextEvent
Event for the control flow method schedIcacheNext()
void schedDcacheNextEvent(Tick when)
Schedule event dcacheNextEvent at the given tick.
CountedExitEvent * execCompleteEvent
A CountedExitEvent which when serviced decrements the counter.
void checkAndSchedExitEvent()
This is called when either generator finishes executing from the trace.
Definition trace_cpu.cc:182
void schedDcacheNext()
This is the control flow that uses the functionality of the dcacheGen to replay the trace.
Definition trace_cpu.cc:168
void schedIcacheNext()
This is the control flow that uses the functionality of the icacheGen to replay the trace.
Definition trace_cpu.cc:142
A formula for statistics that is calculated when printed.
Statistics container.
Definition group.hh:93
Counter value() const
Return the current value of this stat as its base type.
This is a simple scalar statistic, like a counter.
STL list class.
Definition stl.hh:51
STL vector class.
Definition stl.hh:37
ClockedObject declaration and implementation.
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition flags.hh:83
const Params & params() const
uint8_t flags
Definition helpers.cc:87
Port Object Declaration.
Bitfield< 23, 0 > offset
Definition types.hh:144
Bitfield< 4 > pc
Bitfield< 3 > addr
Definition types.hh:84
double Counter
All counters are of 64-bit values.
Definition types.hh:46
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
const PortID InvalidPortID
Definition types.hh:246
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
uint16_t RequestorID
Definition request.hh:95
Declaration of the Packet class.
Declaration of a wrapper for protobuf output streams and input streams.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Declaration of Statistics objects.
statistics::Scalar maxDependents
Stats for data memory accesses replayed.
statistics::Scalar dataLastTick
Tick when ElasticDataGen completes execution.
ElasticDataGenStatGroup(statistics::Group *parent, const std::string &_name)
name is the extension to the name for these stats
Definition trace_cpu.cc:219
Struct to store a ready-to-execute node and its execution tick.
Definition trace_cpu.hh:633
Tick execTick
The tick at which the ready node must be executed.
Definition trace_cpu.hh:638
NodeSeqNum seqNum
The sequence number of the ready node.
Definition trace_cpu.hh:635
statistics::Scalar numSendAttempted
Stats for instruction accesses replayed.
Definition trace_cpu.hh:503
FixedRetryGenStatGroup(statistics::Group *parent, const std::string &_name)
name is the extension to the name for these stats
Definition trace_cpu.cc:965
statistics::Scalar instLastTick
Last simulated tick by the FixedRetryGen.
Definition trace_cpu.hh:508
This struct stores a line in the trace file.
Definition trace_cpu.hh:321
void clear()
Make this element invalid.
Definition trace_cpu.hh:351
MemCmd cmd
Specifies if the request is to be a read or a write.
Definition trace_cpu.hh:324
Addr addr
The address for the request.
Definition trace_cpu.hh:327
Addr blocksize
The size of the access for the request.
Definition trace_cpu.hh:330
Request::FlagsType flags
Potential request flags to use.
Definition trace_cpu.hh:336
Tick tick
The time at which the request should be sent.
Definition trace_cpu.hh:333
bool isValid() const
Check validity of this element.
Definition trace_cpu.hh:346
statistics::Scalar numSchedDcacheEvent
statistics::Scalar numSchedIcacheEvent
statistics::Formula cpi
Stat for the CPI.
statistics::Scalar numCycles
Number of CPU cycles simulated.
TraceStats(TraceCPU *trace)
Definition trace_cpu.cc:201
statistics::Scalar numOps
Stat for number of simulated micro-ops.

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