trace_cpu.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2013 - 2016 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_TRACE_TRACE_CPU_HH__
#define __CPU_TRACE_TRACE_CPU_HH__
 
#include <cstdint>
#include <list>
#include <queue>
#include <set>
#include <unordered_map>
 
#include "base/statistics.hh"
#include "cpu/base.hh"
#include "debug/TraceCPUData.hh"
#include "debug/TraceCPUInst.hh"
#include "params/TraceCPU.hh"
#include "proto/inst_dep_record.pb.h"
#include "proto/packet.pb.h"
#include "proto/protoio.hh"
#include "sim/sim_events.hh"
 
namespace gem5
{
 
class TraceCPU : public BaseCPU
{
 
  public:
    TraceCPU(const TraceCPUParams &params);
 
    void init();
 
    Counter totalInsts() const { return 0; }
 
    Counter totalOps() const { return traceStats.numOps.value(); }
 
    /*
     * Set the no. of ops when elastic data generator completes executing a
     * node.
     */
    void updateNumOps(uint64_t rob_num);
 
    /* Pure virtual function in BaseCPU. Do nothing. */
    void wakeup(ThreadID tid=0) { return; }
 
    /*
     * When resuming from checkpoint in FS mode, the TraceCPU takes over from
     * the old cpu. This function overrides the takeOverFrom() function in the
     * BaseCPU. It unbinds the ports of the old CPU and binds the ports of the
     * TraceCPU.
     */
    void takeOverFrom(BaseCPU *oldCPU);
 
    void icacheRetryRecvd();
 
    void dcacheRetryRecvd();
 
    void dcacheRecvTimingResp(PacketPtr pkt);
 
    void schedDcacheNextEvent(Tick when);
 
  protected:
 
    class IcachePort : public RequestPort
    {
      public:
        IcachePort(TraceCPU* _cpu) :
            RequestPort(_cpu->name() + ".icache_port", _cpu), owner(_cpu)
        {}
 
      public:
        bool recvTimingResp(PacketPtr pkt);
 
        void recvTimingSnoopReq(PacketPtr pkt) {}
 
        void recvReqRetry();
 
      private:
        TraceCPU* owner;
    };
 
    class DcachePort : public RequestPort
    {
 
      public:
        DcachePort(TraceCPU* _cpu) :
            RequestPort(_cpu->name() + ".dcache_port", _cpu), owner(_cpu)
        {}
 
      public:
 
        bool recvTimingResp(PacketPtr pkt);
 
        void recvTimingSnoopReq(PacketPtr pkt) {}
 
        void recvFunctionalSnoop(PacketPtr pkt) {}
 
        void recvReqRetry();
 
        bool isSnooping() const { return true; }
 
      private:
        TraceCPU* owner;
    };
 
    IcachePort icachePort;
 
    DcachePort dcachePort;
 
    const RequestorID instRequestorID;
 
    const RequestorID dataRequestorID;
 
    std::string instTraceFile, dataTraceFile;
 
    class FixedRetryGen
    {
 
      private:
 
        struct TraceElement
        {
 
            MemCmd cmd;
 
            Addr addr;
 
            Addr blocksize;
 
            Tick tick;
 
            Request::FlagsType flags;
 
            Addr pc;
 
            bool isValid() const { return cmd != MemCmd::InvalidCmd; }
 
            void clear() { cmd = MemCmd::InvalidCmd; }
        };
 
        class InputStream
        {
          private:
            // Input file stream for the protobuf trace
            ProtoInputStream trace;
 
          public:
            InputStream(const std::string& filename);
 
            void reset();
 
            bool read(TraceElement* element);
        };
 
      public:
        /* Constructor */
        FixedRetryGen(TraceCPU& _owner, const std::string& _name,
                   RequestPort& _port, RequestorID requestor_id,
                   const std::string& trace_file) :
            owner(_owner),
            port(_port),
            requestorId(requestor_id),
            trace(trace_file),
            genName(owner.name() + ".fixedretry." + _name),
            retryPkt(nullptr),
            delta(0),
            traceComplete(false), fixedStats(&_owner, _name)
        {
        }
 
        Tick init();
 
        bool tryNext();
 
        const std::string& name() const { return genName; }
 
        bool send(Addr addr, unsigned size, const MemCmd& cmd,
              Request::FlagsType flags, Addr pc);
 
        void exit();
 
        bool nextExecute();
 
        bool isTraceComplete() { return traceComplete; }
 
        int64_t tickDelta() { return delta; }
 
      private:
        TraceCPU& owner;
 
        RequestPort& port;
 
        const RequestorID requestorId;
 
        InputStream trace;
 
        std::string genName;
 
        PacketPtr retryPkt;
 
        int64_t delta;
 
        bool traceComplete;
 
        TraceElement currElement;
      protected:
        struct FixedRetryGenStatGroup : public statistics::Group
        {
            FixedRetryGenStatGroup(statistics::Group *parent,
                                   const std::string& _name);
            statistics::Scalar numSendAttempted;
            statistics::Scalar numSendSucceeded;
            statistics::Scalar numSendFailed;
            statistics::Scalar numRetrySucceeded;
            statistics::Scalar instLastTick;
        } fixedStats;
 
    };
 
    class ElasticDataGen
    {
      private:
        typedef uint64_t NodeSeqNum;
 
        typedef uint64_t NodeRobNum;
 
        typedef ProtoMessage::InstDepRecord::RecordType RecordType;
        typedef ProtoMessage::InstDepRecord Record;
 
        class GraphNode
        {
          public:
            typedef std::list<NodeSeqNum> RobDepList;
 
            typedef std::list<NodeSeqNum> RegDepList;
 
            NodeSeqNum seqNum;
 
            NodeRobNum robNum;
 
            RecordType type;
 
            Addr physAddr;
 
            Addr virtAddr;
 
            uint32_t size;
 
            Request::Flags flags;
 
            Addr pc;
 
            RobDepList robDep;
 
            uint64_t compDelay;
 
            RegDepList regDep;
 
            std::vector<GraphNode *> dependents;
 
            bool isLoad() const { return (type == Record::LOAD); }
 
            bool isStore() const { return (type == Record::STORE); }
 
            bool isComp() const { return (type == Record::COMP); }
 
            bool removeRegDep(NodeSeqNum reg_dep);
 
            bool removeRobDep(NodeSeqNum rob_dep);
 
            bool removeDepOnInst(NodeSeqNum done_seq_num);
 
            bool
            isStrictlyOrdered() const
            {
                return (flags.isSet(Request::STRICT_ORDER));
            }
            void writeElementAsTrace() const;
 
            std::string typeToStr() const;
        };
 
        struct ReadyNode
        {
            NodeSeqNum seqNum;
 
            Tick execTick;
        };
 
        class HardwareResource
        {
          public:
            HardwareResource(uint16_t max_rob, uint16_t max_stores,
                                uint16_t max_loads);
 
            void occupy(const GraphNode* new_node);
 
            void release(const GraphNode* done_node);
 
            void releaseStoreBuffer();
 
            bool isAvailable(const GraphNode* new_node) const;
 
            bool awaitingResponse() const;
 
            void printOccupancy();
 
          private:
            const uint16_t sizeROB;
 
            const uint16_t sizeStoreBuffer;
 
            const uint16_t sizeLoadBuffer;
 
            std::map<NodeSeqNum, NodeRobNum> inFlightNodes;
 
            NodeRobNum oldestInFlightRobNum;
 
            uint16_t numInFlightLoads;
 
            uint16_t numInFlightStores;
        };
 
        class InputStream
        {
          private:
            ProtoInputStream trace;
 
            const double timeMultiplier;
 
            uint64_t microOpCount;
 
            uint32_t windowSize;
 
          public:
            InputStream(const std::string& filename,
                        const double time_multiplier);
 
            void reset();
 
            bool read(GraphNode* element);
 
            uint32_t getWindowSize() const { return windowSize; }
 
            uint64_t getMicroOpCount() const { return microOpCount; }
        };
 
        public:
        /* Constructor */
        ElasticDataGen(TraceCPU& _owner, const std::string& _name,
                   RequestPort& _port, RequestorID requestor_id,
                   const std::string& trace_file,
                   const TraceCPUParams &params) :
            owner(_owner),
            port(_port),
            requestorId(requestor_id),
            trace(trace_file, 1.0 / params.freqMultiplier),
            genName(owner.name() + ".elastic." + _name),
            retryPkt(nullptr),
            traceComplete(false),
            nextRead(false),
            execComplete(false),
            windowSize(trace.getWindowSize()),
            hwResource(params.sizeROB, params.sizeStoreBuffer,
                       params.sizeLoadBuffer), elasticStats(&_owner, _name)
        {
            DPRINTF(TraceCPUData, "Window size in the trace is %d.\n",
                    windowSize);
        }
 
        Tick init();
 
        void adjustInitTraceOffset(Tick& offset);
 
        const std::string& name() const { return genName; }
 
        void exit();
 
        bool readNextWindow();
 
        template<typename T>
        void addDepsOnParent(GraphNode *new_node, T& dep_list);
 
        void execute();
 
        PacketPtr executeMemReq(GraphNode* node_ptr);
 
        void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick);
 
        void printReadyList();
 
        void completeMemAccess(PacketPtr pkt);
 
        bool isExecComplete() const { return execComplete; }
 
        bool checkAndIssue(const GraphNode* node_ptr, bool first=true);
 
        uint64_t getMicroOpCount() const { return trace.getMicroOpCount(); }
 
      private:
        TraceCPU& owner;
 
        RequestPort& port;
 
        const RequestorID requestorId;
 
        InputStream trace;
 
        std::string genName;
 
        PacketPtr retryPkt;
 
        bool traceComplete;
 
        bool nextRead;
 
        bool execComplete;
 
        const uint32_t windowSize;
 
        HardwareResource hwResource;
 
        std::unordered_map<NodeSeqNum, GraphNode*> depGraph;
 
        std::queue<const GraphNode*> depFreeQueue;
 
        std::list<ReadyNode> readyList;
 
      protected:
        // Defining the a stat group
        struct ElasticDataGenStatGroup : public statistics::Group
        {
            ElasticDataGenStatGroup(statistics::Group *parent,
                                    const std::string& _name);
            statistics::Scalar maxDependents;
            statistics::Scalar maxReadyListSize;
            statistics::Scalar numSendAttempted;
            statistics::Scalar numSendSucceeded;
            statistics::Scalar numSendFailed;
            statistics::Scalar numRetrySucceeded;
            statistics::Scalar numSplitReqs;
            statistics::Scalar numSOLoads;
            statistics::Scalar numSOStores;
            statistics::Scalar dataLastTick;
        } elasticStats;
    };
 
    FixedRetryGen icacheGen;
 
    ElasticDataGen dcacheGen;
 
    void schedIcacheNext();
 
    void schedDcacheNext();
 
    EventFunctionWrapper icacheNextEvent;
 
    EventFunctionWrapper dcacheNextEvent;
 
    void checkAndSchedExitEvent();
 
    bool oneTraceComplete;
 
    Tick traceOffset;
 
    static int numTraceCPUs;
 
    CountedExitEvent *execCompleteEvent;
 
    const bool enableEarlyExit;
 
    const uint64_t progressMsgInterval;
 
    /*
     * The progress msg threshold is kept updated to the next multiple of the
     * progress msg interval. As soon as the threshold is reached, an info
     * message is printed.
     */
    uint64_t progressMsgThreshold;
    struct TraceStats : public statistics::Group
    {
        TraceStats(TraceCPU *trace);
        statistics::Scalar numSchedDcacheEvent;
        statistics::Scalar numSchedIcacheEvent;
 
        statistics::Scalar numOps;
        statistics::Formula cpi;
    } traceStats;
 
  public:
 
    Port &getInstPort() { return icachePort; }
 
    Port &getDataPort() { return dcachePort; }
 
};
 
} // namespace gem5
 
#endif // __CPU_TRACE_TRACE_CPU_HH__