gem5  v22.1.0.0
gem5::X86IdeController Member List

This is the complete list of members for gem5::X86IdeController, including all inherited members.

_busAddrgem5::PciDeviceprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
activegem5::IdeControllerprivate
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
BARsgem5::PciDeviceprotected
BitUnion8(BMIStatusReg) Bitfield< 6 > dmaCap0gem5::IdeControllerprivate
busAddr() constgem5::PciDeviceinline
cacheBlockSize() constgem5::DmaDeviceinline
clearInterrupt(bool is_primary) overridegem5::X86IdeControllervirtual
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
configgem5::PciDeviceprotected
configDelaygem5::PciDeviceprotected
configSpaceRegsgem5::IdeControllerprivate
ctrlOffsetgem5::IdeControllerprivate
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
dispatchAccess(PacketPtr pkt, bool read)gem5::IdeControllerprivate
dmaCap1gem5::IdeControllerprivate
DmaDevice(const Params &p)gem5::DmaDevice
dmaErrorgem5::IdeControllerprivate
dmaPending() constgem5::DmaDeviceinline
dmaPortgem5::DmaDeviceprotected
dmaRead(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)gem5::DmaDeviceinline
dmaRead(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)gem5::DmaDeviceinline
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0)gem5::DmaDeviceinline
dmaWrite(Addr addr, int size, Event *event, uint8_t *data, Tick delay=0)gem5::DmaDeviceinline
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
EndBitUnion(BMIStatusReg) BitUnion8(BMICommandReg) Bitfield< 3 > rwgem5::IdeControllerprivate
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
frequency() constgem5::Clockedinline
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRanges() const overridegem5::PciDevicevirtual
getBAR(Addr addr, int &num, Addr &offs)gem5::PciDeviceinlineprotected
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::X86IdeControllervirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
hostInterfacegem5::PciDeviceprotected
IdeController(const Params &p)gem5::IdeController
init() overridegem5::DmaDevicevirtual
initState()gem5::SimObjectvirtual
interruptLine() constgem5::PciDeviceinline
intPrimarygem5::X86IdeControllerprivate
intrClear()gem5::PciDeviceinline
intrPost()gem5::PciDeviceinline
intSecondarygem5::X86IdeControllerprivate
intStatusgem5::IdeControllerprivate
ioShiftgem5::IdeControllerprivate
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
msicapgem5::PciDeviceprotected
MSICAP_BASEgem5::PciDeviceprotected
msix_pbagem5::PciDeviceprotected
MSIX_PBA_ENDgem5::PciDeviceprotected
MSIX_PBA_OFFSETgem5::PciDeviceprotected
msix_tablegem5::PciDeviceprotected
MSIX_TABLE_ENDgem5::PciDeviceprotected
MSIX_TABLE_OFFSETgem5::PciDeviceprotected
msixcapgem5::PciDeviceprotected
MSIXCAP_BASEgem5::PciDeviceprotected
MSIXCAP_ID_OFFSETgem5::PciDeviceprotected
MSIXCAP_MPBA_OFFSETgem5::PciDeviceprotected
MSIXCAP_MTAB_OFFSETgem5::PciDeviceprotected
MSIXCAP_MXC_OFFSETgem5::PciDeviceprotected
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
PARAMS(X86IdeController)gem5::X86IdeController
gem5::IdeController::PARAMS(IdeController)gem5::IdeController
Params typedefgem5::DmaDevice
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
PciDevice(const PciDeviceParams &params)gem5::PciDevice
pciToDma(Addr pci_addr) constgem5::PciDeviceinline
pioDelaygem5::PciDeviceprotected
PioDevice(const Params &p)gem5::PioDevice
pioPortgem5::PioDeviceprotected
pmcapgem5::PciDeviceprotected
PMCAP_BASEgem5::PciDeviceprotected
PMCAP_ID_OFFSETgem5::PciDeviceprotected
PMCAP_PC_OFFSETgem5::PciDeviceprotected
PMCAP_PMCS_OFFSETgem5::PciDeviceprotected
postInterrupt(bool is_primary) overridegem5::X86IdeControllervirtual
powerStategem5::ClockedObject
preDumpStats()gem5::statistics::Groupvirtual
primarygem5::IdeControllerprivate
probeManagergem5::SimObjectprivate
pxcapgem5::PciDeviceprotected
PXCAP_BASEgem5::PciDeviceprotected
read(PacketPtr pkt) overridegem5::IdeControllervirtual
readConfig(PacketPtr pkt) overridegem5::IdeControllervirtual
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
secondarygem5::IdeControllerprivate
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::IdeControllervirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
startStopgem5::IdeControllerprivate
startup()gem5::SimObjectvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
sysgem5::PioDeviceprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
unserialize(CheckpointIn &cp) overridegem5::IdeControllervirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
write(PacketPtr pkt) overridegem5::IdeControllervirtual
writeConfig(PacketPtr pkt) overridegem5::IdeControllervirtual
X86IdeController(const Params &p)gem5::X86IdeController
~Clocked()gem5::Clockedinlineprotectedvirtual
~DmaDevice()=defaultgem5::DmaDevicevirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~PioDevice()gem5::PioDevicevirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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