gem5 v24.0.0.0
Loading...
Searching...
No Matches
gem5::fastmodel::CortexA76 Member List

This is the complete list of members for gem5::fastmodel::CortexA76, including all inherited members.

_cacheLineSizegem5::BaseCPUprotected
_cpuIdgem5::BaseCPUprotected
_dataRequestorIdgem5::BaseCPUprotected
_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_instRequestorIdgem5::BaseCPUprotected
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_pidgem5::BaseCPUprotected
_socketIdgem5::BaseCPUprotected
_switchedOutgem5::BaseCPUprotected
_taskIdgem5::BaseCPUprotected
activateContext(ThreadID thread_num)gem5::BaseCPUvirtual
addressMonitorgem5::BaseCPUprivate
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
armMonitor(ThreadID tid, Addr address)gem5::BaseCPU
Base typedefgem5::fastmodel::CortexA76protected
BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs)gem5::Iris::BaseCPU
gem5::BaseCPU::BaseCPU(const Params &params, bool is_checker=false)gem5::BaseCPU
baseStatsgem5::BaseCPU
cacheLineSize() constgem5::BaseCPUinline
checkInterrupts(ThreadID tid) constgem5::BaseCPUinline
clearInterrupt(ThreadID tid, int int_num, int index)gem5::BaseCPUinline
clearInterrupts(ThreadID tid)gem5::BaseCPUinline
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated() overridegem5::Iris::BaseCPUinlineprotectedvirtual
clustergem5::fastmodel::CortexA76protected
commitStatsgem5::BaseCPU
contextToThread(ContextID cid)gem5::BaseCPUinline
CortexA76(const Params &p)gem5::fastmodel::CortexA76inline
CPU(const IrisBaseCPUParams &params, iris::IrisConnectionInterface *iris_if)gem5::Iris::CPU< CortexA76TC >inline
CPU_STATE_ON enum valuegem5::BaseCPUprotected
CPU_STATE_SLEEP enum valuegem5::BaseCPUprotected
CPU_STATE_WAKEUP enum valuegem5::BaseCPUprotected
cpuId() constgem5::BaseCPUinline
cpuListgem5::BaseCPUprivatestatic
CPUState enum namegem5::BaseCPUprotected
curCycle() constgem5::Clockedinline
currentFunctionEndgem5::BaseCPUprivate
currentFunctionStartgem5::BaseCPUprivate
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
dataRequestorId() constgem5::BaseCPUinline
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
deschedulePowerGatingEvent()gem5::BaseCPU
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
enableFunctionTrace()gem5::BaseCPUprivate
enterPwrGating()gem5::BaseCPUprotected
enterPwrGatingEventgem5::BaseCPUprotected
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
evsgem5::Iris::BaseCPUprotected
evs_base_cpugem5::Iris::BaseCPUprotected
executeStatsgem5::BaseCPU
fetchStatsgem5::BaseCPU
find(const char *name)gem5::SimObjectstatic
findContext(ThreadContext *tc)gem5::BaseCPU
flushTLBs()gem5::BaseCPU
frequency() constgem5::Clockedinline
functionEntryTickgem5::BaseCPUprivate
functionTraceStreamgem5::BaseCPUprivate
functionTracingEnabledgem5::BaseCPUprivate
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getContext(int tn)gem5::BaseCPUinlinevirtual
getCpuAddrMonitor(ThreadID tid)gem5::BaseCPUinline
getCurrentInstCount(ThreadID tid)gem5::BaseCPU
getDataPort() overridegem5::Iris::BaseCPUinlinevirtual
getInstPort() overridegem5::Iris::BaseCPUinlinevirtual
getInterruptController(ThreadID tid)gem5::BaseCPUinline
getPid() constgem5::BaseCPUinline
getPort(const std::string &if_name, PortID idx=InvalidPortID) overridegem5::fastmodel::CortexA76virtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
getTracer()gem5::BaseCPUinline
globalStatsgem5::BaseCPUprotectedstatic
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
haltContext(ThreadID thread_num)gem5::BaseCPUvirtual
htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)gem5::BaseCPUinlinevirtual
init() overridegem5::BaseCPUvirtual
initState() overridegem5::fastmodel::CortexA76virtual
instCntgem5::BaseCPUprotected
instCount()gem5::BaseCPUinline
instRequestorId() constgem5::BaseCPUinline
interruptsgem5::BaseCPUprotected
invldPidgem5::BaseCPUstatic
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
modelResetPortgem5::BaseCPUprotected
mwait(ThreadID tid, PacketPtr pkt)gem5::BaseCPU
mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)gem5::BaseCPU
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextCycle() constgem5::Clockedinline
notifyFork()gem5::Drainableinlinevirtual
numgem5::fastmodel::CortexA76protected
numContexts()gem5::BaseCPUinline
numSimulatedCPUs()gem5::BaseCPUinlinestatic
numSimulatedInsts()gem5::BaseCPUinlinestatic
numSimulatedOps()gem5::BaseCPUinlinestatic
numThreadsgem5::BaseCPU
gem5::operator=(const Group &)=deletegem5::statistics::Group
gem5::Clocked::operator=(Clocked &)=deletegem5::Clockedprotected
PARAMS(FastModelCortexA76)gem5::fastmodel::CortexA76
gem5::Iris::CPU< CortexA76TC >::PARAMS(BaseCPU)gem5::BaseCPU
Params typedefgem5::ClockedObject
params() constgem5::SimObjectinline
pathgem5::Serializableprivatestatic
pmuProbePoint(const char *name)gem5::BaseCPUprotected
postInterrupt(ThreadID tid, int int_num, int index)gem5::BaseCPU
powerGatingOnIdlegem5::BaseCPUprotected
powerStategem5::ClockedObject
ppActiveCyclesgem5::BaseCPUprotected
ppAllCyclesgem5::BaseCPUprotected
ppRetiredBranchesgem5::BaseCPUprotected
ppRetiredInstsgem5::BaseCPUprotected
ppRetiredInstsPCgem5::BaseCPUprotected
ppRetiredLoadsgem5::BaseCPUprotected
ppRetiredStoresgem5::BaseCPUprotected
ppSleepinggem5::BaseCPUprotected
preDumpStats()gem5::statistics::Groupvirtual
previousCyclegem5::BaseCPUprotected
previousStategem5::BaseCPUprotected
probeInstCommit(const StaticInstPtr &inst, Addr pc)gem5::BaseCPUvirtual
probeManagergem5::SimObjectprivate
pwrGatingLatencygem5::BaseCPUprotected
registerThreadContexts()gem5::BaseCPU
regProbeListeners()gem5::SimObjectvirtual
regProbePoints() overridegem5::BaseCPUvirtual
regStats() overridegem5::BaseCPUvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
scheduleInstStop(ThreadID tid, Counter insts, std::string cause)gem5::BaseCPU
scheduleInstStopAnyThread(Counter max_insts)gem5::BaseCPU
schedulePowerGatingEvent()gem5::BaseCPU
scheduleSimpointsInstStop(std::vector< Counter > inst_starts)gem5::BaseCPU
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::BaseCPUvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
serializeThread(CheckpointOut &cp, ThreadID tid) const overridegem5::Iris::BaseCPUprotectedvirtual
set_evs_param(const std::string &n, T val)gem5::fastmodel::CortexA76inline
setCluster(CortexA76Cluster *_cluster, int _num)gem5::fastmodel::CortexA76
setCurTick(Tick newVal)gem5::EventManagerinline
setPid(uint32_t pid)gem5::BaseCPUinline
setReset(bool state)gem5::BaseCPUvirtual
setResetAddr(Addr addr, bool secure=false) overridegem5::fastmodel::CortexA76virtual
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
socketId() constgem5::BaseCPUinline
startup() overridegem5::BaseCPUvirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::statistics::Groupprivate
suspendContext(ThreadID thread_num)gem5::BaseCPUvirtual
switchedOut() constgem5::BaseCPUinline
switchOut()gem5::BaseCPUvirtual
syscallRetryLatencygem5::BaseCPU
systemgem5::BaseCPU
takeOverFrom(BaseCPU *cpu)gem5::BaseCPUvirtual
taskId() constgem5::BaseCPUinline
taskId(uint32_t id)gem5::BaseCPUinline
ThreadContextgem5::Iris::BaseCPUprotected
threadContextsgem5::BaseCPUprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
totalInsts() const overridegem5::Iris::BaseCPUvirtual
totalOps() const overridegem5::Iris::BaseCPUinlinevirtual
traceFunctions(Addr pc)gem5::BaseCPUinline
traceFunctionsInternal(Addr pc)gem5::BaseCPUprivate
tracergem5::BaseCPUprotected
unserialize(CheckpointIn &cp) overridegem5::BaseCPUvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
unserializeThread(CheckpointIn &cp, ThreadID tid)gem5::BaseCPUinlinevirtual
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
updateCycleCounters(CPUState state)gem5::BaseCPUinlineprotected
verifyMemoryMode() constgem5::BaseCPUinlinevirtual
voltage() constgem5::Clockedinline
wakeup(ThreadID tid) overridegem5::Iris::BaseCPUinlinevirtual
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
workItemBegin()gem5::BaseCPUinline
workItemEnd()gem5::BaseCPUinline
~BaseCPU()gem5::Iris::BaseCPUvirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual
Generated on Tue Jun 18 2024 16:24:19 for gem5 by doxygen 1.11.0