| _drainManager | gem5::Drainable | private |
| _drainState | gem5::Drainable | mutableprivate |
| _name | gem5::Named | private |
| _objNameResolver | gem5::SimObject | privatestatic |
| _params | gem5::SimObject | protected |
| _system | gem5::memory::AbstractMemory | protected |
| AbstractMemory(const AbstractMemory &) | gem5::memory::AbstractMemory | private |
| AbstractMemory(const Params &p) | gem5::memory::AbstractMemory | |
| access(PacketPtr pkt) | gem5::memory::AbstractMemory | |
| accessLatency() const override | gem5::memory::DRAMInterface | inlinevirtual |
| activateBank(Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row) | gem5::memory::DRAMInterface | private |
| activationLimit | gem5::memory::DRAMInterface | private |
| activeRank | gem5::memory::DRAMInterface | private |
| addLockedAddr(LockedAddr addr) | gem5::memory::AbstractMemory | inline |
| addRankToRankDelay(Tick cmd_at) override | gem5::memory::DRAMInterface | virtual |
| addrMapping | gem5::memory::MemInterface | protected |
| addStat(statistics::Info *info) | gem5::statistics::Group | |
| addStatGroup(const char *name, Group *block) | gem5::statistics::Group | |
| allRanksDrained() const override | gem5::memory::DRAMInterface | virtual |
| backdoor | gem5::memory::AbstractMemory | protected |
| bankGroupArch | gem5::memory::DRAMInterface | private |
| bankGroupsPerRank | gem5::memory::DRAMInterface | private |
| banksPerRank | gem5::memory::MemInterface | protected |
| burstDelay() const | gem5::memory::DRAMInterface | inlineprivate |
| burstInterleave | gem5::memory::DRAMInterface | private |
| burstReady(MemPacket *pkt) const override | gem5::memory::DRAMInterface | inlinevirtual |
| burstSize | gem5::memory::MemInterface | protected |
| burstsPerRowBuffer | gem5::memory::MemInterface | protected |
| burstsPerStripe | gem5::memory::MemInterface | protected |
| bytesPerBurst() const | gem5::memory::MemInterface | inline |
| checkLockedAddrList(PacketPtr pkt) | gem5::memory::AbstractMemory | protected |
| checkRefreshState(uint8_t rank) override | gem5::memory::DRAMInterface | virtual |
| chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const override | gem5::memory::DRAMInterface | virtual |
| chooseRead(MemPacketQueue &queue) override | gem5::memory::DRAMInterface | inlinevirtual |
| clkResyncDelay | gem5::memory::DRAMInterface | private |
| clockDomain | gem5::Clocked | private |
| Clocked(ClockDomain &clk_domain) | gem5::Clocked | inlineprotected |
| Clocked(Clocked &)=delete | gem5::Clocked | protected |
| clockEdge(Cycles cycles=Cycles(0)) const | gem5::Clocked | inline |
| ClockedObject(const ClockedObjectParams &p) | gem5::ClockedObject | |
| clockPeriod() const | gem5::Clocked | inline |
| clockPeriodUpdated() | gem5::Clocked | inlineprotectedvirtual |
| commandOffset() const override | gem5::memory::DRAMInterface | inlinevirtual |
| confTableReported | gem5::memory::AbstractMemory | protected |
| ctrl | gem5::memory::MemInterface | protected |
| curCycle() const | gem5::Clocked | inline |
| currentSection() | gem5::Serializable | static |
| cycle | gem5::Clocked | mutableprivate |
| cyclesToTicks(Cycles c) const | gem5::Clocked | inline |
| dataClockSync | gem5::memory::DRAMInterface | private |
| decodePacket(const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, uint8_t pseudo_channel=0) override | gem5::memory::DRAMInterface | virtual |
| deschedule(Event &event) | gem5::EventManager | inline |
| deschedule(Event *event) | gem5::EventManager | inline |
| deviceRowBufferSize | gem5::memory::MemInterface | protected |
| deviceSize | gem5::memory::MemInterface | protected |
| devicesPerRank | gem5::memory::MemInterface | protected |
| dmDrain() | gem5::Drainable | private |
| dmDrainResume() | gem5::Drainable | private |
| doBurstAccess(MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue) override | gem5::memory::DRAMInterface | virtual |
| drain() override | gem5::SimObject | inlinevirtual |
| Drainable() | gem5::Drainable | protected |
| drainRanks() override | gem5::memory::DRAMInterface | virtual |
| drainResume() | gem5::Drainable | inlineprotectedvirtual |
| drainState() const | gem5::Drainable | inline |
| DRAMInterface(const DRAMInterfaceParams &_p) | gem5::memory::DRAMInterface | |
| enableDRAMPowerdown | gem5::memory::DRAMInterface | private |
| EventManager(EventManager &em) | gem5::EventManager | inline |
| EventManager(EventManager *em) | gem5::EventManager | inline |
| EventManager(EventQueue *eq) | gem5::EventManager | inline |
| eventq | gem5::EventManager | protected |
| eventQueue() const | gem5::EventManager | inline |
| find(const char *name) | gem5::SimObject | static |
| frequency() const | gem5::Clocked | inline |
| functionalAccess(PacketPtr pkt) | gem5::memory::AbstractMemory | |
| generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream) | gem5::Serializable | static |
| getAddrRange() const | gem5::memory::AbstractMemory | |
| getBackdoor(MemBackdoorPtr &bd_ptr) | gem5::memory::AbstractMemory | inline |
| getCtrlAddr(Addr addr) | gem5::memory::MemInterface | inline |
| getLockedAddrList() const | gem5::memory::AbstractMemory | inline |
| getPort(const std::string &if_name, PortID idx=InvalidPortID) | gem5::SimObject | virtual |
| getProbeManager() | gem5::SimObject | |
| getSimObjectResolver() | gem5::SimObject | static |
| getStatGroups() const | gem5::statistics::Group | |
| getStats() const | gem5::statistics::Group | |
| Group()=delete | gem5::statistics::Group | |
| Group(const Group &)=delete | gem5::statistics::Group | |
| Group(Group *parent, const char *name=nullptr) | gem5::statistics::Group | |
| inAddrMap | gem5::memory::AbstractMemory | protected |
| init() override | gem5::memory::DRAMInterface | virtual |
| initState() override | gem5::memory::AbstractMemory | virtual |
| isBusy(bool read_queue_empty, bool all_writes_nvm) override | gem5::memory::DRAMInterface | virtual |
| isConfReported() const | gem5::memory::AbstractMemory | inline |
| isInAddrMap() const | gem5::memory::AbstractMemory | inline |
| isKvmMap() const | gem5::memory::AbstractMemory | inline |
| isNull() const | gem5::memory::AbstractMemory | inline |
| kvmMap | gem5::memory::AbstractMemory | protected |
| lastStatsResetTick | gem5::memory::DRAMInterface | private |
| loadState(CheckpointIn &cp) | gem5::SimObject | virtual |
| lockedAddrList | gem5::memory::AbstractMemory | protected |
| maxAccessesPerRow | gem5::memory::DRAMInterface | private |
| maxCommandsPerWindow | gem5::memory::MemInterface | protected |
| MemInterface(const Params &_p) | gem5::memory::MemInterface | |
| memInvalidate() | gem5::SimObject | inlinevirtual |
| memWriteback() | gem5::SimObject | inlinevirtual |
| mergedParent | gem5::statistics::Group | private |
| mergedStatGroups | gem5::statistics::Group | private |
| mergeStatGroup(Group *block) | gem5::statistics::Group | |
| minBankPrep(const MemPacketQueue &queue, Tick min_col_at) const | gem5::memory::DRAMInterface | private |
| minReadToWriteDataGap() const | gem5::memory::MemInterface | inline |
| minWriteToReadDataGap() const | gem5::memory::MemInterface | inline |
| name() const | gem5::Named | inlinevirtual |
| Named(const std::string &name_) | gem5::Named | inline |
| nextBurstAt | gem5::memory::MemInterface | |
| nextCycle() const | gem5::Clocked | inline |
| nextReqTime | gem5::memory::MemInterface | |
| notifyFork() | gem5::Drainable | inlinevirtual |
| numWritesQueued | gem5::memory::MemInterface | |
| operator=(const AbstractMemory &) | gem5::memory::AbstractMemory | private |
| gem5::ClockedObject::operator=(const Group &)=delete | gem5::statistics::Group | |
| gem5::ClockedObject::operator=(Clocked &)=delete | gem5::Clocked | protected |
| pageMgmt | gem5::memory::DRAMInterface | private |
| Params typedef | gem5::memory::MemInterface | |
| PARAMS(AbstractMemory) | gem5::memory::AbstractMemory | |
| params() const | gem5::SimObject | inline |
| path | gem5::Serializable | privatestatic |
| pmemAddr | gem5::memory::AbstractMemory | protected |
| powerState | gem5::ClockedObject | |
| PowerState enum name | gem5::memory::DRAMInterface | private |
| prechargeBank(Rank &rank_ref, Bank &bank_ref, Tick pre_tick, bool auto_or_preall=false, bool trace=true) | gem5::memory::DRAMInterface | private |
| preDumpStats() | gem5::statistics::Group | virtual |
| probeManager | gem5::SimObject | private |
| pseudoChannel | gem5::memory::MemInterface | |
| PWR_ACT enum value | gem5::memory::DRAMInterface | private |
| PWR_ACT_PDN enum value | gem5::memory::DRAMInterface | private |
| PWR_IDLE enum value | gem5::memory::DRAMInterface | private |
| PWR_PRE_PDN enum value | gem5::memory::DRAMInterface | private |
| PWR_REF enum value | gem5::memory::DRAMInterface | private |
| PWR_SREF enum value | gem5::memory::DRAMInterface | private |
| range | gem5::memory::AbstractMemory | protected |
| rankDelay() const | gem5::memory::MemInterface | inline |
| ranks | gem5::memory::DRAMInterface | private |
| ranksPerChannel | gem5::memory::MemInterface | protected |
| rankToRankDelay() const | gem5::memory::MemInterface | inlineprotected |
| rdToWrDlySameBG | gem5::memory::DRAMInterface | private |
| readBufferSize | gem5::memory::MemInterface | |
| readsWaitingToIssue() const override | gem5::memory::DRAMInterface | inlinevirtual |
| readToWriteDelay() const | gem5::memory::MemInterface | inlineprotected |
| REF_DRAIN enum value | gem5::memory::DRAMInterface | private |
| REF_IDLE enum value | gem5::memory::DRAMInterface | private |
| REF_PD_EXIT enum value | gem5::memory::DRAMInterface | private |
| REF_PRE enum value | gem5::memory::DRAMInterface | private |
| REF_RUN enum value | gem5::memory::DRAMInterface | private |
| REF_SREF_EXIT enum value | gem5::memory::DRAMInterface | private |
| REF_START enum value | gem5::memory::DRAMInterface | private |
| RefreshState enum name | gem5::memory::DRAMInterface | private |
| regProbeListeners() | gem5::SimObject | virtual |
| regProbePoints() | gem5::SimObject | virtual |
| regStats() | gem5::statistics::Group | virtual |
| reschedule(Event &event, Tick when, bool always=false) | gem5::EventManager | inline |
| reschedule(Event *event, Tick when, bool always=false) | gem5::EventManager | inline |
| resetClock() const | gem5::Clocked | inlineprotected |
| resetStats() | gem5::statistics::Group | virtual |
| resolveStat(std::string name) const | gem5::statistics::Group | |
| respondEvent(uint8_t rank) override | gem5::memory::DRAMInterface | virtual |
| rowBufferSize | gem5::memory::MemInterface | protected |
| rowsPerBank | gem5::memory::MemInterface | protected |
| schedule(Event &event, Tick when) | gem5::EventManager | inline |
| schedule(Event *event, Tick when) | gem5::EventManager | inline |
| Serializable() | gem5::Serializable | |
| serialize(CheckpointOut &cp) const override | gem5::ClockedObject | virtual |
| serializeAll(const std::string &cpt_dir) | gem5::SimObject | static |
| serializeSection(CheckpointOut &cp, const char *name) const | gem5::Serializable | |
| serializeSection(CheckpointOut &cp, const std::string &name) const | gem5::Serializable | inline |
| setBackingStore(uint8_t *pmem_addr) | gem5::memory::AbstractMemory | |
| setCtrl(MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0) | gem5::memory::MemInterface | |
| setCurTick(Tick newVal) | gem5::EventManager | inline |
| setSimObjectResolver(SimObjectResolver *resolver) | gem5::SimObject | static |
| setupRank(const uint8_t rank, const bool is_read) override | gem5::memory::DRAMInterface | virtual |
| signalDrainDone() const | gem5::Drainable | inlineprotected |
| SimObject(const Params &p) | gem5::SimObject | |
| SimObjectList typedef | gem5::SimObject | private |
| simObjectList | gem5::SimObject | privatestatic |
| size() const | gem5::memory::AbstractMemory | inline |
| sortTime(const Command &cmd, const Command &cmd_next) | gem5::memory::DRAMInterface | inlineprivatestatic |
| start() const | gem5::memory::AbstractMemory | inline |
| startup() override | gem5::memory::DRAMInterface | virtual |
| statGroups | gem5::statistics::Group | private |
| stats | gem5::memory::DRAMInterface | private |
| suspend() override | gem5::memory::DRAMInterface | virtual |
| system() const | gem5::memory::AbstractMemory | inline |
| system(System *sys) | gem5::memory::AbstractMemory | inline |
| tAAD | gem5::memory::DRAMInterface | private |
| tBURST | gem5::memory::MemInterface | protected |
| tBURST_MAX | gem5::memory::DRAMInterface | private |
| tBURST_MIN | gem5::memory::DRAMInterface | private |
| tCCD_L | gem5::memory::DRAMInterface | private |
| tCCD_L_WR | gem5::memory::DRAMInterface | private |
| tCK | gem5::memory::MemInterface | protected |
| tCS | gem5::memory::MemInterface | protected |
| tick | gem5::Clocked | mutableprivate |
| ticksToCycles(Tick t) const | gem5::Clocked | inline |
| timeStampOffset | gem5::memory::DRAMInterface | private |
| toHostAddr(Addr addr) const | gem5::memory::AbstractMemory | inline |
| tPPD | gem5::memory::DRAMInterface | private |
| trackLoadLocked(PacketPtr pkt) | gem5::memory::AbstractMemory | protected |
| tRAS | gem5::memory::DRAMInterface | private |
| tRCD_RD | gem5::memory::DRAMInterface | private |
| tRCD_WR | gem5::memory::DRAMInterface | private |
| tREFI | gem5::memory::DRAMInterface | private |
| tRFC | gem5::memory::DRAMInterface | private |
| tRL | gem5::memory::DRAMInterface | private |
| tRP | gem5::memory::DRAMInterface | private |
| tRRD | gem5::memory::DRAMInterface | private |
| tRRD_L | gem5::memory::DRAMInterface | private |
| tRTP | gem5::memory::DRAMInterface | private |
| tRTW | gem5::memory::MemInterface | protected |
| tWL | gem5::memory::DRAMInterface | private |
| twoCycleActivate | gem5::memory::DRAMInterface | private |
| tWR | gem5::memory::DRAMInterface | private |
| tWTR | gem5::memory::MemInterface | protected |
| tXAW | gem5::memory::DRAMInterface | private |
| tXP | gem5::memory::DRAMInterface | private |
| tXS | gem5::memory::DRAMInterface | private |
| unserialize(CheckpointIn &cp) override | gem5::ClockedObject | virtual |
| unserializeSection(CheckpointIn &cp, const char *name) | gem5::Serializable | |
| unserializeSection(CheckpointIn &cp, const std::string &name) | gem5::Serializable | inline |
| update() const | gem5::Clocked | inlineprivate |
| updateClockPeriod() | gem5::Clocked | inline |
| voltage() const | gem5::Clocked | inline |
| wakeupEventQueue(Tick when=(Tick) -1) | gem5::EventManager | inline |
| writeBufferSize | gem5::memory::MemInterface | |
| writeOK(PacketPtr pkt) | gem5::memory::AbstractMemory | inlineprotected |
| writeRespQueueFull() const override | gem5::memory::DRAMInterface | inlinevirtual |
| writeToReadDelay() const override | gem5::memory::DRAMInterface | inlineprivatevirtual |
| wrToRdDlySameBG | gem5::memory::DRAMInterface | private |
| ~AbstractMemory() | gem5::memory::AbstractMemory | inlinevirtual |
| ~Clocked() | gem5::Clocked | inlineprotectedvirtual |
| ~Drainable() | gem5::Drainable | protectedvirtual |
| ~Group() | gem5::statistics::Group | virtual |
| ~Named()=default | gem5::Named | virtual |
| ~Serializable() | gem5::Serializable | virtual |
| ~SimObject() | gem5::SimObject | virtual |