gem5  v22.0.0.2
gem5::memory::DRAMInterface Member List

This is the complete list of members for gem5::memory::DRAMInterface, including all inherited members.

_drainManagergem5::Drainableprivate
_drainStategem5::Drainablemutableprivate
_namegem5::Namedprivate
_objNameResolvergem5::SimObjectprivatestatic
_paramsgem5::SimObjectprotected
_systemgem5::memory::AbstractMemoryprotected
AbstractMemory(const AbstractMemory &)gem5::memory::AbstractMemoryprivate
AbstractMemory(const Params &p)gem5::memory::AbstractMemory
access(PacketPtr pkt)gem5::memory::AbstractMemory
accessLatency() const overridegem5::memory::DRAMInterfaceinlinevirtual
activateBank(Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row)gem5::memory::DRAMInterfaceprivate
activationLimitgem5::memory::DRAMInterfaceprivate
activeRankgem5::memory::DRAMInterfaceprivate
addLockedAddr(LockedAddr addr)gem5::memory::AbstractMemoryinline
addRankToRankDelay(Tick cmd_at) overridegem5::memory::DRAMInterfacevirtual
addrMappinggem5::memory::MemInterfaceprotected
addStat(statistics::Info *info)gem5::statistics::Group
addStatGroup(const char *name, Group *block)gem5::statistics::Group
allRanksDrained() const overridegem5::memory::DRAMInterfacevirtual
backdoorgem5::memory::AbstractMemoryprotected
bankGroupArchgem5::memory::DRAMInterfaceprivate
bankGroupsPerRankgem5::memory::DRAMInterfaceprivate
banksPerRankgem5::memory::MemInterfaceprotected
burstDelay() constgem5::memory::DRAMInterfaceinlineprivate
burstInterleavegem5::memory::DRAMInterfaceprivate
burstReady(MemPacket *pkt) const overridegem5::memory::DRAMInterfaceinlinevirtual
burstSizegem5::memory::MemInterfaceprotected
burstsPerRowBuffergem5::memory::MemInterfaceprotected
burstsPerStripegem5::memory::MemInterfaceprotected
bytesPerBurst() constgem5::memory::MemInterfaceinline
checkLockedAddrList(PacketPtr pkt)gem5::memory::AbstractMemoryprotected
checkRefreshState(uint8_t rank) overridegem5::memory::DRAMInterfacevirtual
chooseNextFRFCFS(MemPacketQueue &queue, Tick min_col_at) const overridegem5::memory::DRAMInterfacevirtual
chooseRead(MemPacketQueue &queue) overridegem5::memory::DRAMInterfaceinlinevirtual
clkResyncDelaygem5::memory::DRAMInterfaceprivate
clockDomaingem5::Clockedprivate
Clocked(ClockDomain &clk_domain)gem5::Clockedinlineprotected
Clocked(Clocked &)=deletegem5::Clockedprotected
clockEdge(Cycles cycles=Cycles(0)) constgem5::Clockedinline
ClockedObject(const ClockedObjectParams &p)gem5::ClockedObject
clockPeriod() constgem5::Clockedinline
clockPeriodUpdated()gem5::Clockedinlineprotectedvirtual
commandOffset() const overridegem5::memory::DRAMInterfaceinlinevirtual
confTableReportedgem5::memory::AbstractMemoryprotected
ctrlgem5::memory::MemInterfaceprotected
curCycle() constgem5::Clockedinline
currentSection()gem5::Serializablestatic
cyclegem5::Clockedmutableprivate
cyclesToTicks(Cycles c) constgem5::Clockedinline
dataClockSyncgem5::memory::DRAMInterfaceprivate
decodePacket(const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, uint8_t pseudo_channel=0) overridegem5::memory::DRAMInterfacevirtual
deschedule(Event &event)gem5::EventManagerinline
deschedule(Event *event)gem5::EventManagerinline
deviceRowBufferSizegem5::memory::MemInterfaceprotected
deviceSizegem5::memory::MemInterfaceprotected
devicesPerRankgem5::memory::MemInterfaceprotected
dmDrain()gem5::Drainableprivate
dmDrainResume()gem5::Drainableprivate
doBurstAccess(MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue) overridegem5::memory::DRAMInterfacevirtual
drain() overridegem5::SimObjectinlinevirtual
Drainable()gem5::Drainableprotected
drainRanks() overridegem5::memory::DRAMInterfacevirtual
drainResume()gem5::Drainableinlineprotectedvirtual
drainState() constgem5::Drainableinline
DRAMInterface(const DRAMInterfaceParams &_p)gem5::memory::DRAMInterface
enableDRAMPowerdowngem5::memory::DRAMInterfaceprivate
EventManager(EventManager &em)gem5::EventManagerinline
EventManager(EventManager *em)gem5::EventManagerinline
EventManager(EventQueue *eq)gem5::EventManagerinline
eventqgem5::EventManagerprotected
eventQueue() constgem5::EventManagerinline
find(const char *name)gem5::SimObjectstatic
frequency() constgem5::Clockedinline
functionalAccess(PacketPtr pkt)gem5::memory::AbstractMemory
generateCheckpointOut(const std::string &cpt_dir, std::ofstream &outstream)gem5::Serializablestatic
getAddrRange() constgem5::memory::AbstractMemory
getBackdoor(MemBackdoorPtr &bd_ptr)gem5::memory::AbstractMemoryinline
getCtrlAddr(Addr addr)gem5::memory::MemInterfaceinline
getLockedAddrList() constgem5::memory::AbstractMemoryinline
getPort(const std::string &if_name, PortID idx=InvalidPortID)gem5::SimObjectvirtual
getProbeManager()gem5::SimObject
getSimObjectResolver()gem5::SimObjectstatic
getStatGroups() constgem5::statistics::Group
getStats() constgem5::statistics::Group
Group()=deletegem5::statistics::Group
Group(const Group &)=deletegem5::statistics::Group
Group(Group *parent, const char *name=nullptr)gem5::statistics::Group
inAddrMapgem5::memory::AbstractMemoryprotected
init() overridegem5::memory::DRAMInterfacevirtual
initState() overridegem5::memory::AbstractMemoryvirtual
isBusy(bool read_queue_empty, bool all_writes_nvm) overridegem5::memory::DRAMInterfacevirtual
isConfReported() constgem5::memory::AbstractMemoryinline
isInAddrMap() constgem5::memory::AbstractMemoryinline
isKvmMap() constgem5::memory::AbstractMemoryinline
isNull() constgem5::memory::AbstractMemoryinline
kvmMapgem5::memory::AbstractMemoryprotected
lastStatsResetTickgem5::memory::DRAMInterfaceprivate
loadState(CheckpointIn &cp)gem5::SimObjectvirtual
lockedAddrListgem5::memory::AbstractMemoryprotected
maxAccessesPerRowgem5::memory::DRAMInterfaceprivate
maxCommandsPerWindowgem5::memory::MemInterfaceprotected
MemInterface(const Params &_p)gem5::memory::MemInterface
memInvalidate()gem5::SimObjectinlinevirtual
memWriteback()gem5::SimObjectinlinevirtual
mergedParentgem5::statistics::Groupprivate
mergedStatGroupsgem5::statistics::Groupprivate
mergeStatGroup(Group *block)gem5::statistics::Group
minBankPrep(const MemPacketQueue &queue, Tick min_col_at) constgem5::memory::DRAMInterfaceprivate
minReadToWriteDataGap() constgem5::memory::MemInterfaceinline
minWriteToReadDataGap() constgem5::memory::MemInterfaceinline
name() constgem5::Namedinlinevirtual
Named(const std::string &name_)gem5::Namedinline
nextBurstAtgem5::memory::MemInterface
nextCycle() constgem5::Clockedinline
nextReqTimegem5::memory::MemInterface
notifyFork()gem5::Drainableinlinevirtual
numWritesQueuedgem5::memory::MemInterface
operator=(const AbstractMemory &)gem5::memory::AbstractMemoryprivate
gem5::ClockedObject::operator=(const Group &)=deletegem5::statistics::Group
gem5::ClockedObject::operator=(Clocked &)=deletegem5::Clockedprotected
pageMgmtgem5::memory::DRAMInterfaceprivate
params() constgem5::SimObjectinline
Params typedefgem5::memory::MemInterface
PARAMS(AbstractMemory)gem5::memory::AbstractMemory
pathgem5::Serializableprivatestatic
pmemAddrgem5::memory::AbstractMemoryprotected
powerStategem5::ClockedObject
PowerState enum namegem5::memory::DRAMInterfaceprivate
prechargeBank(Rank &rank_ref, Bank &bank_ref, Tick pre_tick, bool auto_or_preall=false, bool trace=true)gem5::memory::DRAMInterfaceprivate
preDumpStats()gem5::statistics::Groupvirtual
probeManagergem5::SimObjectprivate
pseudoChannelgem5::memory::MemInterface
PWR_ACT enum valuegem5::memory::DRAMInterfaceprivate
PWR_ACT_PDN enum valuegem5::memory::DRAMInterfaceprivate
PWR_IDLE enum valuegem5::memory::DRAMInterfaceprivate
PWR_PRE_PDN enum valuegem5::memory::DRAMInterfaceprivate
PWR_REF enum valuegem5::memory::DRAMInterfaceprivate
PWR_SREF enum valuegem5::memory::DRAMInterfaceprivate
rangegem5::memory::AbstractMemoryprotected
rankDelay() constgem5::memory::MemInterfaceinline
ranksgem5::memory::DRAMInterfaceprivate
ranksPerChannelgem5::memory::MemInterfaceprotected
rankToRankDelay() constgem5::memory::MemInterfaceinlineprotected
rdToWrDlySameBGgem5::memory::DRAMInterfaceprivate
readBufferSizegem5::memory::MemInterface
readsWaitingToIssue() const overridegem5::memory::DRAMInterfaceinlinevirtual
readToWriteDelay() constgem5::memory::MemInterfaceinlineprotected
REF_DRAIN enum valuegem5::memory::DRAMInterfaceprivate
REF_IDLE enum valuegem5::memory::DRAMInterfaceprivate
REF_PD_EXIT enum valuegem5::memory::DRAMInterfaceprivate
REF_PRE enum valuegem5::memory::DRAMInterfaceprivate
REF_RUN enum valuegem5::memory::DRAMInterfaceprivate
REF_SREF_EXIT enum valuegem5::memory::DRAMInterfaceprivate
REF_START enum valuegem5::memory::DRAMInterfaceprivate
RefreshState enum namegem5::memory::DRAMInterfaceprivate
regProbeListeners()gem5::SimObjectvirtual
regProbePoints()gem5::SimObjectvirtual
regStats()gem5::statistics::Groupvirtual
reschedule(Event &event, Tick when, bool always=false)gem5::EventManagerinline
reschedule(Event *event, Tick when, bool always=false)gem5::EventManagerinline
resetClock() constgem5::Clockedinlineprotected
resetStats()gem5::statistics::Groupvirtual
resolveStat(std::string name) constgem5::statistics::Group
respondEvent(uint8_t rank) overridegem5::memory::DRAMInterfacevirtual
rowBufferSizegem5::memory::MemInterfaceprotected
rowsPerBankgem5::memory::MemInterfaceprotected
schedule(Event &event, Tick when)gem5::EventManagerinline
schedule(Event *event, Tick when)gem5::EventManagerinline
Serializable()gem5::Serializable
serialize(CheckpointOut &cp) const overridegem5::ClockedObjectvirtual
serializeAll(const std::string &cpt_dir)gem5::SimObjectstatic
serializeSection(CheckpointOut &cp, const char *name) constgem5::Serializable
serializeSection(CheckpointOut &cp, const std::string &name) constgem5::Serializableinline
setBackingStore(uint8_t *pmem_addr)gem5::memory::AbstractMemory
setCtrl(MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0)gem5::memory::MemInterface
setCurTick(Tick newVal)gem5::EventManagerinline
setSimObjectResolver(SimObjectResolver *resolver)gem5::SimObjectstatic
setupRank(const uint8_t rank, const bool is_read) overridegem5::memory::DRAMInterfacevirtual
signalDrainDone() constgem5::Drainableinlineprotected
SimObject(const Params &p)gem5::SimObject
SimObjectList typedefgem5::SimObjectprivate
simObjectListgem5::SimObjectprivatestatic
size() constgem5::memory::AbstractMemoryinline
sortTime(const Command &cmd, const Command &cmd_next)gem5::memory::DRAMInterfaceinlineprivatestatic
start() constgem5::memory::AbstractMemoryinline
startup() overridegem5::memory::DRAMInterfacevirtual
statGroupsgem5::statistics::Groupprivate
statsgem5::memory::DRAMInterfaceprivate
suspend() overridegem5::memory::DRAMInterfacevirtual
system() constgem5::memory::AbstractMemoryinline
system(System *sys)gem5::memory::AbstractMemoryinline
tAADgem5::memory::DRAMInterfaceprivate
tBURSTgem5::memory::MemInterfaceprotected
tBURST_MAXgem5::memory::DRAMInterfaceprivate
tBURST_MINgem5::memory::DRAMInterfaceprivate
tCCD_Lgem5::memory::DRAMInterfaceprivate
tCCD_L_WRgem5::memory::DRAMInterfaceprivate
tCKgem5::memory::MemInterfaceprotected
tCSgem5::memory::MemInterfaceprotected
tickgem5::Clockedmutableprivate
ticksToCycles(Tick t) constgem5::Clockedinline
timeStampOffsetgem5::memory::DRAMInterfaceprivate
toHostAddr(Addr addr) constgem5::memory::AbstractMemoryinline
tPPDgem5::memory::DRAMInterfaceprivate
trackLoadLocked(PacketPtr pkt)gem5::memory::AbstractMemoryprotected
tRASgem5::memory::DRAMInterfaceprivate
tRCD_RDgem5::memory::DRAMInterfaceprivate
tRCD_WRgem5::memory::DRAMInterfaceprivate
tREFIgem5::memory::DRAMInterfaceprivate
tRFCgem5::memory::DRAMInterfaceprivate
tRLgem5::memory::DRAMInterfaceprivate
tRPgem5::memory::DRAMInterfaceprivate
tRRDgem5::memory::DRAMInterfaceprivate
tRRD_Lgem5::memory::DRAMInterfaceprivate
tRTPgem5::memory::DRAMInterfaceprivate
tRTWgem5::memory::MemInterfaceprotected
tWLgem5::memory::DRAMInterfaceprivate
twoCycleActivategem5::memory::DRAMInterfaceprivate
tWRgem5::memory::DRAMInterfaceprivate
tWTRgem5::memory::MemInterfaceprotected
tXAWgem5::memory::DRAMInterfaceprivate
tXPgem5::memory::DRAMInterfaceprivate
tXSgem5::memory::DRAMInterfaceprivate
unserialize(CheckpointIn &cp) overridegem5::ClockedObjectvirtual
unserializeSection(CheckpointIn &cp, const char *name)gem5::Serializable
unserializeSection(CheckpointIn &cp, const std::string &name)gem5::Serializableinline
update() constgem5::Clockedinlineprivate
updateClockPeriod()gem5::Clockedinline
voltage() constgem5::Clockedinline
wakeupEventQueue(Tick when=(Tick) -1)gem5::EventManagerinline
writeBufferSizegem5::memory::MemInterface
writeOK(PacketPtr pkt)gem5::memory::AbstractMemoryinlineprotected
writeRespQueueFull() const overridegem5::memory::DRAMInterfaceinlinevirtual
writeToReadDelay() const overridegem5::memory::DRAMInterfaceinlineprivatevirtual
wrToRdDlySameBGgem5::memory::DRAMInterfaceprivate
~AbstractMemory()gem5::memory::AbstractMemoryinlinevirtual
~Clocked()gem5::Clockedinlineprotectedvirtual
~Drainable()gem5::Drainableprotectedvirtual
~Group()gem5::statistics::Groupvirtual
~Named()=defaultgem5::Namedvirtual
~Serializable()gem5::Serializablevirtual
~SimObject()gem5::SimObjectvirtual

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