Interface to DRAM devices with media specific parameters, statistics, and functions. More...

#include <dram_interface.hh>

Inheritance diagram for gem5::memory::DRAMInterface:

Classes
struct	Command
	Simple structure to hold the values needed to keep track of commands for DRAMPower. More...

struct	DRAMStats

class	Rank
	Rank class includes a vector of banks. More...

struct	RankStats

Public Member Functions
void	init () override
	Initialize the DRAM interface and verify parameters.

void	startup () override
	Iterate through dram ranks and instantiate per rank startup routine.

void	setupRank (const uint8_t rank, const bool is_read) override
	Setup the rank based on packet received.

MemPacket *	decodePacket (const PacketPtr pkt, Addr pkt_addr, unsigned int size, bool is_read, uint8_t pseudo_channel=0) override
	Address decoder to figure out physical mapping onto ranks, banks, and rows.

void	drainRanks () override
	Iterate through dram ranks to exit self-refresh in order to drain.

bool	allRanksDrained () const override
	Return true once refresh is complete for all ranks and there are no additional commands enqueued.

void	suspend () override
	Iterate through DRAM ranks and suspend them.

Tick	commandOffset () const override

Tick	accessLatency () const override

std::pair< MemPacketQueue::iterator, Tick >	chooseNextFRFCFS (MemPacketQueue &queue, Tick min_col_at) const override
	For FR-FCFS policy, find first DRAM command that can issue.

std::pair< Tick, Tick >	doBurstAccess (MemPacket *mem_pkt, Tick next_burst_at, const std::vector< MemPacketQueue > &queue) override
	Actually do the burst - figure out the latency it will take to service the req based on bank state, channel state etc and then update those states to account for this request.

bool	burstReady (MemPacket *pkt) const override
	Check if a burst operation can be issued to the DRAM.

bool	isBusy (bool read_queue_empty, bool all_writes_nvm) override
	This function checks if ranks are actively refreshing and therefore busy.

void	addRankToRankDelay (Tick cmd_at) override
	Add rank to rank delay to bus timing to all DRAM banks in alli ranks when access to an alternate interface is issued.

void	respondEvent (uint8_t rank) override
	Complete response process for DRAM when read burst is complete This will update the counters and check if a power down state can be entered.

void	checkRefreshState (uint8_t rank) override
	Check the refresh state to determine if refresh needs to be kicked back into action after a read response.

bool	readsWaitingToIssue () const override
	The next three functions are NVM-specific and will be ignored by DRAM.

void	chooseRead (MemPacketQueue &queue) override
	This function is NVM specific.

bool	writeRespQueueFull () const override
	This function is NVM specific.

	DRAMInterface (const DRAMInterfaceParams &_p)

Public Member Functions inherited from gem5::memory::MemInterface
void	setCtrl (MemCtrl *_ctrl, unsigned int command_window, uint8_t pseudo_channel=0)
	Set a pointer to the controller and initialize interface based on controller parameters.

Addr	getCtrlAddr (Addr addr)
	Get an address in a dense range which starts from 0.

uint32_t	bytesPerBurst () const

Tick	rankDelay () const
	Determine the required delay for an access to a different rank.

Tick	minReadToWriteDataGap () const

Tick	minWriteToReadDataGap () const

	MemInterface (const Params &_p)

Public Member Functions inherited from gem5::memory::AbstractMemory
	PARAMS (AbstractMemory)

	AbstractMemory (const Params &p)

virtual	~AbstractMemory ()

void	initState () override
	initState() is called on each SimObject when not restoring from a checkpoint.

bool	isNull () const
	See if this is a null memory that should never store data and always return zero.

void	setBackingStore (uint8_t *pmem_addr)
	Set the host memory backing store to be used by this memory controller.

void	getBackdoor (MemBackdoorPtr &bd_ptr)

const std::list< LockedAddr > &	getLockedAddrList () const
	Get the list of locked addresses to allow checkpointing.

void	addLockedAddr (LockedAddr addr)
	Add a locked address to allow for checkpointing.

System *	system () const
	read the system pointer Implemented for completeness with the setter

void	system (System *sys)
	Set the system pointer on this memory This can't be done via a python parameter because the system needs pointers to all the memories and the reverse would create a cycle in the object graph.

AddrRange	getAddrRange () const
	Get the address range.

uint8_t *	toHostAddr (Addr addr) const
	Transform a gem5 address space address into its physical counterpart in the host address space.

uint64_t	size () const
	Get the memory size.

Addr	start () const
	Get the start address.

bool	isConfReported () const
	Should this memory be passed to the kernel and part of the OS physical memory layout.

bool	isInAddrMap () const
	Some memories are used as shadow memories or should for other reasons not be part of the global address map.

bool	isKvmMap () const
	When shadow memories are in use, KVM may want to make one or the other, but cannot map both into the guest address space.

void	access (PacketPtr pkt)
	Perform an untimed memory access and update all the state (e.g.

void	functionalAccess (PacketPtr pkt)
	Perform an untimed memory read or write without changing anything but the memory itself.

Public Member Functions inherited from gem5::ClockedObject
	ClockedObject (const ClockedObjectParams &p)

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::SimObject
const Params &	params () const

	SimObject (const Params &p)

virtual	~SimObject ()

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint.

virtual void	regProbePoints ()
	Register probe points for this object.

virtual void	regProbeListeners ()
	Register probe listeners for this object.

ProbeManager *	getProbeManager ()
	Get the probe manager for this object.

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index.

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining.

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes.

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers.

void	serialize (CheckpointOut &cp) const override
	Serialize an object.

void	unserialize (CheckpointIn &cp) override
	Unserialize an object.

Public Member Functions inherited from gem5::EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers.

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue.

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from gem5::Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section.

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object.

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from gem5::Drainable
DrainState	drainState () const
	Return the current drain state of an object.

virtual void	notifyFork ()
	Notify a child process of a fork.

Public Member Functions inherited from gem5::statistics::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group.

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters.

virtual void	resetStats ()
	Callback to reset stats.

virtual void	preDumpStats ()
	Callback before stats are dumped.

void	addStat (statistics::Info *info)
	Register a stat with this group.

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object.

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object.

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block.

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group.

void	mergeStatGroup (Group *block)
	Merge the contents (stats & children) of a block to this block.

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from gem5::Named
	Named (const std::string &name_)

virtual	~Named ()=default

virtual std::string	name () const

Public Member Functions inherited from gem5::Clocked
void	updateClockPeriod ()
	Update the tick to the current tick.

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle.

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge.

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future.

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Private Types
enum	PowerState { PWR_IDLE = 0 , PWR_REF , PWR_SREF , PWR_PRE_PDN , PWR_ACT , PWR_ACT_PDN }
	The power state captures the different operational states of the DRAM and interacts with the bus read/write state machine, and the refresh state machine. More...

enum	RefreshState { REF_IDLE = 0 , REF_DRAIN , REF_PD_EXIT , REF_SREF_EXIT , REF_PRE , REF_START , REF_RUN }
	The refresh state is used to control the progress of the refresh scheduling. More...

Private Member Functions
void	activateBank (Rank &rank_ref, Bank &bank_ref, Tick act_tick, uint32_t row)
	Keep track of when row activations happen, in order to enforce the maximum number of activations in the activation window.

void	prechargeBank (Rank &rank_ref, Bank &bank_ref, Tick pre_tick, bool auto_or_preall=false, bool trace=true)
	Precharge a given bank and also update when the precharge is done.

Tick	writeToReadDelay () const override

std::pair< std::vector< uint32_t >, bool >	minBankPrep (const MemPacketQueue &queue, Tick min_col_at) const
	Find which are the earliest banks ready to issue an activate for the enqueued requests.

Tick	burstDelay () const

Static Private Member Functions
static bool	sortTime (const Command &cmd, const Command &cmd_next)
	Function for sorting Command structures based on timeStamp.

Private Attributes
const uint32_t	bankGroupsPerRank
	DRAM specific device characteristics.

const bool	bankGroupArch

const Tick	tRL
	DRAM specific timing requirements.

const Tick	tWL

const Tick	tBURST_MIN

const Tick	tBURST_MAX

const Tick	tCCD_L_WR

const Tick	tCCD_L

const Tick	tRCD_RD

const Tick	tRCD_WR

const Tick	tRP

const Tick	tRAS

const Tick	tWR

const Tick	tRTP

const Tick	tRFC

const Tick	tREFI

const Tick	tRRD

const Tick	tRRD_L

const Tick	tPPD

const Tick	tAAD

const Tick	tXAW

const Tick	tXP

const Tick	tXS

const Tick	clkResyncDelay

const bool	dataClockSync

const bool	burstInterleave

const uint8_t	twoCycleActivate

const uint32_t	activationLimit

const Tick	wrToRdDlySameBG

const Tick	rdToWrDlySameBG

enums::PageManage	pageMgmt

const uint32_t	maxAccessesPerRow
	Max column accesses (read and write) per row, before forefully closing it.

uint64_t	timeStampOffset

uint8_t	activeRank

bool	enableDRAMPowerdown
	Enable or disable DRAM powerdown states.

Tick	lastStatsResetTick
	The time when stats were last reset used to calculate average power.

DRAMStats	stats

std::vector< Rank * >	ranks
	Vector of dram ranks.

Additional Inherited Members
Public Types inherited from gem5::memory::MemInterface
typedef MemInterfaceParams	Params

Public Types inherited from gem5::ClockedObject
using	Params = ClockedObjectParams
	Parameters of ClockedObject.

Public Types inherited from gem5::SimObject
typedef SimObjectParams	Params

Static Public Member Functions inherited from gem5::SimObject
static void	serializeAll (const std::string &cpt_dir)
	Create a checkpoint by serializing all SimObjects in the system.

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it.

static void	setSimObjectResolver (SimObjectResolver *resolver)
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

static SimObjectResolver *	getSimObjectResolver ()
	There is a single object name resolver, and it is only set when simulation is restoring from checkpoints.

Static Public Member Functions inherited from gem5::Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section.

static void	generateCheckpointOut (const std::string &cpt_dir, std::ofstream &outstream)
	Generate a checkpoint file so that the serialization can be routed to it.

Public Attributes inherited from gem5::memory::MemInterface
const uint32_t	readBufferSize
	Buffer sizes for read and write queues in the controller These are passed to the controller on instantiation Defining them here allows for buffers to be resized based on memory type / configuration.

const uint32_t	writeBufferSize

uint32_t	numWritesQueued
	NVM specific variable, but declaring it here allows treating different interfaces in a more genral way at the memory controller's end.

Tick	nextBurstAt = 0
	Till when the controller must wait before issuing next RD/WR burst?

Tick	nextReqTime = 0

uint32_t	readsThisTime = 0
	Reads/writes performed by the controller for this interface before bus direction is switched.

uint32_t	writesThisTime = 0

uint32_t	readQueueSize = 0
	Read/write packets in the read/write queue for this interface qos/mem_ctrl.hh has similar counters, but they track all packets in the controller for all memory interfaces connected to the controller.

uint32_t	writeQueueSize = 0

MemCtrl::BusState	busState = MemCtrl::READ

MemCtrl::BusState	busStateNext = MemCtrl::READ
	bus state for next request event triggered

uint8_t	pseudoChannel
	pseudo channel number used for HBM modeling

Public Attributes inherited from gem5::ClockedObject
PowerState *	powerState

Protected Member Functions inherited from gem5::memory::MemInterface
Tick	readToWriteDelay () const

Tick	rankToRankDelay () const

Protected Member Functions inherited from gem5::memory::AbstractMemory
bool	checkLockedAddrList (PacketPtr pkt)

void	trackLoadLocked (PacketPtr pkt)

bool	writeOK (PacketPtr pkt)

Protected Member Functions inherited from gem5::Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain.

void	signalDrainDone () const
	Signal that an object is drained.

Protected Member Functions inherited from gem5::Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters.

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance.

void	resetClock () const
	Reset the object's clock using the current global tick value.

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed.

Protected Attributes inherited from gem5::memory::MemInterface
MemCtrl *	ctrl
	A pointer to the parent memory controller instance.

unsigned int	maxCommandsPerWindow
	Number of commands that can issue in the defined controller command window, used to verify command bandwidth.

enums::AddrMap	addrMapping
	Memory controller configuration initialized based on parameter values.

const uint32_t	burstSize
	General device and channel characteristics The rowsPerBank is determined based on the capacity, number of ranks and banks, the burst size, and the row buffer size.

const uint32_t	deviceSize

const uint32_t	deviceRowBufferSize

const uint32_t	devicesPerRank

const uint32_t	rowBufferSize

const uint32_t	burstsPerRowBuffer

const uint32_t	burstsPerStripe

const uint32_t	ranksPerChannel

const uint32_t	banksPerRank

uint32_t	rowsPerBank

GEM5_CLASS_VAR_USED const Tick	tCK
	General timing requirements.

const Tick	tCS

const Tick	tBURST

const Tick	tRTW

const Tick	tWTR

Protected Attributes inherited from gem5::memory::AbstractMemory
AddrRange	range

uint8_t *	pmemAddr

MemBackdoor	backdoor

const bool	confTableReported

const bool	inAddrMap

const bool	kvmMap

const bool	writeable

const bool	collectStats

std::list< LockedAddr >	lockedAddrList

System *	_system
	Pointer to the System object.

gem5::memory::AbstractMemory::MemStats	stats

Protected Attributes inherited from gem5::SimObject
const SimObjectParams &	_params
	Cached copy of the object parameters.

Protected Attributes inherited from gem5::EventManager
EventQueue *	eventq
	A pointer to this object's event queue.

Detailed Description

Interface to DRAM devices with media specific parameters, statistics, and functions.

The DRAMInterface includes a class for individual ranks and per rank functions.

Definition at line 65 of file dram_interface.hh.

Member Enumeration Documentation

◆ PowerState

enum gem5::memory::DRAMInterface::PowerState

private

The power state captures the different operational states of the DRAM and interacts with the bus read/write state machine, and the refresh state machine.

PWR_IDLE : The idle state in which all banks are closed From here can transition to: PWR_REF, PWR_ACT, PWR_PRE_PDN

PWR_REF : Auto-refresh state. Will transition when refresh is complete based on power state prior to PWR_REF From here can transition to: PWR_IDLE, PWR_PRE_PDN, PWR_SREF

PWR_SREF : Self-refresh state. Entered after refresh if previous state was PWR_PRE_PDN From here can transition to: PWR_IDLE

PWR_PRE_PDN : Precharge power down state From here can transition to: PWR_REF, PWR_IDLE

PWR_ACT : Activate state in which one or more banks are open From here can transition to: PWR_IDLE, PWR_ACT_PDN

PWR_ACT_PDN : Activate power down state From here can transition to: PWR_ACT

Enumerator
PWR_IDLE
PWR_REF
PWR_SREF
PWR_PRE_PDN
PWR_ACT
PWR_ACT_PDN

Definition at line 111 of file dram_interface.hh.

◆ RefreshState

enum gem5::memory::DRAMInterface::RefreshState

private

The refresh state is used to control the progress of the refresh scheduling.

When normal operation is in progress the refresh state is idle. Once tREFI has elasped, a refresh event is triggered to start the following STM transitions which are used to issue a refresh and return back to normal operation

REF_IDLE : IDLE state used during normal operation From here can transition to: REF_DRAIN

REF_SREF_EXIT : Exiting a self-refresh; refresh event scheduled after self-refresh exit completes From here can transition to: REF_DRAIN

REF_DRAIN : Drain state in which on going accesses complete. From here can transition to: REF_PD_EXIT

REF_PD_EXIT : Evaluate pwrState and issue wakeup if needed Next state dependent on whether banks are open From here can transition to: REF_PRE, REF_START

REF_PRE : Close (precharge) all open banks From here can transition to: REF_START

REF_START : Issue refresh command and update DRAMPower stats From here can transition to: REF_RUN

REF_RUN : Refresh running, waiting for tRFC to expire From here can transition to: REF_IDLE, REF_SREF_EXIT

Enumerator
REF_IDLE
REF_DRAIN
REF_PD_EXIT
REF_SREF_EXIT
REF_PRE
REF_START
REF_RUN

Definition at line 151 of file dram_interface.hh.

Constructor & Destructor Documentation

◆ DRAMInterface()

gem5::memory::DRAMInterface::DRAMInterface ( const DRAMInterfaceParams & _p )

Member Function Documentation

◆ accessLatency()

Tick gem5::memory::DRAMInterface::accessLatency ( ) const

inlineoverridevirtual

Implements gem5::memory::MemInterface.

Definition at line 716 of file dram_interface.hh.

References tRCD_RD, tRL, and tRP.

◆ activateBank()

void gem5::memory::DRAMInterface::activateBank	(	Rank &	rank_ref,
		Bank &	bank_ref,
		Tick	act_tick,
		uint32_t	row )

private

Keep track of when row activations happen, in order to enforce the maximum number of activations in the activation window.

The method updates the time that the banks become available based on the current limits.

Parameters

rank_ref	Reference to the rank
bank_ref	Reference to the bank
act_tick	Time when the activation takes place
row	Index of the row

Definition at line 175 of file dram_interface.cc.

Referenced by doBurstAccess().

◆ addRankToRankDelay()

void gem5::memory::DRAMInterface::addRankToRankDelay ( Tick cmd_at )

overridevirtual

Add rank to rank delay to bus timing to all DRAM banks in alli ranks when access to an alternate interface is issued.

param cmd_at Time of current command used as starting point for addition of rank-to-rank delay

Implements gem5::memory::MemInterface.

Definition at line 620 of file dram_interface.cc.

References gem5::memory::MemInterface::banksPerRank, gem5::ArmISA::i, gem5::ArmISA::n, ranks, and gem5::memory::MemInterface::rankToRankDelay().

◆ allRanksDrained()

bool gem5::memory::DRAMInterface::allRanksDrained ( ) const

overridevirtual

Return true once refresh is complete for all ranks and there are no additional commands enqueued.

(only evaluated when draining) This will ensure that all banks are closed, power state is IDLE, and power stats have been updated

Returns: true if all ranks have refreshed, with no commands enqueued

Implements gem5::memory::MemInterface.

Definition at line 1005 of file dram_interface.cc.

References gem5::MipsISA::r, and ranks.

◆ burstDelay()

Tick gem5::memory::DRAMInterface::burstDelay ( ) const

inlineprivate

Definition at line 656 of file dram_interface.hh.

References burstInterleave, gem5::memory::MemInterface::tBURST, and tBURST_MAX.

◆ burstReady()

bool gem5::memory::DRAMInterface::burstReady ( MemPacket * pkt ) const

inlineoverridevirtual

Check if a burst operation can be issued to the DRAM.

Parameters

Return true if RD/WR can issue This requires the DRAM to be in the REF IDLE state

Implements gem5::memory::MemInterface.

Definition at line 755 of file dram_interface.hh.

References gem5::memory::MemPacket::rank, and ranks.

Referenced by chooseNextFRFCFS().

◆ checkRefreshState()

void gem5::memory::DRAMInterface::checkRefreshState ( uint8_t rank )

overridevirtual

Check the refresh state to determine if refresh needs to be kicked back into action after a read response.

Parameters

rank	Specifies rank associated with read burst

Reimplemented from gem5::memory::MemInterface.

Definition at line 978 of file dram_interface.cc.

References gem5::curTick(), gem5::memory::DRAMInterface::Rank::prechargeEvent, ranks, REF_PRE, gem5::memory::DRAMInterface::Rank::refreshEvent, gem5::memory::DRAMInterface::Rank::refreshState, gem5::EventManager::schedule(), and gem5::Event::scheduled().

◆ chooseNextFRFCFS()

std::pair< MemPacketQueue::iterator, Tick > gem5::memory::DRAMInterface::chooseNextFRFCFS	(	MemPacketQueue &	queue,
		Tick	min_col_at ) const

overridevirtual

For FR-FCFS policy, find first DRAM command that can issue.

Parameters

queue	Queued requests to consider
min_col_at	Minimum tick for 'seamless' issue

Returns: an iterator to the selected packet, else queue.end(); the tick when the packet selected will issue

Implements gem5::memory::MemInterface.

Definition at line 60 of file dram_interface.cc.

References gem5::memory::MemPacket::bank, gem5::bits(), burstReady(), DPRINTF, gem5::ArmISA::i, gem5::memory::MemPacket::isDram(), gem5::memory::MemPacket::isRead(), gem5::MaxTick, minBankPrep(), gem5::memory::MemInterface::Bank::openRow, gem5::memory::MemInterface::pseudoChannel, gem5::memory::MemPacket::pseudoChannel, gem5::memory::MemPacket::rank, ranks, gem5::memory::MemInterface::ranksPerChannel, gem5::memory::MemInterface::Bank::rdAllowedAt, gem5::memory::MemPacket::row, and gem5::memory::MemInterface::Bank::wrAllowedAt.

◆ chooseRead()

void gem5::memory::DRAMInterface::chooseRead ( MemPacketQueue & queue )

inlineoverridevirtual

This function is NVM specific.

Reimplemented from gem5::memory::MemInterface.

Definition at line 800 of file dram_interface.hh.

◆ commandOffset()

Tick gem5::memory::DRAMInterface::commandOffset ( ) const

inlineoverridevirtual

Implements gem5::memory::MemInterface.

Definition at line 708 of file dram_interface.hh.

References tRCD_RD, tRCD_WR, and tRP.

Referenced by gem5::memory::HBMCtrl::startup().

◆ decodePacket()

MemPacket * gem5::memory::DRAMInterface::decodePacket	(	const PacketPtr	pkt,
		Addr	pkt_addr,
		unsigned int	size,
		bool	is_read,
		uint8_t	pseudo_channel = 0 )

overridevirtual

Address decoder to figure out physical mapping onto ranks, banks, and rows.

This function is called multiple times on the same system packet if the pakcet is larger than burst of the memory. The pkt_addr is used for the offset within the packet.

Parameters

pkt	The packet from the outside world
pkt_addr	The starting address of the packet
size	The size of the packet in bytes
is_read	Is the request for a read or a write to memory
pseudo_channel	pseudo channel number of the packet

Returns: A MemPacket pointer with the decoded information

Reimplemented from gem5::memory::MemInterface.

Definition at line 835 of file dram_interface.cc.

References gem5::X86ISA::addr, gem5::memory::MemInterface::addrMapping, gem5::memory::MemInterface::banksPerRank, gem5::memory::MemInterface::burstSize, gem5::memory::MemInterface::burstsPerRowBuffer, gem5::memory::MemInterface::burstsPerStripe, DPRINTF, gem5::memory::MemInterface::getCtrlAddr(), panic, gem5::memory::MemInterface::ranksPerChannel, gem5::memory::MemInterface::rowsPerBank, and gem5::memory::AbstractMemory::size().

◆ doBurstAccess()

std::pair< Tick, Tick > gem5::memory::DRAMInterface::doBurstAccess	(	MemPacket *	mem_pkt,
		Tick	next_burst_at,
		const std::vector< MemPacketQueue > &	queue )

overridevirtual

Actually do the burst - figure out the latency it will take to service the req based on bank state, channel state etc and then update those states to account for this request.

Based on this, update the packet's "readyTime" and move it to the response q from where it will eventually go back to the outside world.

Parameters

mem_pkt	The packet created from the outside world pkt
next_burst_at	Minimum bus timing requirement from controller
queue	Reference to the read or write queue with the packet

Returns: pair, tick when current burst is issued and tick when next burst can issue

Implements gem5::memory::MemInterface.

Definition at line 347 of file dram_interface.cc.

◆ drainRanks()

void gem5::memory::DRAMInterface::drainRanks ( )

overridevirtual

Iterate through dram ranks to exit self-refresh in order to drain.

Reimplemented from gem5::memory::MemInterface.

Definition at line 991 of file dram_interface.cc.

References DPRINTF, PWR_SREF, gem5::MipsISA::r, ranks, and tXS.

Referenced by gem5::memory::HBMCtrl::drainResume().

◆ init()

void gem5::memory::DRAMInterface::init ( )

overridevirtual

Initialize the DRAM interface and verify parameters.

Reimplemented from gem5::SimObject.

Definition at line 742 of file dram_interface.cc.

References gem5::memory::MemInterface::addrMapping, gem5::memory::MemInterface::burstsPerRowBuffer, gem5::memory::MemInterface::burstsPerStripe, fatal, gem5::AddrRange::granularity(), gem5::SimObject::init(), gem5::AddrRange::interleaved(), gem5::Named::name(), gem5::memory::AbstractMemory::range, gem5::memory::MemInterface::rowBufferSize, and gem5::memory::AbstractMemory::system().

◆ isBusy()

bool gem5::memory::DRAMInterface::isBusy	(	bool	read_queue_empty,
		bool	all_writes_nvm )

overridevirtual

This function checks if ranks are actively refreshing and therefore busy.

The function also checks if ranks are in the self-refresh state, in which case, a self-refresh exit is initiated. The arguments are NVM-specific and will be ignored by DRAM. return boolean if all ranks are in refresh and therefore busy

Implements gem5::memory::MemInterface.

Definition at line 797 of file dram_interface.cc.

References DPRINTF, PWR_SREF, gem5::MipsISA::r, ranks, gem5::memory::MemInterface::ranksPerChannel, and tXS.

◆ minBankPrep()

std::pair< std::vector< uint32_t >, bool > gem5::memory::DRAMInterface::minBankPrep	(	const MemPacketQueue &	queue,
		Tick	min_col_at ) const

private

Find which are the earliest banks ready to issue an activate for the enqueued requests.

Assumes maximum of 32 banks per rank Also checks if the bank is already prepped.

Parameters

queue	Queued requests to consider
min_col_at	time of seamless burst command

Returns: One-hot encoded mask of bank indices; boolean indicating burst can issue seamlessly, with no gaps

Definition at line 1028 of file dram_interface.cc.

References gem5::memory::MemInterface::banksPerRank, gem5::memory::MemInterface::ctrl, gem5::curTick(), gem5::ArmISA::i, gem5::memory::MemCtrl::inReadBusState(), gem5::MaxTick, gem5::MipsISA::p, gem5::memory::MemInterface::pseudoChannel, ranks, gem5::memory::MemInterface::ranksPerChannel, gem5::replaceBits(), tRCD_RD, tRCD_WR, and tRP.

Referenced by chooseNextFRFCFS().

◆ prechargeBank()

void gem5::memory::DRAMInterface::prechargeBank	(	Rank &	rank_ref,
		Bank &	bank_ref,
		Tick	pre_tick,
		bool	auto_or_preall = false,
		bool	trace = true )

private

Precharge a given bank and also update when the precharge is done.

This will also deal with any stats related to the accesses to the open page.

Parameters

rank_ref	The rank to precharge
bank_ref	The bank to precharge
pre_tick	Time when the precharge takes place
auto_or_preall	Is this an auto-precharge or precharge all command
trace	Is this an auto precharge then do not add to trace

Definition at line 284 of file dram_interface.cc.

Referenced by doBurstAccess().

◆ readsWaitingToIssue()

bool gem5::memory::DRAMInterface::readsWaitingToIssue ( ) const

inlineoverridevirtual

The next three functions are NVM-specific and will be ignored by DRAM.

Reimplemented from gem5::memory::MemInterface.

Definition at line 799 of file dram_interface.hh.

◆ respondEvent()

void gem5::memory::DRAMInterface::respondEvent ( uint8_t rank )

overridevirtual

Complete response process for DRAM when read burst is complete This will update the counters and check if a power down state can be entered.

Parameters

rank	Specifies rank associated with read burst

Reimplemented from gem5::memory::MemInterface.

Definition at line 931 of file dram_interface.cc.

◆ setupRank()

void gem5::memory::DRAMInterface::setupRank	(	const uint8_t	rank,
		const bool	is_read )

overridevirtual

Setup the rank based on packet received.

Parameters

integer	value of rank to be setup. used to index ranks vector
are	we setting up rank for read or write packet?

Implements gem5::memory::MemInterface.

Definition at line 920 of file dram_interface.cc.

References ranks.

◆ sortTime()

static bool gem5::memory::DRAMInterface::sortTime	(	const Command &	cmd,
		const Command &	cmd_next )

inlinestaticprivate

Function for sorting Command structures based on timeStamp.

Parameters

a	Memory Command
next	Memory Command

Returns: true if timeStamp of Command 1 < timeStamp of Command 2

Definition at line 487 of file dram_interface.hh.

References gem5::memory::DRAMInterface::Command::timeStamp.

Referenced by gem5::memory::DRAMInterface::Rank::flushCmdList().

◆ startup()

void gem5::memory::DRAMInterface::startup ( )

overridevirtual

Iterate through dram ranks and instantiate per rank startup routine.

Reimplemented from gem5::SimObject.

Definition at line 784 of file dram_interface.cc.

References gem5::curTick(), gem5::divCeil(), gem5::MipsISA::r, ranks, gem5::memory::AbstractMemory::system(), gem5::memory::MemInterface::tCK, timeStampOffset, tREFI, and tRP.

Referenced by gem5::memory::HBMCtrl::drainResume().

◆ suspend()

void gem5::memory::DRAMInterface::suspend ( )

overridevirtual

Iterate through DRAM ranks and suspend them.

Reimplemented from gem5::memory::MemInterface.

Definition at line 1020 of file dram_interface.cc.

References gem5::MipsISA::r, and ranks.

◆ writeRespQueueFull()

bool gem5::memory::DRAMInterface::writeRespQueueFull ( ) const

inlineoverridevirtual

This function is NVM specific.

Reimplemented from gem5::memory::MemInterface.

Definition at line 801 of file dram_interface.hh.

◆ writeToReadDelay()

Tick gem5::memory::DRAMInterface::writeToReadDelay ( ) const

inlineoverrideprivatevirtual

Reimplemented from gem5::memory::MemInterface.

Definition at line 637 of file dram_interface.hh.

References gem5::memory::MemInterface::tBURST, tWL, and gem5::memory::MemInterface::tWTR.

Referenced by doBurstAccess().

Member Data Documentation

◆ activationLimit

const uint32_t gem5::memory::DRAMInterface::activationLimit

private

Definition at line 526 of file dram_interface.hh.

Referenced by activateBank().

◆ activeRank

uint8_t gem5::memory::DRAMInterface::activeRank

private

Definition at line 542 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ bankGroupArch

const bool gem5::memory::DRAMInterface::bankGroupArch

private

Definition at line 496 of file dram_interface.hh.

Referenced by activateBank(), doBurstAccess(), and DRAMInterface().

◆ bankGroupsPerRank

const uint32_t gem5::memory::DRAMInterface::bankGroupsPerRank

private

DRAM specific device characteristics.

Definition at line 495 of file dram_interface.hh.

Referenced by DRAMInterface().

◆ burstInterleave

const bool gem5::memory::DRAMInterface::burstInterleave

private

Definition at line 524 of file dram_interface.hh.

Referenced by burstDelay(), and doBurstAccess().

◆ clkResyncDelay

const Tick gem5::memory::DRAMInterface::clkResyncDelay

private

Definition at line 522 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ dataClockSync

const bool gem5::memory::DRAMInterface::dataClockSync

private

Definition at line 523 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ enableDRAMPowerdown

bool gem5::memory::DRAMInterface::enableDRAMPowerdown

private

Enable or disable DRAM powerdown states.

Definition at line 545 of file dram_interface.hh.

Referenced by gem5::memory::DRAMInterface::Rank::inPwrIdleState(), and respondEvent().

◆ lastStatsResetTick

Tick gem5::memory::DRAMInterface::lastStatsResetTick

private

The time when stats were last reset used to calculate average power.

Definition at line 548 of file dram_interface.hh.

◆ maxAccessesPerRow

const uint32_t gem5::memory::DRAMInterface::maxAccessesPerRow

private

Max column accesses (read and write) per row, before forefully closing it.

Definition at line 536 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ pageMgmt

enums::PageManage gem5::memory::DRAMInterface::pageMgmt

private

Definition at line 531 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ ranks

std::vector<Rank*> gem5::memory::DRAMInterface::ranks

private

Vector of dram ranks.

Definition at line 632 of file dram_interface.hh.

Referenced by activateBank(), addRankToRankDelay(), allRanksDrained(), burstReady(), checkRefreshState(), chooseNextFRFCFS(), doBurstAccess(), drainRanks(), DRAMInterface(), isBusy(), minBankPrep(), respondEvent(), setupRank(), startup(), and suspend().

◆ rdToWrDlySameBG

const Tick gem5::memory::DRAMInterface::rdToWrDlySameBG

private

Definition at line 528 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ stats

DRAMStats gem5::memory::DRAMInterface::stats

private

Definition at line 627 of file dram_interface.hh.

Referenced by gem5::memory::DRAMInterface::Rank::computeStats(), doBurstAccess(), prechargeBank(), gem5::memory::DRAMInterface::Rank::processPowerEvent(), and gem5::memory::DRAMInterface::Rank::updatePowerStats().

◆ tAAD

const Tick gem5::memory::DRAMInterface::tAAD

private

Definition at line 518 of file dram_interface.hh.

Referenced by activateBank().

◆ tBURST_MAX

const Tick gem5::memory::DRAMInterface::tBURST_MAX

private

Definition at line 504 of file dram_interface.hh.

Referenced by burstDelay().

◆ tBURST_MIN

const Tick gem5::memory::DRAMInterface::tBURST_MIN

private

Definition at line 503 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ tCCD_L

const Tick gem5::memory::DRAMInterface::tCCD_L

private

Definition at line 506 of file dram_interface.hh.

Referenced by doBurstAccess(), and DRAMInterface().

◆ tCCD_L_WR

const Tick gem5::memory::DRAMInterface::tCCD_L_WR

private

Definition at line 505 of file dram_interface.hh.

Referenced by doBurstAccess(), and DRAMInterface().

◆ timeStampOffset

uint64_t gem5::memory::DRAMInterface::timeStampOffset

private

Definition at line 539 of file dram_interface.hh.

Referenced by activateBank(), doBurstAccess(), prechargeBank(), and startup().

◆ tPPD

const Tick gem5::memory::DRAMInterface::tPPD

private

Definition at line 517 of file dram_interface.hh.

Referenced by prechargeBank().

◆ tRAS

const Tick gem5::memory::DRAMInterface::tRAS

private

Definition at line 510 of file dram_interface.hh.

Referenced by activateBank().

◆ tRCD_RD

const Tick gem5::memory::DRAMInterface::tRCD_RD

private

Definition at line 507 of file dram_interface.hh.

Referenced by accessLatency(), activateBank(), commandOffset(), and minBankPrep().

◆ tRCD_WR

const Tick gem5::memory::DRAMInterface::tRCD_WR

private

Definition at line 508 of file dram_interface.hh.

Referenced by activateBank(), commandOffset(), and minBankPrep().

◆ tREFI

const Tick gem5::memory::DRAMInterface::tREFI

private

Definition at line 514 of file dram_interface.hh.

Referenced by DRAMInterface(), and startup().

◆ tRFC

const Tick gem5::memory::DRAMInterface::tRFC

private

Definition at line 513 of file dram_interface.hh.

Referenced by DRAMInterface().

◆ tRL

const Tick gem5::memory::DRAMInterface::tRL

private

DRAM specific timing requirements.

Definition at line 501 of file dram_interface.hh.

Referenced by accessLatency(), and doBurstAccess().

◆ tRP

const Tick gem5::memory::DRAMInterface::tRP

private

Definition at line 509 of file dram_interface.hh.

Referenced by accessLatency(), commandOffset(), DRAMInterface(), minBankPrep(), prechargeBank(), and startup().

◆ tRRD

const Tick gem5::memory::DRAMInterface::tRRD

private

Definition at line 515 of file dram_interface.hh.

Referenced by activateBank(), and DRAMInterface().

◆ tRRD_L

const Tick gem5::memory::DRAMInterface::tRRD_L

private

Definition at line 516 of file dram_interface.hh.

Referenced by activateBank(), and DRAMInterface().

◆ tRTP

const Tick gem5::memory::DRAMInterface::tRTP

private

Definition at line 512 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ tWL

const Tick gem5::memory::DRAMInterface::tWL

private

Definition at line 502 of file dram_interface.hh.

Referenced by doBurstAccess(), and writeToReadDelay().

◆ twoCycleActivate

const uint8_t gem5::memory::DRAMInterface::twoCycleActivate

private

Definition at line 525 of file dram_interface.hh.

Referenced by activateBank().

◆ tWR

const Tick gem5::memory::DRAMInterface::tWR

private

Definition at line 511 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ tXAW

const Tick gem5::memory::DRAMInterface::tXAW

private

Definition at line 519 of file dram_interface.hh.

Referenced by activateBank().

◆ tXP

const Tick gem5::memory::DRAMInterface::tXP

private

Definition at line 520 of file dram_interface.hh.

Referenced by doBurstAccess().

◆ tXS

const Tick gem5::memory::DRAMInterface::tXS

private

Definition at line 521 of file dram_interface.hh.

Referenced by drainRanks(), and isBusy().

◆ wrToRdDlySameBG

const Tick gem5::memory::DRAMInterface::wrToRdDlySameBG

private

Definition at line 527 of file dram_interface.hh.

Referenced by doBurstAccess().

The documentation for this class was generated from the following files:

mem/dram_interface.hh
mem/dram_interface.cc

Classes

Public Member Functions

Private Types

Private Member Functions

Static Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Enumeration Documentation

◆ PowerState

◆ RefreshState

Constructor & Destructor Documentation

◆ DRAMInterface()

Member Function Documentation

◆ accessLatency()

◆ activateBank()

◆ addRankToRankDelay()

◆ allRanksDrained()

◆ burstDelay()

◆ burstReady()

◆ checkRefreshState()

◆ chooseNextFRFCFS()

◆ chooseRead()

◆ commandOffset()

◆ decodePacket()

◆ doBurstAccess()

◆ drainRanks()

◆ init()

◆ isBusy()

◆ minBankPrep()

◆ prechargeBank()

◆ readsWaitingToIssue()

◆ respondEvent()

◆ setupRank()

◆ sortTime()

◆ startup()

◆ suspend()

◆ writeRespQueueFull()

◆ writeToReadDelay()

Member Data Documentation

◆ activationLimit

◆ activeRank

◆ bankGroupArch

◆ bankGroupsPerRank

◆ burstInterleave

◆ clkResyncDelay

◆ dataClockSync

◆ enableDRAMPowerdown

◆ lastStatsResetTick

◆ maxAccessesPerRow

◆ pageMgmt

◆ ranks

◆ rdToWrDlySameBG

◆ stats

◆ tAAD

◆ tBURST_MAX

◆ tBURST_MIN

◆ tCCD_L

◆ tCCD_L_WR

◆ timeStampOffset

◆ tPPD

◆ tRAS

◆ tRCD_RD

◆ tRCD_WR

◆ tREFI

◆ tRFC

◆ tRL

◆ tRP

◆ tRRD

◆ tRRD_L

◆ tRTP

◆ tWL

◆ twoCycleActivate

◆ tWR

◆ tXAW

◆ tXP

◆ tXS

◆ wrToRdDlySameBG