gem5  v22.1.0.0
compressed.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015 RISC-V Foundation
3  * Copyright (c) 2017 The University of Virginia
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
31 #define __ARCH_RISCV_INSTS_COMPRESSED_HH__
32 
33 #include <string>
34 
36 #include "cpu/static_inst.hh"
37 
38 namespace gem5
39 {
40 
41 namespace RiscvISA
42 {
43 
47 class CompRegOp : public RiscvStaticInst
48 {
49  protected:
51 
52  std::string generateDisassembly(
53  Addr pc, const loader::SymbolTable *symtab) const override;
54 };
55 
56 } // namespace RiscvISA
57 } // namespace gem5
58 
59 #endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
Base class for compressed operations that work only on registers.
Definition: compressed.hh:48
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: compressed.cc:45
Base class for all RISC-V static instructions.
Definition: static_inst.hh:52
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition: static_inst.hh:54
Bitfield< 4 > pc
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147

Generated on Wed Dec 21 2022 10:22:27 for gem5 by doxygen 1.9.1