gem5
v21.2.1.1
arch
riscv
insts
compressed.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2015 RISC-V Foundation
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* Copyright (c) 2017 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_RISCV_INSTS_COMPRESSED_HH__
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#define __ARCH_RISCV_INSTS_COMPRESSED_HH__
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#include <string>
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#include "
arch/riscv/insts/static_inst.hh
"
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#include "
cpu/static_inst.hh
"
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namespace
gem5
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{
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namespace
RiscvISA
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{
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class
CompRegOp
:
public
RiscvStaticInst
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{
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protected
:
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using
RiscvStaticInst::RiscvStaticInst
;
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std::string
generateDisassembly
(
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Addr
pc
,
const
loader::SymbolTable
*symtab)
const override
;
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};
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}
// namespace RiscvISA
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}
// namespace gem5
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#endif // __ARCH_RISCV_INSTS_COMPRESSED_HH__
gem5::RiscvISA::RiscvStaticInst
Base class for all RISC-V static instructions.
Definition:
static_inst.hh:51
gem5::RiscvISA::RiscvStaticInst::RiscvStaticInst
RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
Definition:
static_inst.hh:54
gem5::loader::SymbolTable
Definition:
symtab.hh:65
gem5::RiscvISA::pc
Bitfield< 4 > pc
Definition:
pra_constants.hh:243
gem5::RiscvISA::CompRegOp
Base class for compressed operations that work only on registers.
Definition:
compressed.hh:47
static_inst.hh
static_inst.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:147
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
tlb.cc:60
gem5::RiscvISA::CompRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition:
compressed.cc:45
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