gem5 v24.0.0.0
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compressed.cc
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1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
31
32#include <sstream>
33#include <string>
34
35#include "arch/riscv/utility.hh"
36#include "cpu/static_inst.hh"
37
38namespace gem5
39{
40
41namespace RiscvISA
42{
43
44std::string
46 Addr pc, const loader::SymbolTable *symtab) const
47{
48 std::stringstream ss;
49 ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
51 return ss.str();
52}
53
54} // namespace RiscvISA
55} // namespace gem5
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition compressed.cc:45
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
const char * mnemonic
Base mnemonic (e.g., "add").
const RegId & srcRegIdx(int i) const
Return logical index (architectural reg num) of i'th source reg.
std::string registerName(RegId reg)
Definition utility.hh:130
Bitfield< 11, 8 > ss
Bitfield< 4 > pc
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

Generated on Tue Jun 18 2024 16:24:00 for gem5 by doxygen 1.11.0