gem5 v24.0.0.0
Loading...
Searching...
No Matches
Namespaces | Enumerations | Functions | Variables
dsp.hh File Reference
#include "arch/mips/types.hh"
#include "base/logging.hh"
#include "base/types.hh"

Go to the source code of this file.

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::MipsISA
 

Enumerations

enum  {
  gem5::MipsISA::SIMD_FMT_L , gem5::MipsISA::SIMD_FMT_W , gem5::MipsISA::SIMD_FMT_PH , gem5::MipsISA::SIMD_FMT_QB ,
  gem5::MipsISA::SIMD_NUM_FMTS
}
 
enum  {
  gem5::MipsISA::DSP_POS , gem5::MipsISA::DSP_SCOUNT , gem5::MipsISA::DSP_C , gem5::MipsISA::DSP_OUFLAG ,
  gem5::MipsISA::DSP_CCOND , gem5::MipsISA::DSP_EFI , gem5::MipsISA::DSP_NUM_FIELDS
}
 
enum  { gem5::MipsISA::CMP_EQ , gem5::MipsISA::CMP_LT , gem5::MipsISA::CMP_LE }
 
enum  {
  gem5::MipsISA::MODE_L , gem5::MipsISA::MODE_R , gem5::MipsISA::MODE_LA , gem5::MipsISA::MODE_RA ,
  gem5::MipsISA::MODE_X
}
 
enum  { gem5::MipsISA::UNSIGNED , gem5::MipsISA::SIGNED }
 
enum  { gem5::MipsISA::NOSATURATE , gem5::MipsISA::SATURATE }
 
enum  { gem5::MipsISA::NOROUND , gem5::MipsISA::ROUND }
 

Functions

int32_t gem5::MipsISA::bitrev (int32_t value)
 
uint64_t gem5::MipsISA::dspSaturate (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
 
uint64_t gem5::MipsISA::checkOverflow (uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
 
uint64_t gem5::MipsISA::signExtend (uint64_t value, int32_t signpos)
 
uint64_t gem5::MipsISA::addHalfLsb (uint64_t value, int32_t lsbpos)
 
int32_t gem5::MipsISA::dspAbs (int32_t a, int32_t fmt, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspAdd (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspAddh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
 
int32_t gem5::MipsISA::dspSub (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspSubh (int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
 
int32_t gem5::MipsISA::dspShll (int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspShrl (int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
 
int32_t gem5::MipsISA::dspShra (int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspMul (int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspMulq (int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspMuleu (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspMuleq (int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
 
int64_t gem5::MipsISA::dspDpaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
 
int64_t gem5::MipsISA::dspDpsq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
 
int64_t gem5::MipsISA::dspDpa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
 
int64_t gem5::MipsISA::dspDps (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
 
int64_t gem5::MipsISA::dspMaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
 
int64_t gem5::MipsISA::dspMulsa (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
 
int64_t gem5::MipsISA::dspMulsaq (int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)
 
void gem5::MipsISA::dspCmp (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspCmpg (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
 
int32_t gem5::MipsISA::dspCmpgd (int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspPrece (int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)
 
int32_t gem5::MipsISA::dspPrecrqu (int32_t a, int32_t b, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspPrecrq (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspPrecrSra (int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)
 
int32_t gem5::MipsISA::dspPick (int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspPack (int32_t a, int32_t b, int32_t fmt)
 
int32_t gem5::MipsISA::dspExtr (int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspExtp (int64_t dspac, int32_t size, uint32_t *dspctl)
 
int32_t gem5::MipsISA::dspExtpd (int64_t dspac, int32_t size, uint32_t *dspctl)
 
void gem5::MipsISA::simdPack (uint64_t *values_ptr, int32_t *reg, int32_t fmt)
 
void gem5::MipsISA::simdUnpack (int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
 
void gem5::MipsISA::writeDSPControl (uint32_t *dspctl, uint32_t value, uint32_t mask)
 
uint32_t gem5::MipsISA::readDSPControl (uint32_t *dspctl, uint32_t mask)
 

Variables

const uint32_t gem5::MipsISA::DSP_CTL_POS [DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 }
 
const uint32_t gem5::MipsISA::DSP_CTL_MASK [DSP_NUM_FIELDS]
 
const uint32_t gem5::MipsISA::SIMD_MAX_VALS = 4
 
const uint32_t gem5::MipsISA::SIMD_NVALS [SIMD_NUM_FMTS] = { 1, 1, 2, 4 }
 
const uint32_t gem5::MipsISA::SIMD_NBITS [SIMD_NUM_FMTS] = { 64, 32, 16, 8 }
 
const uint32_t gem5::MipsISA::SIMD_LOG2N [SIMD_NUM_FMTS] = { 6, 5, 4, 3 }
 
const uint64_t gem5::MipsISA::FIXED_L_SMAX = 0x7fffffffffffffffULL
 
const uint64_t gem5::MipsISA::FIXED_W_SMAX = 0x000000007fffffffULL
 
const uint64_t gem5::MipsISA::FIXED_H_SMAX = 0x0000000000007fffULL
 
const uint64_t gem5::MipsISA::FIXED_B_SMAX = 0x000000000000007fULL
 
const uint64_t gem5::MipsISA::FIXED_L_UMAX = 0xffffffffffffffffULL
 
const uint64_t gem5::MipsISA::FIXED_W_UMAX = 0x00000000ffffffffULL
 
const uint64_t gem5::MipsISA::FIXED_H_UMAX = 0x000000000000ffffULL
 
const uint64_t gem5::MipsISA::FIXED_B_UMAX = 0x00000000000000ffULL
 
const uint64_t gem5::MipsISA::FIXED_SMAX [SIMD_NUM_FMTS]
 
const uint64_t gem5::MipsISA::FIXED_UMAX [SIMD_NUM_FMTS]
 
const uint64_t gem5::MipsISA::FIXED_L_SMIN = 0x8000000000000000ULL
 
const uint64_t gem5::MipsISA::FIXED_W_SMIN = 0xffffffff80000000ULL
 
const uint64_t gem5::MipsISA::FIXED_H_SMIN = 0xffffffffffff8000ULL
 
const uint64_t gem5::MipsISA::FIXED_B_SMIN = 0xffffffffffffff80ULL
 
const uint64_t gem5::MipsISA::FIXED_L_UMIN = 0x0000000000000000ULL
 
const uint64_t gem5::MipsISA::FIXED_W_UMIN = 0x0000000000000000ULL
 
const uint64_t gem5::MipsISA::FIXED_H_UMIN = 0x0000000000000000ULL
 
const uint64_t gem5::MipsISA::FIXED_B_UMIN = 0x0000000000000000ULL
 
const uint64_t gem5::MipsISA::FIXED_SMIN [SIMD_NUM_FMTS]
 
const uint64_t gem5::MipsISA::FIXED_UMIN [SIMD_NUM_FMTS]
 
Generated on Tue Jun 18 2024 16:24:08 for gem5 by doxygen 1.11.0