gem5  v22.0.0.1
dsp.hh
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1 /*
2  * Copyright (c) 2007 MIPS Technologies, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #ifndef __ARCH_MIPS_DSP_HH__
30 #define __ARCH_MIPS_DSP_HH__
31 
32 #include "arch/mips/types.hh"
33 #include "base/logging.hh"
34 #include "base/types.hh"
35 
36 namespace gem5
37 {
38 
39 class ThreadContext;
40 
41 namespace MipsISA {
42 
43 // SIMD formats
44 enum
45 {
46  SIMD_FMT_L, // long word
47  SIMD_FMT_W, // word
48  SIMD_FMT_PH, // paired halfword
49  SIMD_FMT_QB, // quad byte
51 };
52 
53 // DSPControl Fields
54 enum
55 {
56  DSP_POS, // insertion bitfield position
57  DSP_SCOUNT, // insertion bitfield size
58  DSP_C, // carry bit
59  DSP_OUFLAG, // overflow-underflow flag
60  DSP_CCOND, // condition code
61  DSP_EFI, // extract fail indicator bit
63 };
64 
65 // compare instruction operations
66 enum
67 {
68  CMP_EQ, // equal
69  CMP_LT, // less than
70  CMP_LE // less than or equal
71 };
72 
73 // SIMD operation order modes
74 enum
75 {
76  MODE_L, // left
77  MODE_R, // right
78  MODE_LA, // left-alternate
79  MODE_RA, // right-alternate
80  MODE_X // cross
81 };
82 
83 // dsp operation parameters
84 enum { UNSIGNED, SIGNED };
85 enum { NOSATURATE, SATURATE };
86 enum { NOROUND, ROUND };
87 
88 // DSPControl field positions and masks
89 const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
90 const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] =
91 { 0x0000003f, 0x00001f80, 0x00002000,
92  0x00ff0000, 0x0f000000, 0x00004000 };
93 
94 /*
95  * SIMD format constants
96  */
97 
98 // maximum values per register
99 const uint32_t SIMD_MAX_VALS = 4;
100 // number of values in fmt
101 const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 };
102 // number of bits per value
103 const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 };
104 // log2(bits per value)
105 const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 };
106 
107 
108 // DSP maximum values
109 const uint64_t FIXED_L_SMAX = 0x7fffffffffffffffULL;
110 const uint64_t FIXED_W_SMAX = 0x000000007fffffffULL;
111 const uint64_t FIXED_H_SMAX = 0x0000000000007fffULL;
112 const uint64_t FIXED_B_SMAX = 0x000000000000007fULL;
113 const uint64_t FIXED_L_UMAX = 0xffffffffffffffffULL;
114 const uint64_t FIXED_W_UMAX = 0x00000000ffffffffULL;
115 const uint64_t FIXED_H_UMAX = 0x000000000000ffffULL;
116 const uint64_t FIXED_B_UMAX = 0x00000000000000ffULL;
117 const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] =
119 const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] =
121 
122 // DSP minimum values
123 const uint64_t FIXED_L_SMIN = 0x8000000000000000ULL;
124 const uint64_t FIXED_W_SMIN = 0xffffffff80000000ULL;
125 const uint64_t FIXED_H_SMIN = 0xffffffffffff8000ULL;
126 const uint64_t FIXED_B_SMIN = 0xffffffffffffff80ULL;
127 const uint64_t FIXED_L_UMIN = 0x0000000000000000ULL;
128 const uint64_t FIXED_W_UMIN = 0x0000000000000000ULL;
129 const uint64_t FIXED_H_UMIN = 0x0000000000000000ULL;
130 const uint64_t FIXED_B_UMIN = 0x0000000000000000ULL;
131 const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] =
133 const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] =
135 
136 // DSP utility functions
137 int32_t bitrev(int32_t value);
138 uint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign,
139  uint32_t *overflow);
140 uint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign,
141  uint32_t *overflow);
142 uint64_t signExtend(uint64_t value, int32_t signpos);
143 uint64_t addHalfLsb(uint64_t value, int32_t lsbpos);
144 int32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl);
145 int32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
146  int32_t sign, uint32_t *dspctl);
147 int32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round,
148  int32_t sign);
149 int32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
150  int32_t sign, uint32_t *dspctl);
151 int32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round,
152  int32_t sign);
153 int32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate,
154  int32_t sign, uint32_t *dspctl);
155 int32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign);
156 int32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round,
157  int32_t sign, uint32_t *dspctl);
158 int32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
159  uint32_t *dspctl);
160 int32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate,
161  int32_t round, uint32_t *dspctl);
162 int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
163 int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl);
164 int64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
165  int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
166  uint32_t *dspctl);
167 int64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
168  int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
169  uint32_t *dspctl);
170 int64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
171  int32_t sign, int32_t mode);
172 int64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
173  int32_t sign, int32_t mode);
174 int64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac,
175  int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl);
176 int64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt);
177 int64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt,
178  uint32_t *dspctl);
179 void dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
180  uint32_t *dspctl);
181 int32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op);
182 int32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op,
183  uint32_t *dspctl);
184 int32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt,
185  int32_t outsign, int32_t mode);
186 int32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl);
187 int32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
188 int32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt,
189  int32_t round);
190 int32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl);
191 int32_t dspPack(int32_t a, int32_t b, int32_t fmt);
192 int32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
193  int32_t saturate, uint32_t *dspctl);
194 int32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl);
195 int32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl);
196 
197 // SIMD pack/unpack utility functions
198 void simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt);
199 void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign);
200 
201 // DSPControl r/w utility functions
202 void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask);
203 uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask);
204 
205 } // namespace MipsISA
206 } // namespace gem5
207 
208 #endif // __ARCH_MIPS_DSP_HH__
gem5::MipsISA::DSP_CTL_MASK
const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS]
Definition: dsp.hh:90
gem5::MipsISA::FIXED_W_UMIN
const uint64_t FIXED_W_UMIN
Definition: dsp.hh:128
gem5::MipsISA::mask
mask
Definition: pra_constants.hh:73
gem5::MipsISA::SIMD_FMT_W
@ SIMD_FMT_W
Definition: dsp.hh:47
gem5::MipsISA::SIMD_LOG2N
const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS]
Definition: dsp.hh:105
gem5::MipsISA::dspShrl
int32_t dspShrl(int32_t a, uint32_t sa, int32_t fmt, int32_t sign)
Definition: dsp.cc:306
gem5::MipsISA::SIMD_MAX_VALS
const uint32_t SIMD_MAX_VALS
Definition: dsp.hh:99
gem5::MipsISA::CMP_EQ
@ CMP_EQ
Definition: dsp.hh:68
types.hh
gem5::MipsISA::dspExtp
int32_t dspExtp(int64_t dspac, int32_t size, uint32_t *dspctl)
Definition: dsp.cc:1083
gem5::MipsISA::dspExtpd
int32_t dspExtpd(int64_t dspac, int32_t size, uint32_t *dspctl)
Definition: dsp.cc:1103
gem5::MipsISA::dspMul
int32_t dspMul(int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl)
Definition: dsp.cc:390
gem5::MipsISA::MODE_LA
@ MODE_LA
Definition: dsp.hh:78
gem5::MipsISA::dspCmpg
int32_t dspCmpg(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op)
Definition: dsp.cc:803
gem5::MipsISA::dspMuleq
int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:456
gem5::MipsISA::dspMulq
int32_t dspMulq(int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl)
Definition: dsp.cc:349
gem5::MipsISA::writeDSPControl
void writeDSPControl(uint32_t *dspctl, uint32_t value, uint32_t mask)
Definition: dsp.cc:1161
gem5::MipsISA::FIXED_W_SMAX
const uint64_t FIXED_W_SMAX
Definition: dsp.hh:110
sc_dt::overflow
static void overflow(double &c, const scfx_params &params, bool &o_flag)
Definition: sc_fxnum.cc:459
gem5::MipsISA::DSP_EFI
@ DSP_EFI
Definition: dsp.hh:61
gem5::MipsISA::MODE_L
@ MODE_L
Definition: dsp.hh:76
gem5::MipsISA::FIXED_H_SMAX
const uint64_t FIXED_H_SMAX
Definition: dsp.hh:111
gem5::MipsISA::SIMD_NBITS
const uint32_t SIMD_NBITS[SIMD_NUM_FMTS]
Definition: dsp.hh:103
gem5::MipsISA::MODE_R
@ MODE_R
Definition: dsp.hh:77
gem5::MipsISA::bitrev
int32_t bitrev(int32_t value)
Definition: dsp.cc:42
gem5::MipsISA::SIMD_FMT_L
@ SIMD_FMT_L
Definition: dsp.hh:46
gem5::MipsISA::a
Bitfield< 13 > a
Definition: mt_constants.hh:92
gem5::MipsISA::SIMD_FMT_QB
@ SIMD_FMT_QB
Definition: dsp.hh:49
gem5::MipsISA::FIXED_SMIN
const uint64_t FIXED_SMIN[SIMD_NUM_FMTS]
Definition: dsp.hh:131
gem5::MipsISA::dspCmp
void dspCmp(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
Definition: dsp.cc:770
gem5::MipsISA::dspCmpgd
int32_t dspCmpgd(int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl)
Definition: dsp.cc:835
gem5::MipsISA::DSP_CTL_POS
const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS]
Definition: dsp.hh:89
gem5::MipsISA::checkOverflow
uint64_t checkOverflow(uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
Definition: dsp.cc:90
gem5::MipsISA::FIXED_L_SMIN
const uint64_t FIXED_L_SMIN
Definition: dsp.hh:123
gem5::MipsISA::FIXED_W_SMIN
const uint64_t FIXED_W_SMIN
Definition: dsp.hh:124
gem5::MipsISA::SIMD_FMT_PH
@ SIMD_FMT_PH
Definition: dsp.hh:48
gem5::MipsISA::SIMD_NUM_FMTS
@ SIMD_NUM_FMTS
Definition: dsp.hh:50
gem5::MipsISA::MODE_RA
@ MODE_RA
Definition: dsp.hh:79
gem5::MipsISA::dspDpa
int64_t dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
Definition: dsp.cc:627
gem5::MipsISA::DSP_C
@ DSP_C
Definition: dsp.hh:58
gem5::MipsISA::dspSubh
int32_t dspSubh(int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
Definition: dsp.cc:252
gem5::MipsISA::sa
Bitfield< 3, 0 > sa
Definition: pra_constants.hh:259
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::MipsISA::DSP_SCOUNT
@ DSP_SCOUNT
Definition: dsp.hh:57
gem5::MipsISA::dspMaq
int64_t dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl)
Definition: dsp.cc:683
gem5::MipsISA::FIXED_W_UMAX
const uint64_t FIXED_W_UMAX
Definition: dsp.hh:114
gem5::MipsISA::FIXED_L_SMAX
const uint64_t FIXED_L_SMAX
Definition: dsp.hh:109
gem5::MipsISA::dspDps
int64_t dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode)
Definition: dsp.cc:655
gem5::MipsISA::dspPrece
int32_t dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode)
Definition: dsp.cc:872
gem5::MipsISA::DSP_NUM_FIELDS
@ DSP_NUM_FIELDS
Definition: dsp.hh:62
gem5::MipsISA::dspMuleu
int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:422
gem5::MipsISA::NOSATURATE
@ NOSATURATE
Definition: dsp.hh:85
gem5::MipsISA::NOROUND
@ NOROUND
Definition: dsp.hh:86
gem5::MipsISA::DSP_POS
@ DSP_POS
Definition: dsp.hh:56
gem5::MipsISA::SIGNED
@ SIGNED
Definition: dsp.hh:84
gem5::MipsISA::dspDpsq
int64_t dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:560
gem5::MipsISA::FIXED_L_UMAX
const uint64_t FIXED_L_UMAX
Definition: dsp.hh:113
gem5::MipsISA::FIXED_L_UMIN
const uint64_t FIXED_L_UMIN
Definition: dsp.hh:127
gem5::MipsISA::dspSub
int32_t dspSub(int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:221
gem5::MipsISA::readDSPControl
uint32_t readDSPControl(uint32_t *dspctl, uint32_t mask)
Definition: dsp.cc:1178
gem5::MipsISA::signExtend
uint64_t signExtend(uint64_t value, int32_t signpos)
Definition: dsp.cc:113
gem5::MipsISA::FIXED_H_UMAX
const uint64_t FIXED_H_UMAX
Definition: dsp.hh:115
gem5::MipsISA::FIXED_B_UMIN
const uint64_t FIXED_B_UMIN
Definition: dsp.hh:130
gem5::MipsISA::dspMulsa
int64_t dspMulsa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt)
Definition: dsp.cc:727
gem5::MipsISA::dspPrecrqu
int32_t dspPrecrqu(int32_t a, int32_t b, uint32_t *dspctl)
Definition: dsp.cc:914
gem5::X86ISA::ac
Bitfield< 18 > ac
Definition: misc.hh:561
gem5::MipsISA::ROUND
@ ROUND
Definition: dsp.hh:86
gem5::MipsISA::FIXED_UMAX
const uint64_t FIXED_UMAX[SIMD_NUM_FMTS]
Definition: dsp.hh:119
gem5::MipsISA::CMP_LT
@ CMP_LT
Definition: dsp.hh:69
gem5::MipsISA::dspAbs
int32_t dspAbs(int32_t a, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:134
gem5::MipsISA::dspSaturate
uint64_t dspSaturate(uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow)
Definition: dsp.cc:60
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::MipsISA::FIXED_B_SMIN
const uint64_t FIXED_B_SMIN
Definition: dsp.hh:126
gem5::MipsISA::FIXED_H_UMIN
const uint64_t FIXED_H_UMIN
Definition: dsp.hh:129
gem5::MipsISA::dspPrecrq
int32_t dspPrecrq(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:943
gem5::MipsISA::FIXED_UMIN
const uint64_t FIXED_UMIN[SIMD_NUM_FMTS]
Definition: dsp.hh:133
gem5::MipsISA::MODE_X
@ MODE_X
Definition: dsp.hh:80
gem5::MipsISA::dspAddh
int32_t dspAddh(int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign)
Definition: dsp.cc:197
gem5::MipsISA::FIXED_B_SMAX
const uint64_t FIXED_B_SMAX
Definition: dsp.hh:112
types.hh
gem5::MipsISA::dspPick
int32_t dspPick(int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:996
gem5::MipsISA::FIXED_SMAX
const uint64_t FIXED_SMAX[SIMD_NUM_FMTS]
Definition: dsp.hh:117
gem5::MipsISA::SATURATE
@ SATURATE
Definition: dsp.hh:85
gem5::MipsISA::dspAdd
int32_t dspAdd(int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:165
gem5::MipsISA::dspShra
int32_t dspShra(int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:325
logging.hh
gem5::MipsISA::dspDpaq
int64_t dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl)
Definition: dsp.cc:493
gem5::MipsISA::addHalfLsb
uint64_t addHalfLsb(uint64_t value, int32_t lsbpos)
Definition: dsp.cc:128
gem5::MipsISA::SIMD_NVALS
const uint32_t SIMD_NVALS[SIMD_NUM_FMTS]
Definition: dsp.hh:101
gem5::MipsISA::dspPack
int32_t dspPack(int32_t a, int32_t b, int32_t fmt)
Definition: dsp.cc:1021
gem5::MipsISA::CMP_LE
@ CMP_LE
Definition: dsp.hh:70
gem5::MipsISA::simdUnpack
void simdUnpack(int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign)
Definition: dsp.cc:1139
gem5::MipsISA::FIXED_B_UMAX
const uint64_t FIXED_B_UMAX
Definition: dsp.hh:116
gem5::MipsISA::simdPack
void simdPack(uint64_t *values_ptr, int32_t *reg, int32_t fmt)
Definition: dsp.cc:1127
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::DSP_CCOND
@ DSP_CCOND
Definition: dsp.hh:60
gem5::MipsISA::dspPrecrSra
int32_t dspPrecrSra(int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round)
Definition: dsp.cc:968
gem5::MipsISA::UNSIGNED
@ UNSIGNED
Definition: dsp.hh:84
gem5::MipsISA::DSP_OUFLAG
@ DSP_OUFLAG
Definition: dsp.hh:59
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::MipsISA::dspShll
int32_t dspShll(int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl)
Definition: dsp.cc:277
gem5::MipsISA::FIXED_H_SMIN
const uint64_t FIXED_H_SMIN
Definition: dsp.hh:125
gem5::MipsISA::dspExtr
int32_t dspExtr(int64_t dspac, int32_t fmt, int32_t sa, int32_t round, int32_t saturate, uint32_t *dspctl)
Definition: dsp.cc:1040
gem5::MipsISA::mode
Bitfield< 11, 7 > mode
Definition: dt_constants.hh:98
gem5::MipsISA::dspMulsaq
int64_t dspMulsaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl)
Definition: dsp.cc:741

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