indirect.hh

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/*
 * Copyright (c) 2014 ARM Limited
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/* @file
 * Indirect target predictor interface
 */
 
#ifndef __CPU_PRED_INDIRECT_BASE_HH__
#define __CPU_PRED_INDIRECT_BASE_HH__
 
#include "arch/generic/pcstate.hh"
#include "cpu/inst_seq.hh"
#include "cpu/pred/branch_type.hh"
#include "params/IndirectPredictor.hh"
#include "sim/sim_object.hh"
 
namespace gem5
{
 
namespace branch_prediction
{
 
class IndirectPredictor : public SimObject
{
  public:
 
    typedef IndirectPredictorParams Params;
 
    IndirectPredictor(const Params &params)
        : SimObject(params)
    {
    }
 
    virtual void reset() {};
 
    virtual const PCStateBase* lookup(ThreadID tid, InstSeqNum sn,
                                      Addr pc, void * &i_history) = 0;
 
    virtual void update(ThreadID tid, InstSeqNum sn, Addr pc, bool squash,
                        bool taken, const PCStateBase& target,
                        BranchType br_type, void * &i_history) = 0;
 
    virtual void squash(ThreadID tid, InstSeqNum sn, void * &i_history) = 0;
 
    virtual void commit(ThreadID tid, InstSeqNum sn, void * &i_history) = 0;
};
 
} // namespace branch_prediction
} // namespace gem5
 
#endif // __CPU_PRED_INDIRECT_BASE_HH__