gem5  v21.1.0.2
indirect.hh
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28 
29 #ifndef __CPU_PRED_INDIRECT_BASE_HH__
30 #define __CPU_PRED_INDIRECT_BASE_HH__
31 
32 #include "arch/pcstate.hh"
33 #include "config/the_isa.hh"
34 #include "cpu/inst_seq.hh"
35 #include "params/IndirectPredictor.hh"
36 #include "sim/sim_object.hh"
37 
38 namespace gem5
39 {
40 
41 namespace branch_prediction
42 {
43 
45 {
46  public:
47 
48  typedef IndirectPredictorParams Params;
49 
51  : SimObject(params)
52  {
53  }
54 
55  virtual bool lookup(Addr br_addr, TheISA::PCState& br_target,
56  ThreadID tid) = 0;
57  virtual void recordIndirect(Addr br_addr, Addr tgt_addr,
58  InstSeqNum seq_num, ThreadID tid) = 0;
59  virtual void commit(InstSeqNum seq_num, ThreadID tid,
60  void * indirect_history) = 0;
61  virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
62  virtual void recordTarget(InstSeqNum seq_num, void * indirect_history,
63  const TheISA::PCState& target, ThreadID tid) = 0;
64  virtual void genIndirectInfo(ThreadID tid, void* & indirect_history) = 0;
65  virtual void updateDirectionInfo(ThreadID tid, bool actually_taken) = 0;
66  virtual void deleteIndirectInfo(ThreadID tid, void * indirect_history) = 0;
67  virtual void changeDirectionPrediction(ThreadID tid,
68  void * indirect_history,
69  bool actually_taken) = 0;
70 };
71 
72 } // namespace branch_prediction
73 } // namespace gem5
74 
75 #endif // __CPU_PRED_INDIRECT_BASE_HH__
gem5::branch_prediction::IndirectPredictor::genIndirectInfo
virtual void genIndirectInfo(ThreadID tid, void *&indirect_history)=0
gem5::branch_prediction::IndirectPredictor::lookup
virtual bool lookup(Addr br_addr, TheISA::PCState &br_target, ThreadID tid)=0
gem5::branch_prediction::IndirectPredictor::recordIndirect
virtual void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num, ThreadID tid)=0
gem5::branch_prediction::IndirectPredictor::deleteIndirectInfo
virtual void deleteIndirectInfo(ThreadID tid, void *indirect_history)=0
inst_seq.hh
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::branch_prediction::IndirectPredictor::updateDirectionInfo
virtual void updateDirectionInfo(ThreadID tid, bool actually_taken)=0
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::branch_prediction::IndirectPredictor
Definition: indirect.hh:44
gem5::branch_prediction::IndirectPredictor::commit
virtual void commit(InstSeqNum seq_num, ThreadID tid, void *indirect_history)=0
gem5::branch_prediction::IndirectPredictor::Params
IndirectPredictorParams Params
Definition: indirect.hh:48
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::branch_prediction::IndirectPredictor::squash
virtual void squash(InstSeqNum seq_num, ThreadID tid)=0
gem5::branch_prediction::IndirectPredictor::recordTarget
virtual void recordTarget(InstSeqNum seq_num, void *indirect_history, const TheISA::PCState &target, ThreadID tid)=0
gem5::branch_prediction::IndirectPredictor::changeDirectionPrediction
virtual void changeDirectionPrediction(ThreadID tid, void *indirect_history, bool actually_taken)=0
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::branch_prediction::IndirectPredictor::IndirectPredictor
IndirectPredictor(const Params &params)
Definition: indirect.hh:50
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242

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