gem5 v24.0.0.0
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Miss and writeback queue declarations. More...
#include <cstdint>
#include "arch/generic/tlb.hh"
#include "base/compiler.hh"
#include "base/statistics.hh"
#include "base/types.hh"
#include "mem/cache/cache_probe_arg.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/clocked_object.hh"
#include "sim/probe/probe.hh"
Go to the source code of this file.
Classes | |
class | gem5::prefetch::Base |
class | gem5::prefetch::Base::PrefetchListener |
class | gem5::prefetch::Base::PrefetchEvictListener |
class | gem5::prefetch::Base::PrefetchInfo |
Class containing the information needed by the prefetch to train and generate new prefetch requests. More... | |
struct | gem5::prefetch::Base::StatGroup |
Namespaces | |
namespace | gem5 |
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved. | |
namespace | gem5::prefetch |
Miss and writeback queue declarations.
Definition in file base.hh.