gem5  v21.2.1.1
request.hh
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41 
48 #ifndef __MEM_REQUEST_HH__
49 #define __MEM_REQUEST_HH__
50 
51 #include <algorithm>
52 #include <cassert>
53 #include <cstdint>
54 #include <functional>
55 #include <limits>
56 #include <memory>
57 #include <vector>
58 
59 #include "base/amo.hh"
60 #include "base/compiler.hh"
61 #include "base/flags.hh"
62 #include "base/types.hh"
63 #include "cpu/inst_seq.hh"
64 #include "mem/htm.hh"
65 #include "sim/cur_tick.hh"
66 
67 namespace gem5
68 {
69 
77 GEM5_DEPRECATED_NAMESPACE(ContextSwitchTaskId, context_switch_task_id);
78 namespace context_switch_task_id
79 {
80  enum TaskId
81  {
82  MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
83  Prefetcher = 1022, /* For cache lines brought in by prefetcher */
84  DMA = 1023, /* Mostly Table Walker */
85  Unknown = 1024,
87  };
88 }
89 
90 class Packet;
91 class Request;
93 
94 typedef std::shared_ptr<Request> RequestPtr;
95 typedef uint16_t RequestorID;
96 
97 class Request
98 {
99  public:
100  typedef uint64_t FlagsType;
101  typedef uint8_t ArchFlagsType;
103 
104  enum : FlagsType
105  {
113  ARCH_BITS = 0x000000FF,
115  INST_FETCH = 0x00000100,
117  PHYSICAL = 0x00000200,
125  UNCACHEABLE = 0x00000400,
135  STRICT_ORDER = 0x00000800,
137  PRIVILEGED = 0x00008000,
138 
143  CACHE_BLOCK_ZERO = 0x00010000,
144 
146  NO_ACCESS = 0x00080000,
154  LOCKED_RMW = 0x00100000,
156  LLSC = 0x00200000,
158  MEM_SWAP = 0x00400000,
159  MEM_SWAP_COND = 0x00800000,
161  READ_MODIFY_WRITE = 0x00020000,
162 
164  PREFETCH = 0x01000000,
166  PF_EXCLUSIVE = 0x02000000,
168  EVICT_NEXT = 0x04000000,
170  ACQUIRE = 0x00020000,
172  RELEASE = 0x00040000,
173 
175  ATOMIC_RETURN_OP = 0x40000000,
177  ATOMIC_NO_RETURN_OP = 0x80000000,
178 
183  KERNEL = 0x00001000,
184 
186  SECURE = 0x10000000,
188  PT_WALK = 0x20000000,
189 
191  INVALIDATE = 0x0000000100000000,
193  CLEAN = 0x0000000200000000,
194 
196  DST_POU = 0x0000001000000000,
197 
199  DST_POC = 0x0000002000000000,
200 
202  DST_BITS = 0x0000003000000000,
203 
207  HTM_START = 0x0000010000000000,
208 
210  HTM_COMMIT = 0x0000020000000000,
211 
213  HTM_CANCEL = 0x0000040000000000,
214 
216  HTM_ABORT = 0x0000080000000000,
217 
218  // What is the different between HTM cancel and abort?
219  //
220  // HTM_CANCEL will originate from a user instruction, e.g.
221  // Arm's TCANCEL or x86's XABORT. This is an explicit request
222  // to end a transaction and restore from the last checkpoint.
223  //
224  // HTM_ABORT is an internally generated request used to synchronize
225  // a transaction's failure between the core and memory subsystem.
226  // If a transaction fails in the core, e.g. because an instruction
227  // within the transaction generates an exception, the core will prepare
228  // itself to stop fetching/executing more instructions and send an
229  // HTM_ABORT to the memory subsystem before restoring the checkpoint.
230  // Similarly, the transaction could fail in the memory subsystem and
231  // this will be communicated to the core via the Packet object.
232  // Once the core notices, it will do the same as the above and send
233  // a HTM_ABORT to the memory subsystem.
234  // A HTM_CANCEL sent to the memory subsystem will ultimately return
235  // to the core which in turn will send a HTM_ABORT.
236  //
237  // This separation is necessary to ensure the disjoint components
238  // of the system work correctly together.
239 
245  };
247  CLEAN | INVALIDATE;
248 
251 
254  enum : RequestorID
255  {
269  invldRequestorId = std::numeric_limits<RequestorID>::max()
270  };
273  typedef uint64_t CacheCoherenceFlagsType;
275 
304  {
306  I_CACHE_INV = 0x00000001,
308  V_CACHE_INV = 0x00000002,
309  K_CACHE_INV = 0x00000004,
310  GL1_CACHE_INV = 0x00000008,
311  K_CACHE_WB = 0x00000010,
312  FLUSH_L2 = 0x00000020,
313  GL2_CACHE_INV = 0x00000040,
315  SLC_BIT = 0x00000080,
316  DLC_BIT = 0x00000100,
317  GLC_BIT = 0x00000200,
319  CACHED = 0x00000400,
320  READ_WRITE = 0x00000800,
321  SHARED = 0x00001000,
322 
323  };
324 
325  using LocalAccessor =
326  std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
327 
328  private:
329  typedef uint16_t PrivateFlagsType;
331 
332  enum : PrivateFlagsType
333  {
335  VALID_SIZE = 0x00000001,
337  VALID_PADDR = 0x00000002,
339  VALID_VADDR = 0x00000004,
341  VALID_INST_SEQ_NUM = 0x00000008,
343  VALID_PC = 0x00000010,
345  VALID_CONTEXT_ID = 0x00000020,
347  VALID_EXTRA_DATA = 0x00000080,
349  VALID_STREAM_ID = 0x00000100,
350  VALID_SUBSTREAM_ID = 0x00000200,
351  // hardware transactional memory
353  VALID_HTM_ABORT_CAUSE = 0x00000400,
355  VALID_INST_COUNT = 0x00000800,
361  };
362 
363  private:
364 
370 
376  unsigned _size = 0;
377 
380 
385 
388 
391 
394 
401 
406 
412  uint32_t _streamId = 0;
413 
420  uint32_t _substreamId = 0;
421 
424 
428  uint64_t _extraData = 0;
429 
432 
435 
438 
441 
443 
446 
449 
450  public:
451 
457  Request() {}
458 
464  Request(Addr paddr, unsigned size, Flags flags, RequestorID id) :
465  _paddr(paddr), _size(size), _requestorId(id), _time(curTick())
466  {
467  _flags.set(flags);
469  _byteEnable = std::vector<bool>(size, true);
470  }
471 
472  Request(Addr vaddr, unsigned size, Flags flags,
473  RequestorID id, Addr pc, ContextID cid,
474  AtomicOpFunctorPtr atomic_op=nullptr)
475  {
476  setVirt(vaddr, size, flags, id, pc, std::move(atomic_op));
477  setContext(cid);
478  _byteEnable = std::vector<bool>(size, true);
479  }
480 
481  Request(const Request& other)
482  : _paddr(other._paddr), _size(other._size),
483  _byteEnable(other._byteEnable),
484  _requestorId(other._requestorId),
485  _flags(other._flags),
487  privateFlags(other.privateFlags),
488  _time(other._time),
489  _taskId(other._taskId), _vaddr(other._vaddr),
491  _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
494  accessDelta(other.accessDelta), depth(other.depth)
495  {
496  atomicOpFunctor.reset(other.atomicOpFunctor ?
497  other.atomicOpFunctor->clone() : nullptr);
498  }
499 
500  ~Request() {}
501 
505  void
506  setContext(ContextID context_id)
507  {
508  _contextId = context_id;
510  }
511 
512  void
513  setStreamId(uint32_t sid)
514  {
515  _streamId = sid;
517  }
518 
519  void
520  setSubstreamId(uint32_t ssid)
521  {
522  assert(hasStreamId());
523  _substreamId = ssid;
525  }
526 
531  void
532  setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc,
533  AtomicOpFunctorPtr amo_op=nullptr)
534  {
535  _vaddr = vaddr;
536  _size = size;
537  _requestorId = id;
538  _pc = pc;
539  _time = curTick();
540 
542  _flags.set(flags);
545  depth = 0;
546  accessDelta = 0;
547  translateDelta = 0;
548  atomicOpFunctor = std::move(amo_op);
549  _localAccessor = nullptr;
550  }
551 
556  void
557  setPaddr(Addr paddr)
558  {
559  _paddr = paddr;
561  }
562 
567  // TODO: this function is still required by TimingSimpleCPU - should be
568  // removed once TimingSimpleCPU will support arbitrarily long multi-line
569  // mem. accesses
570  void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
571  {
572  assert(hasVaddr());
573  assert(!hasPaddr());
574  assert(split_addr > _vaddr && split_addr < _vaddr + _size);
575  req1 = std::make_shared<Request>(*this);
576  req2 = std::make_shared<Request>(*this);
577  req1->_size = split_addr - _vaddr;
578  req2->_vaddr = split_addr;
579  req2->_size = _size - req1->_size;
580  req1->_byteEnable = std::vector<bool>(
581  _byteEnable.begin(),
582  _byteEnable.begin() + req1->_size);
583  req2->_byteEnable = std::vector<bool>(
584  _byteEnable.begin() + req1->_size,
585  _byteEnable.end());
586  }
587 
591  bool
592  hasPaddr() const
593  {
595  }
596 
597  Addr
598  getPaddr() const
599  {
600  assert(hasPaddr());
601  return _paddr;
602  }
603 
607  bool
608  hasInstCount() const
609  {
611  }
612 
614  {
615  assert(hasInstCount());
616  return _instCount;
617  }
618 
620  {
622  _instCount = val;
623  }
624 
629 
635 
640  mutable int depth = 0;
641 
645  bool
646  hasSize() const
647  {
648  return privateFlags.isSet(VALID_SIZE);
649  }
650 
651  unsigned
652  getSize() const
653  {
654  assert(hasSize());
655  return _size;
656  }
657 
658  const std::vector<bool>&
660  {
661  return _byteEnable;
662  }
663 
664  void
666  {
667  assert(be.size() == _size);
668  _byteEnable = be;
669  }
670 
676  bool
677  isMasked() const
678  {
679  return std::find(
680  _byteEnable.begin(),
681  _byteEnable.end(),
682  false) != _byteEnable.end();
683  }
684 
686  Tick
687  time() const
688  {
689  assert(hasPaddr() || hasVaddr());
690  return _time;
691  }
692 
694  bool isLocalAccess() { return (bool)_localAccessor; }
698  Cycles
700  {
701  return _localAccessor(tc, pkt);
702  }
703 
707  bool
709  {
710  return (bool)atomicOpFunctor;
711  }
712 
715  {
716  assert(atomicOpFunctor);
717  return atomicOpFunctor.get();
718  }
719 
723  bool
725  {
727  }
728 
731  {
732  assert(hasHtmAbortCause());
733  return _htmAbortCause;
734  }
735 
736  void
738  {
739  assert(isHTMAbort());
742  }
743 
745  Flags
747  {
748  assert(hasPaddr() || hasVaddr());
749  return _flags;
750  }
751 
756  void
758  {
759  assert(hasPaddr() || hasVaddr());
760  _flags.set(flags);
761  }
762 
763  void
765  {
766  // TODO: do mem_sync_op requests have valid paddr/vaddr?
767  assert(hasPaddr() || hasVaddr());
768  _cacheCoherenceFlags.set(extraFlags);
769  }
770 
772  bool
773  hasVaddr() const
774  {
776  }
777 
778  Addr
779  getVaddr() const
780  {
781  assert(privateFlags.isSet(VALID_VADDR));
782  return _vaddr;
783  }
784 
787  requestorId() const
788  {
789  return _requestorId;
790  }
791 
792  uint32_t
793  taskId() const
794  {
795  return _taskId;
796  }
797 
798  void
799  taskId(uint32_t id) {
800  _taskId = id;
801  }
802 
805  getArchFlags() const
806  {
807  assert(hasPaddr() || hasVaddr());
808  return _flags & ARCH_BITS;
809  }
810 
812  bool
814  {
816  }
817 
819  uint64_t
820  getExtraData() const
821  {
822  assert(extraDataValid());
823  return _extraData;
824  }
825 
827  void
828  setExtraData(uint64_t extraData)
829  {
830  _extraData = extraData;
832  }
833 
834  bool
835  hasContextId() const
836  {
838  }
839 
841  ContextID
842  contextId() const
843  {
844  assert(hasContextId());
845  return _contextId;
846  }
847 
848  bool
849  hasStreamId() const
850  {
852  }
853 
854  uint32_t
855  streamId() const
856  {
857  assert(hasStreamId());
858  return _streamId;
859  }
860 
861  bool
863  {
865  }
866 
867  uint32_t
868  substreamId() const
869  {
870  assert(hasSubstreamId());
871  return _substreamId;
872  }
873 
874  void
876  {
878  _pc = pc;
879  }
880 
881  bool
882  hasPC() const
883  {
884  return privateFlags.isSet(VALID_PC);
885  }
886 
888  Addr
889  getPC() const
890  {
891  assert(hasPC());
892  return _pc;
893  }
894 
899  void incAccessDepth() const { depth++; }
900  int getAccessDepth() const { return depth; }
901 
907 
913  Tick getAccessLatency() const { return accessDelta; }
914 
919  bool
921  {
923  }
924 
925  InstSeqNum
927  {
928  assert(hasInstSeqNum());
929  return _reqInstSeqNum;
930  }
931 
932  void
934  {
936  _reqInstSeqNum = seq_num;
937  }
938 
941  bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
942  bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
943  bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
944  bool
945  isPrefetch() const
946  {
947  return (_flags.isSet(PREFETCH | PF_EXCLUSIVE));
948  }
949  bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
950  bool isLLSC() const { return _flags.isSet(LLSC); }
951  bool isPriv() const { return _flags.isSet(PRIVILEGED); }
952  bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
953  bool isSwap() const { return _flags.isSet(MEM_SWAP | MEM_SWAP_COND); }
954  bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
955  bool
957  {
959  }
960  bool isSecure() const { return _flags.isSet(SECURE); }
961  bool isPTWalk() const { return _flags.isSet(PT_WALK); }
962  bool isRelease() const { return _flags.isSet(RELEASE); }
963  bool isKernel() const { return _flags.isSet(KERNEL); }
964  bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
966  // hardware transactional memory
967  bool isHTMStart() const { return _flags.isSet(HTM_START); }
968  bool isHTMCommit() const { return _flags.isSet(HTM_COMMIT); }
969  bool isHTMCancel() const { return _flags.isSet(HTM_CANCEL); }
970  bool isHTMAbort() const { return _flags.isSet(HTM_ABORT); }
971  bool
972  isHTMCmd() const
973  {
974  return (isHTMStart() || isHTMCommit() ||
975  isHTMCancel() || isHTMAbort());
976  }
977 
978  bool
979  isAtomic() const
980  {
981  return _flags.isSet(ATOMIC_RETURN_OP) ||
983  }
984 
992  bool isToPOU() const { return _flags.isSet(DST_POU); }
993  bool isToPOC() const { return _flags.isSet(DST_POC); }
994  Flags getDest() const { return _flags & DST_BITS; }
995 
996  bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
997 
1003  bool isInvL1() const { return _cacheCoherenceFlags.isSet(INV_L1); }
1004 
1005  bool
1007  {
1009  }
1010 
1023  bool isCacheClean() const { return _flags.isSet(CLEAN); }
1024  bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
1025  bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
1027 };
1028 
1029 } // namespace gem5
1030 
1031 #endif // __MEM_REQUEST_HH__
gem5::Request::getReqInstSeqNum
InstSeqNum getReqInstSeqNum() const
Definition: request.hh:926
gem5::Request::hasStreamId
bool hasStreamId() const
Definition: request.hh:849
gem5::Request::hasHtmAbortCause
bool hasHtmAbortCause() const
Accessor for hardware transactional memory abort cause.
Definition: request.hh:724
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Request::_instCount
Counter _instCount
The instruction count at the time this request is created.
Definition: request.hh:445
gem5::Request::_flags
Flags _flags
Flag structure for the request.
Definition: request.hh:387
gem5::Request::HTM_ABORT
@ HTM_ABORT
The request aborts a HTM transaction.
Definition: request.hh:216
gem5::Request::isAtomicNoReturn
bool isAtomicNoReturn() const
Definition: request.hh:965
gem5::Request::setLocalAccessor
void setLocalAccessor(LocalAccessor acc)
Set the function which will enact that access.
Definition: request.hh:696
gem5::Request::_size
unsigned _size
The size of the request.
Definition: request.hh:376
gem5::Request::VALID_EXTRA_DATA
@ VALID_EXTRA_DATA
Whether or not the sc result is valid.
Definition: request.hh:347
gem5::Request::VALID_CONTEXT_ID
@ VALID_CONTEXT_ID
Whether or not the context ID is valid.
Definition: request.hh:345
gem5::Request::Request
Request()
Minimal constructor.
Definition: request.hh:457
gem5::Request::K_CACHE_INV
@ K_CACHE_INV
Definition: request.hh:309
gem5::Request::getArchFlags
ArchFlagsType getArchFlags() const
Accessor function for architecture-specific flags.
Definition: request.hh:805
gem5::Request::setAccessLatency
void setAccessLatency()
Set/Get the time taken to complete this request's access, not including the time to successfully tran...
Definition: request.hh:912
gem5::Request::PrivateFlags
gem5::Flags< PrivateFlagsType > PrivateFlags
Definition: request.hh:330
gem5::Request::_localAccessor
LocalAccessor _localAccessor
Definition: request.hh:442
gem5::Request::_requestorId
RequestorID _requestorId
The requestor ID which is unique in the system for all ports that are capable of issuing a transactio...
Definition: request.hh:384
gem5::Request::hasAtomicOpFunctor
bool hasAtomicOpFunctor()
Accessor for atomic-op functor.
Definition: request.hh:708
gem5::Request::isStrictlyOrdered
bool isStrictlyOrdered() const
Definition: request.hh:942
gem5::Request::I_CACHE_INV
@ I_CACHE_INV
mem_sync_op flags
Definition: request.hh:306
gem5::Request::VALID_PADDR
@ VALID_PADDR
Whether or not paddr is valid (has been written yet).
Definition: request.hh:337
gem5::Request::isPrefetch
bool isPrefetch() const
Definition: request.hh:945
gem5::Request::VALID_VADDR
@ VALID_VADDR
Whether or not the vaddr is valid.
Definition: request.hh:339
gem5::Request::GLC_BIT
@ GLC_BIT
Definition: request.hh:317
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::Request::getAccessLatency
Tick getAccessLatency() const
Definition: request.hh:913
gem5::Request::isPTWalk
bool isPTWalk() const
Definition: request.hh:961
gem5::Request::isPrefetchEx
bool isPrefetchEx() const
Definition: request.hh:949
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::Request::SLC_BIT
@ SLC_BIT
user-policy flags
Definition: request.hh:315
gem5::RiscvISA::Unknown
Static instruction class for unknown (illegal) instructions.
Definition: unknown.hh:53
gem5::Request::isUncacheable
bool isUncacheable() const
Accessor functions for flags.
Definition: request.hh:941
gem5::Request::STICKY_FLAGS
@ STICKY_FLAGS
These flags are not cleared when a Request object is reused (assigned a new address).
Definition: request.hh:244
gem5::AtomicOpFunctor
Definition: amo.hh:43
amo.hh
gem5::Request::LocalAccessor
std::function< Cycles(ThreadContext *tc, Packet *pkt)> LocalAccessor
Definition: request.hh:326
gem5::Request::GL1_CACHE_INV
@ GL1_CACHE_INV
Definition: request.hh:310
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::Request::isSecure
bool isSecure() const
Definition: request.hh:960
gem5::Request::getSize
unsigned getSize() const
Definition: request.hh:652
gem5::Request::splitOnVaddr
void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
Generate two requests as if this request had been split into two pieces.
Definition: request.hh:570
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:247
gem5::Request::DST_POU
@ DST_POU
The request targets the point of unification.
Definition: request.hh:196
gem5::Flags::clear
void clear()
Clear all flag's bits.
Definition: flags.hh:102
gem5::Request::_extraData
uint64_t _extraData
Extra data for the request, such as the return value of store conditional or the compare value for a ...
Definition: request.hh:428
gem5::Request::streamId
uint32_t streamId() const
Definition: request.hh:855
cur_tick.hh
gem5::Request::getInstCount
Counter getInstCount() const
Definition: request.hh:613
gem5::Request::Request
Request(const Request &other)
Definition: request.hh:481
htm.hh
gem5::Request::SECURE
@ SECURE
The request targets the secure memory space.
Definition: request.hh:186
gem5::Request::isRelease
bool isRelease() const
Definition: request.hh:962
gem5::Request::setReqInstSeqNum
void setReqInstSeqNum(const InstSeqNum seq_num)
Definition: request.hh:933
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::Request::HTM_CMD
static const FlagsType HTM_CMD
Definition: request.hh:249
gem5::Request::~Request
~Request()
Definition: request.hh:500
gem5::Request::getHtmAbortCause
HtmFailureFaultCause getHtmAbortCause() const
Definition: request.hh:730
gem5::Request::isInvL1
bool isInvL1() const
Accessor functions for the memory space configuration flags and used by GPU ISAs such as the Heteroge...
Definition: request.hh:1003
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::Request::_paddr
Addr _paddr
The physical address of the request.
Definition: request.hh:369
gem5::Request::READ_WRITE
@ READ_WRITE
Definition: request.hh:320
std::vector< bool >
gem5::Request::isPriv
bool isPriv() const
Definition: request.hh:951
gem5::Request::getDest
Flags getDest() const
Definition: request.hh:994
gem5::Request::DLC_BIT
@ DLC_BIT
Definition: request.hh:316
gem5::Request::hasInstSeqNum
bool hasInstSeqNum() const
Accessor for the sequence number of instruction that creates the request.
Definition: request.hh:920
gem5::Request::FlagsType
uint64_t FlagsType
Definition: request.hh:100
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:262
gem5::Request::setPC
void setPC(Addr pc)
Definition: request.hh:875
gem5::Request::getPaddr
Addr getPaddr() const
Definition: request.hh:598
gem5::Request::Request
Request(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc, ContextID cid, AtomicOpFunctorPtr atomic_op=nullptr)
Definition: request.hh:472
gem5::Request::HTM_CANCEL
@ HTM_CANCEL
The request cancels a HTM transaction.
Definition: request.hh:213
gem5::Request::hasVaddr
bool hasVaddr() const
Accessor function for vaddr.
Definition: request.hh:773
gem5::Request::VALID_PC
@ VALID_PC
Whether or not the pc is valid.
Definition: request.hh:343
gem5::Request::isReadModifyWrite
bool isReadModifyWrite() const
Definition: request.hh:956
gem5::Request::isAtomic
bool isAtomic() const
Definition: request.hh:979
gem5::Request::setStreamId
void setStreamId(uint32_t sid)
Definition: request.hh:513
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Request::VALID_INST_SEQ_NUM
@ VALID_INST_SEQ_NUM
Whether or not the instruction sequence number is valid.
Definition: request.hh:341
gem5::Request::RELEASE
@ RELEASE
The request should be marked with RELEASE.
Definition: request.hh:172
gem5::Request::MEM_SWAP
@ MEM_SWAP
This request is for a memory swap.
Definition: request.hh:158
gem5::Request::_taskId
uint32_t _taskId
The task id associated with this request.
Definition: request.hh:405
gem5::Request::PT_WALK
@ PT_WALK
The request is a page table walk.
Definition: request.hh:188
gem5::Request::isHTMAbort
bool isHTMAbort() const
Definition: request.hh:970
gem5::Request::Flags
gem5::Flags< FlagsType > Flags
Definition: request.hh:102
gem5::Request::getExtraData
uint64_t getExtraData() const
Accessor function for store conditional return value.
Definition: request.hh:820
gem5::Request::taskId
uint32_t taskId() const
Definition: request.hh:793
gem5::Request::PF_EXCLUSIVE
@ PF_EXCLUSIVE
The request should be prefetched into the exclusive state.
Definition: request.hh:166
gem5::Flags< FlagsType >
gem5::Request::_pc
Addr _pc
program counter of initiating access; for tracing/debugging
Definition: request.hh:434
gem5::Request::HTM_START
@ HTM_START
hardware transactional memory
Definition: request.hh:207
gem5::context_switch_task_id::TaskId
TaskId
Definition: request.hh:80
gem5::Request::privateFlags
PrivateFlags privateFlags
Private flags for field validity checking.
Definition: request.hh:393
gem5::Request::setHtmAbortCause
void setHtmAbortCause(HtmFailureFaultCause val)
Definition: request.hh:737
inst_seq.hh
gem5::Request::getFlags
Flags getFlags()
Accessor for flags.
Definition: request.hh:746
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Request::GL2_CACHE_INV
@ GL2_CACHE_INV
Definition: request.hh:313
gem5::Request::CACHED
@ CACHED
mtype flags
Definition: request.hh:319
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::Request::hasSize
bool hasSize() const
Accessor for size.
Definition: request.hh:646
gem5::Request::isHTMStart
bool isHTMStart() const
Definition: request.hh:967
gem5::Request::LOCKED_RMW
@ LOCKED_RMW
This request will lock or unlock the accessed memory.
Definition: request.hh:154
gem5::MaxAddr
const Addr MaxAddr
Definition: types.hh:171
gem5::Request::ATOMIC_NO_RETURN_OP
@ ATOMIC_NO_RETURN_OP
The request is an atomic that does not return data.
Definition: request.hh:177
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Request::isSwap
bool isSwap() const
Definition: request.hh:953
gem5::Request::MEM_SWAP_COND
@ MEM_SWAP_COND
Definition: request.hh:159
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Request::PREFETCH
@ PREFETCH
The request is a prefetch.
Definition: request.hh:164
gem5::Request::substreamId
uint32_t substreamId() const
Definition: request.hh:868
gem5::Request::setPaddr
void setPaddr(Addr paddr)
Set just the physical address.
Definition: request.hh:557
gem5::Request::SHARED
@ SHARED
Definition: request.hh:321
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::Request::STICKY_PRIVATE_FLAGS
@ STICKY_PRIVATE_FLAGS
These flags are not cleared when a Request object is reused (assigned a new address).
Definition: request.hh:360
gem5::Request::_time
Tick _time
The time this request was started.
Definition: request.hh:400
gem5::Request::CacheCoherenceFlagsType
uint64_t CacheCoherenceFlagsType
Definition: request.hh:273
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:264
gem5::Request::_cacheCoherenceFlags
CacheCoherenceFlags _cacheCoherenceFlags
Flags that control how downstream cache system maintains coherence.
Definition: request.hh:390
gem5::Request::isAcquire
bool isAcquire() const
Definition: request.hh:996
gem5::context_switch_task_id::NumTaskId
@ NumTaskId
Definition: request.hh:86
gem5::MipsISA::be
Bitfield< 15 > be
Definition: pra_constants.hh:223
gem5::Request::wbRequestorId
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
Definition: request.hh:257
gem5::Request::PRIVILEGED
@ PRIVILEGED
This request is made in privileged mode.
Definition: request.hh:137
gem5::Request::ATOMIC_RETURN_OP
@ ATOMIC_RETURN_OP
The request is an atomic that returns data.
Definition: request.hh:175
gem5::Request::setExtraData
void setExtraData(uint64_t extraData)
Accessor function for store conditional return value.
Definition: request.hh:828
gem5::Request::isAtomicReturn
bool isAtomicReturn() const
Definition: request.hh:964
gem5::Request::getAccessDepth
int getAccessDepth() const
Definition: request.hh:900
gem5::Request::VALID_STREAM_ID
@ VALID_STREAM_ID
Whether or not the stream ID and substream ID is valid.
Definition: request.hh:349
gem5::Request::isCacheMaintenance
bool isCacheMaintenance() const
Definition: request.hh:1025
gem5::Request::isInstFetch
bool isInstFetch() const
Definition: request.hh:943
gem5::Request::isLLSC
bool isLLSC() const
Definition: request.hh:950
gem5::HtmFailureFaultCause::INVALID
@ INVALID
compiler.hh
gem5::Request::hasSubstreamId
bool hasSubstreamId() const
Definition: request.hh:862
gem5::Request::hasPaddr
bool hasPaddr() const
Accessor for paddr.
Definition: request.hh:592
gem5::Request::setSubstreamId
void setSubstreamId(uint32_t ssid)
Definition: request.hh:520
gem5::Request::setContext
void setContext(ContextID context_id)
Set up Context numbers.
Definition: request.hh:506
gem5::Request::DST_BITS
@ DST_BITS
Bits to define the destination of a request.
Definition: request.hh:202
gem5::Request::_substreamId
uint32_t _substreamId
The substream ID identifies an "execution context" within a device behind an SMMU/IOMMU.
Definition: request.hh:420
gem5::Request::isGL2CacheFlush
bool isGL2CacheFlush() const
Definition: request.hh:1006
gem5::Request::isHTMCmd
bool isHTMCmd() const
Definition: request.hh:972
gem5::Request::isCacheInvalidate
bool isCacheInvalidate() const
Definition: request.hh:1024
gem5::Request::_htmAbortCause
HtmFailureFaultCause _htmAbortCause
The cause for HTM transaction abort.
Definition: request.hh:448
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Request::isKernel
bool isKernel() const
Definition: request.hh:963
gem5::Request::setFlags
void setFlags(Flags flags)
Note that unlike other accessors, this function sets specific flags (ORs them in); it does not assign...
Definition: request.hh:757
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::Request::getByteEnable
const std::vector< bool > & getByteEnable() const
Definition: request.hh:659
gem5::Request::CacheCoherenceFlags
gem5::Flags< CacheCoherenceFlagsType > CacheCoherenceFlags
Definition: request.hh:274
gem5::Request::requestorId
RequestorID requestorId() const
Accesssor for the requestor id.
Definition: request.hh:787
gem5::context_switch_task_id::DMA
@ DMA
Definition: request.hh:84
gem5::Request::VALID_HTM_ABORT_CAUSE
@ VALID_HTM_ABORT_CAUSE
Whether or not the abort cause is valid.
Definition: request.hh:353
gem5::Request::CACHE_BLOCK_ZERO
@ CACHE_BLOCK_ZERO
This is a write that is targeted and zeroing an entire cache block.
Definition: request.hh:143
flags.hh
gem5::Request::PrivateFlagsType
uint16_t PrivateFlagsType
Definition: request.hh:329
gem5::Request::_reqInstSeqNum
InstSeqNum _reqInstSeqNum
Sequence number of the instruction that creates the request.
Definition: request.hh:437
gem5::Request::localAccessor
Cycles localAccessor(ThreadContext *tc, Packet *pkt)
Perform the installed local access.
Definition: request.hh:699
gem5::Request::isHTMCancel
bool isHTMCancel() const
Definition: request.hh:969
gem5::Request::isLockedRMW
bool isLockedRMW() const
Definition: request.hh:952
gem5::Request::setVirt
void setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc, AtomicOpFunctorPtr amo_op=nullptr)
Set up a virtual (e.g., CPU) request in a previously allocated Request object.
Definition: request.hh:532
gem5::Request::READ_MODIFY_WRITE
@ READ_MODIFY_WRITE
This request is a read which will be followed by a write.
Definition: request.hh:161
gem5::Request::STORE_NO_DATA
static const FlagsType STORE_NO_DATA
Definition: request.hh:246
gem5::Request::HTM_COMMIT
@ HTM_COMMIT
The request commits a HTM transaction.
Definition: request.hh:210
gem5::Request::LLSC
@ LLSC
The request is a Load locked/store conditional.
Definition: request.hh:156
gem5::Request::ArchFlagsType
uint8_t ArchFlagsType
Definition: request.hh:101
gem5::context_switch_task_id::Unknown
@ Unknown
Definition: request.hh:85
gem5::Request::atomicOpFunctor
AtomicOpFunctorPtr atomicOpFunctor
A pointer to an atomic operation.
Definition: request.hh:440
gem5::Request::VALID_SUBSTREAM_ID
@ VALID_SUBSTREAM_ID
Definition: request.hh:350
gem5::Request::contextId
ContextID contextId() const
Accessor function for context ID.
Definition: request.hh:842
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::context_switch_task_id::MaxNormalTaskId
@ MaxNormalTaskId
Definition: request.hh:82
gem5::Request::setByteEnable
void setByteEnable(const std::vector< bool > &be)
Definition: request.hh:665
gem5::Request::hasContextId
bool hasContextId() const
Definition: request.hh:835
gem5::Request::hasInstCount
bool hasInstCount() const
Accessor for instruction count.
Definition: request.hh:608
types.hh
gem5::Request
Definition: request.hh:97
gem5::Request::VALID_INST_COUNT
@ VALID_INST_COUNT
Whether or not the instruction count is valid.
Definition: request.hh:355
gem5::Request::setTranslateLatency
void setTranslateLatency()
Set/Get the time taken for this request to be successfully translated.
Definition: request.hh:905
gem5::Request::_streamId
uint32_t _streamId
The stream ID uniquely identifies a device behind the SMMU/IOMMU Each transaction arriving at the SMM...
Definition: request.hh:412
gem5::Request::DST_POC
@ DST_POC
The request targets the point of coherence.
Definition: request.hh:199
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
gem5::Request::isCacheClean
bool isCacheClean() const
Accessor functions to determine whether this request is part of a cache maintenance operation.
Definition: request.hh:1023
gem5::Request::INV_L1
@ INV_L1
Definition: request.hh:307
gem5::Request::V_CACHE_INV
@ V_CACHE_INV
Definition: request.hh:308
gem5::Request::getAtomicOpFunctor
AtomicOpFunctor * getAtomicOpFunctor()
Definition: request.hh:714
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::Request::taskId
void taskId(uint32_t id)
Definition: request.hh:799
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::Request::VALID_SIZE
@ VALID_SIZE
Whether or not the size is valid.
Definition: request.hh:335
gem5::Request::hasPC
bool hasPC() const
Definition: request.hh:882
gem5::Request::ARCH_BITS
@ ARCH_BITS
Architecture specific flags.
Definition: request.hh:113
gem5::Request::time
Tick time() const
Accessor for time.
Definition: request.hh:687
gem5::Request::_byteEnable
std::vector< bool > _byteEnable
Byte-enable mask for writes.
Definition: request.hh:379
gem5::Request::_contextId
ContextID _contextId
The context ID (for statistics, locks, and wakeups).
Definition: request.hh:431
gem5::Request::invldRequestorId
@ invldRequestorId
Invalid requestor id for assertion checking only.
Definition: request.hh:269
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::Request::_vaddr
Addr _vaddr
The virtual address of the request.
Definition: request.hh:423
gem5::Request::getVaddr
Addr getVaddr() const
Definition: request.hh:779
gem5::Request::incAccessDepth
void incAccessDepth() const
Increment/Get the depth at which this request is responded to.
Definition: request.hh:899
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::Request::getTranslateLatency
Tick getTranslateLatency() const
Definition: request.hh:906
gem5::Request::K_CACHE_WB
@ K_CACHE_WB
Definition: request.hh:311
gem5::Request::isCondSwap
bool isCondSwap() const
Definition: request.hh:954
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::Request::INVALIDATE
@ INVALIDATE
The request invalidates a memory location.
Definition: request.hh:191
gem5::Request::isMasked
bool isMasked() const
Returns true if the memory request is masked, which means there is at least one byteEnable element wh...
Definition: request.hh:677
gem5::Request::translateDelta
Tick translateDelta
Time for the TLB/table walker to successfully translate this request.
Definition: request.hh:628
gem5::Request::EVICT_NEXT
@ EVICT_NEXT
The request should be marked as LRU.
Definition: request.hh:168
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::Request::isToPOC
bool isToPOC() const
Definition: request.hh:993
gem5::Request::FLUSH_L2
@ FLUSH_L2
Definition: request.hh:312
gem5::Request::ACQUIRE
@ ACQUIRE
The request should be marked with ACQUIRE.
Definition: request.hh:170
gem5::Request::Request
Request(Addr paddr, unsigned size, Flags flags, RequestorID id)
Constructor for physical (e.g.
Definition: request.hh:464
gem5::Request::isLocalAccess
bool isLocalAccess()
Is this request for a local memory mapped resource/register?
Definition: request.hh:694
gem5::Request::isToPOU
bool isToPOU() const
Accessor functions for the destination of a memory request.
Definition: request.hh:992
gem5::Request::setInstCount
void setInstCount(Counter val)
Definition: request.hh:619
gem5::Request::depth
int depth
Level of the cache hierachy where this request was responded to (e.g.
Definition: request.hh:640
gem5::Request::extraDataValid
bool extraDataValid() const
Accessor function to check if sc result is valid.
Definition: request.hh:813
gem5::Request::getPC
Addr getPC() const
Accessor function for pc.
Definition: request.hh:889
gem5::Request::KERNEL
@ KERNEL
The request should be marked with KERNEL.
Definition: request.hh:183
gem5::Request::CLEAN
@ CLEAN
The request cleans a memory location.
Definition: request.hh:193
gem5::Request::isHTMCommit
bool isHTMCommit() const
Definition: request.hh:968
gem5::Request::accessDelta
Tick accessDelta
Access latency to complete this memory transaction not including translation time.
Definition: request.hh:634
gem5::Request::setCacheCoherenceFlags
void setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
Definition: request.hh:764
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117

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