gem5  v21.1.0.2
request.hh
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41 
48 #ifndef __MEM_REQUEST_HH__
49 #define __MEM_REQUEST_HH__
50 
51 #include <algorithm>
52 #include <cassert>
53 #include <cstdint>
54 #include <functional>
55 #include <limits>
56 #include <memory>
57 #include <vector>
58 
59 #include "base/amo.hh"
60 #include "base/compiler.hh"
61 #include "base/flags.hh"
62 #include "base/types.hh"
63 #include "cpu/inst_seq.hh"
64 #include "mem/htm.hh"
65 #include "sim/cur_tick.hh"
66 
67 namespace gem5
68 {
69 
77 GEM5_DEPRECATED_NAMESPACE(ContextSwitchTaskId, context_switch_task_id);
78 namespace context_switch_task_id
79 {
80  enum TaskId
81  {
82  MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
83  Prefetcher = 1022, /* For cache lines brought in by prefetcher */
84  DMA = 1023, /* Mostly Table Walker */
85  Unknown = 1024,
87  };
88 }
89 
90 class Packet;
91 class Request;
93 
94 typedef std::shared_ptr<Request> RequestPtr;
95 typedef uint16_t RequestorID;
96 
97 class Request
98 {
99  public:
100  typedef uint64_t FlagsType;
101  typedef uint8_t ArchFlagsType;
103 
104  enum : FlagsType
105  {
113  ARCH_BITS = 0x000000FF,
115  INST_FETCH = 0x00000100,
117  PHYSICAL = 0x00000200,
125  UNCACHEABLE = 0x00000400,
135  STRICT_ORDER = 0x00000800,
137  PRIVILEGED = 0x00008000,
138 
143  CACHE_BLOCK_ZERO = 0x00010000,
144 
146  NO_ACCESS = 0x00080000,
154  LOCKED_RMW = 0x00100000,
156  LLSC = 0x00200000,
158  MEM_SWAP = 0x00400000,
159  MEM_SWAP_COND = 0x00800000,
160 
162  PREFETCH = 0x01000000,
164  PF_EXCLUSIVE = 0x02000000,
166  EVICT_NEXT = 0x04000000,
168  ACQUIRE = 0x00020000,
170  RELEASE = 0x00040000,
171 
173  ATOMIC_RETURN_OP = 0x40000000,
175  ATOMIC_NO_RETURN_OP = 0x80000000,
176 
181  KERNEL = 0x00001000,
182 
184  SECURE = 0x10000000,
186  PT_WALK = 0x20000000,
187 
189  INVALIDATE = 0x0000000100000000,
191  CLEAN = 0x0000000200000000,
192 
194  DST_POU = 0x0000001000000000,
195 
197  DST_POC = 0x0000002000000000,
198 
200  DST_BITS = 0x0000003000000000,
201 
205  HTM_START = 0x0000010000000000,
206 
208  HTM_COMMIT = 0x0000020000000000,
209 
211  HTM_CANCEL = 0x0000040000000000,
212 
214  HTM_ABORT = 0x0000080000000000,
215 
216  // What is the different between HTM cancel and abort?
217  //
218  // HTM_CANCEL will originate from a user instruction, e.g.
219  // Arm's TCANCEL or x86's XABORT. This is an explicit request
220  // to end a transaction and restore from the last checkpoint.
221  //
222  // HTM_ABORT is an internally generated request used to synchronize
223  // a transaction's failure between the core and memory subsystem.
224  // If a transaction fails in the core, e.g. because an instruction
225  // within the transaction generates an exception, the core will prepare
226  // itself to stop fetching/executing more instructions and send an
227  // HTM_ABORT to the memory subsystem before restoring the checkpoint.
228  // Similarly, the transaction could fail in the memory subsystem and
229  // this will be communicated to the core via the Packet object.
230  // Once the core notices, it will do the same as the above and send
231  // a HTM_ABORT to the memory subsystem.
232  // A HTM_CANCEL sent to the memory subsystem will ultimately return
233  // to the core which in turn will send a HTM_ABORT.
234  //
235  // This separation is necessary to ensure the disjoint components
236  // of the system work correctly together.
237 
243  };
245  CLEAN | INVALIDATE;
246 
249 
252  enum : RequestorID
253  {
267  invldRequestorId = std::numeric_limits<RequestorID>::max()
268  };
271  typedef uint64_t CacheCoherenceFlagsType;
273 
302  {
304  I_CACHE_INV = 0x00000001,
306  V_CACHE_INV = 0x00000002,
307  K_CACHE_INV = 0x00000004,
308  GL1_CACHE_INV = 0x00000008,
309  K_CACHE_WB = 0x00000010,
310  FLUSH_L2 = 0x00000020,
311  GL2_CACHE_INV = 0x00000040,
313  SLC_BIT = 0x00000080,
314  DLC_BIT = 0x00000100,
315  GLC_BIT = 0x00000200,
317  CACHED = 0x00000400,
318  READ_WRITE = 0x00000800,
319  SHARED = 0x00001000,
320 
321  };
322 
323  using LocalAccessor =
324  std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
325 
326  private:
327  typedef uint16_t PrivateFlagsType;
329 
330  enum : PrivateFlagsType
331  {
333  VALID_SIZE = 0x00000001,
335  VALID_PADDR = 0x00000002,
337  VALID_VADDR = 0x00000004,
339  VALID_INST_SEQ_NUM = 0x00000008,
341  VALID_PC = 0x00000010,
343  VALID_CONTEXT_ID = 0x00000020,
345  VALID_EXTRA_DATA = 0x00000080,
347  VALID_STREAM_ID = 0x00000100,
348  VALID_SUBSTREAM_ID = 0x00000200,
349  // hardware transactional memory
351  VALID_HTM_ABORT_CAUSE = 0x00000400,
353  VALID_INST_COUNT = 0x00000800,
359  };
360 
361  private:
362 
368 
374  unsigned _size = 0;
375 
378 
383 
386 
389 
392 
399 
404 
410  uint32_t _streamId = 0;
411 
418  uint32_t _substreamId = 0;
419 
422 
426  uint64_t _extraData = 0;
427 
430 
433 
436 
439 
441 
444 
447 
448  public:
449 
455  Request() {}
456 
462  Request(Addr paddr, unsigned size, Flags flags, RequestorID id) :
463  _paddr(paddr), _size(size), _requestorId(id), _time(curTick())
464  {
465  _flags.set(flags);
467  _byteEnable = std::vector<bool>(size, true);
468  }
469 
470  Request(Addr vaddr, unsigned size, Flags flags,
471  RequestorID id, Addr pc, ContextID cid,
472  AtomicOpFunctorPtr atomic_op=nullptr)
473  {
474  setVirt(vaddr, size, flags, id, pc, std::move(atomic_op));
475  setContext(cid);
476  _byteEnable = std::vector<bool>(size, true);
477  }
478 
479  Request(const Request& other)
480  : _paddr(other._paddr), _size(other._size),
481  _byteEnable(other._byteEnable),
482  _requestorId(other._requestorId),
483  _flags(other._flags),
485  privateFlags(other.privateFlags),
486  _time(other._time),
487  _taskId(other._taskId), _vaddr(other._vaddr),
489  _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
492  accessDelta(other.accessDelta), depth(other.depth)
493  {
494  atomicOpFunctor.reset(other.atomicOpFunctor ?
495  other.atomicOpFunctor->clone() : nullptr);
496  }
497 
498  ~Request() {}
499 
503  void
504  setContext(ContextID context_id)
505  {
506  _contextId = context_id;
508  }
509 
510  void
511  setStreamId(uint32_t sid)
512  {
513  _streamId = sid;
515  }
516 
517  void
518  setSubstreamId(uint32_t ssid)
519  {
520  assert(hasStreamId());
521  _substreamId = ssid;
523  }
524 
529  void
530  setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc,
531  AtomicOpFunctorPtr amo_op=nullptr)
532  {
533  _vaddr = vaddr;
534  _size = size;
535  _requestorId = id;
536  _pc = pc;
537  _time = curTick();
538 
540  _flags.set(flags);
543  depth = 0;
544  accessDelta = 0;
545  translateDelta = 0;
546  atomicOpFunctor = std::move(amo_op);
547  _localAccessor = nullptr;
548  }
549 
554  void
555  setPaddr(Addr paddr)
556  {
557  _paddr = paddr;
559  }
560 
565  // TODO: this function is still required by TimingSimpleCPU - should be
566  // removed once TimingSimpleCPU will support arbitrarily long multi-line
567  // mem. accesses
568  void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
569  {
570  assert(hasVaddr());
571  assert(!hasPaddr());
572  assert(split_addr > _vaddr && split_addr < _vaddr + _size);
573  req1 = std::make_shared<Request>(*this);
574  req2 = std::make_shared<Request>(*this);
575  req1->_size = split_addr - _vaddr;
576  req2->_vaddr = split_addr;
577  req2->_size = _size - req1->_size;
578  req1->_byteEnable = std::vector<bool>(
579  _byteEnable.begin(),
580  _byteEnable.begin() + req1->_size);
581  req2->_byteEnable = std::vector<bool>(
582  _byteEnable.begin() + req1->_size,
583  _byteEnable.end());
584  }
585 
589  bool
590  hasPaddr() const
591  {
593  }
594 
595  Addr
596  getPaddr() const
597  {
598  assert(hasPaddr());
599  return _paddr;
600  }
601 
605  bool
606  hasInstCount() const
607  {
609  }
610 
612  {
613  assert(hasInstCount());
614  return _instCount;
615  }
616 
618  {
620  _instCount = val;
621  }
622 
627 
633 
638  mutable int depth = 0;
639 
643  bool
644  hasSize() const
645  {
646  return privateFlags.isSet(VALID_SIZE);
647  }
648 
649  unsigned
650  getSize() const
651  {
652  assert(hasSize());
653  return _size;
654  }
655 
656  const std::vector<bool>&
658  {
659  return _byteEnable;
660  }
661 
662  void
664  {
665  assert(be.size() == _size);
666  _byteEnable = be;
667  }
668 
674  bool
675  isMasked() const
676  {
677  return std::find(
678  _byteEnable.begin(),
679  _byteEnable.end(),
680  false) != _byteEnable.end();
681  }
682 
684  Tick
685  time() const
686  {
687  assert(hasPaddr() || hasVaddr());
688  return _time;
689  }
690 
692  bool isLocalAccess() { return (bool)_localAccessor; }
696  Cycles
698  {
699  return _localAccessor(tc, pkt);
700  }
701 
705  bool
707  {
708  return (bool)atomicOpFunctor;
709  }
710 
713  {
714  assert(atomicOpFunctor);
715  return atomicOpFunctor.get();
716  }
717 
721  bool
723  {
725  }
726 
729  {
730  assert(hasHtmAbortCause());
731  return _htmAbortCause;
732  }
733 
734  void
736  {
737  assert(isHTMAbort());
740  }
741 
743  Flags
745  {
746  assert(hasPaddr() || hasVaddr());
747  return _flags;
748  }
749 
754  void
756  {
757  assert(hasPaddr() || hasVaddr());
758  _flags.set(flags);
759  }
760 
761  void
763  {
764  // TODO: do mem_sync_op requests have valid paddr/vaddr?
765  assert(hasPaddr() || hasVaddr());
766  _cacheCoherenceFlags.set(extraFlags);
767  }
768 
770  bool
771  hasVaddr() const
772  {
774  }
775 
776  Addr
777  getVaddr() const
778  {
779  assert(privateFlags.isSet(VALID_VADDR));
780  return _vaddr;
781  }
782 
785  requestorId() const
786  {
787  return _requestorId;
788  }
789 
790  uint32_t
791  taskId() const
792  {
793  return _taskId;
794  }
795 
796  void
797  taskId(uint32_t id) {
798  _taskId = id;
799  }
800 
803  getArchFlags() const
804  {
805  assert(hasPaddr() || hasVaddr());
806  return _flags & ARCH_BITS;
807  }
808 
810  bool
812  {
814  }
815 
817  uint64_t
818  getExtraData() const
819  {
820  assert(extraDataValid());
821  return _extraData;
822  }
823 
825  void
826  setExtraData(uint64_t extraData)
827  {
828  _extraData = extraData;
830  }
831 
832  bool
833  hasContextId() const
834  {
836  }
837 
839  ContextID
840  contextId() const
841  {
842  assert(hasContextId());
843  return _contextId;
844  }
845 
846  bool
847  hasStreamId() const
848  {
850  }
851 
852  uint32_t
853  streamId() const
854  {
855  assert(hasStreamId());
856  return _streamId;
857  }
858 
859  bool
861  {
863  }
864 
865  uint32_t
866  substreamId() const
867  {
868  assert(hasSubstreamId());
869  return _substreamId;
870  }
871 
872  void
874  {
876  _pc = pc;
877  }
878 
879  bool
880  hasPC() const
881  {
882  return privateFlags.isSet(VALID_PC);
883  }
884 
886  Addr
887  getPC() const
888  {
889  assert(hasPC());
890  return _pc;
891  }
892 
897  void incAccessDepth() const { depth++; }
898  int getAccessDepth() const { return depth; }
899 
905 
911  Tick getAccessLatency() const { return accessDelta; }
912 
917  bool
919  {
921  }
922 
923  InstSeqNum
925  {
926  assert(hasInstSeqNum());
927  return _reqInstSeqNum;
928  }
929 
930  void
932  {
934  _reqInstSeqNum = seq_num;
935  }
936 
939  bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
940  bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
941  bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
942  bool isPrefetch() const { return (_flags.isSet(PREFETCH) ||
944  bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
945  bool isLLSC() const { return _flags.isSet(LLSC); }
946  bool isPriv() const { return _flags.isSet(PRIVILEGED); }
947  bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
948  bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
949  bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
950  bool isSecure() const { return _flags.isSet(SECURE); }
951  bool isPTWalk() const { return _flags.isSet(PT_WALK); }
952  bool isRelease() const { return _flags.isSet(RELEASE); }
953  bool isKernel() const { return _flags.isSet(KERNEL); }
954  bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
956  // hardware transactional memory
957  bool isHTMStart() const { return _flags.isSet(HTM_START); }
958  bool isHTMCommit() const { return _flags.isSet(HTM_COMMIT); }
959  bool isHTMCancel() const { return _flags.isSet(HTM_CANCEL); }
960  bool isHTMAbort() const { return _flags.isSet(HTM_ABORT); }
961  bool
962  isHTMCmd() const
963  {
964  return (isHTMStart() || isHTMCommit() ||
965  isHTMCancel() || isHTMAbort());
966  }
967 
968  bool
969  isAtomic() const
970  {
971  return _flags.isSet(ATOMIC_RETURN_OP) ||
973  }
974 
982  bool isToPOU() const { return _flags.isSet(DST_POU); }
983  bool isToPOC() const { return _flags.isSet(DST_POC); }
984  Flags getDest() const { return _flags & DST_BITS; }
985 
986  bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
987 
993  bool isInvL1() const { return _cacheCoherenceFlags.isSet(INV_L1); }
994 
995  bool
997  {
999  }
1000 
1013  bool isCacheClean() const { return _flags.isSet(CLEAN); }
1014  bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
1015  bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
1017 };
1018 
1019 } // namespace gem5
1020 
1021 #endif // __MEM_REQUEST_HH__
gem5::Request::VALID_INST_SEQ_NUM
@ VALID_INST_SEQ_NUM
Whether or not the instruction sequence number is valid.
Definition: request.hh:339
gem5::Request::getReqInstSeqNum
InstSeqNum getReqInstSeqNum() const
Definition: request.hh:924
gem5::Request::hasStreamId
bool hasStreamId() const
Definition: request.hh:847
gem5::Request::hasHtmAbortCause
bool hasHtmAbortCause() const
Accessor for hardware transactional memory abort cause.
Definition: request.hh:722
gem5::Request::I_CACHE_INV
@ I_CACHE_INV
mem_sync_op flags
Definition: request.hh:304
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Request::_instCount
Counter _instCount
The instruction count at the time this request is created.
Definition: request.hh:443
gem5::Request::_flags
Flags _flags
Flag structure for the request.
Definition: request.hh:385
gem5::Request::isAtomicNoReturn
bool isAtomicNoReturn() const
Definition: request.hh:955
gem5::Request::setLocalAccessor
void setLocalAccessor(LocalAccessor acc)
Set the function which will enact that access.
Definition: request.hh:694
gem5::Request::_size
unsigned _size
The size of the request.
Definition: request.hh:374
gem5::Request::Request
Request()
Minimal constructor.
Definition: request.hh:455
gem5::Request::READ_WRITE
@ READ_WRITE
Definition: request.hh:318
gem5::Request::HTM_START
@ HTM_START
hardware transactional memory
Definition: request.hh:205
gem5::Request::VALID_EXTRA_DATA
@ VALID_EXTRA_DATA
Whether or not the sc result is valid.
Definition: request.hh:345
gem5::Request::getArchFlags
ArchFlagsType getArchFlags() const
Accessor function for architecture-specific flags.
Definition: request.hh:803
gem5::Request::setAccessLatency
void setAccessLatency()
Set/Get the time taken to complete this request's access, not including the time to successfully tran...
Definition: request.hh:910
gem5::Request::PrivateFlags
gem5::Flags< PrivateFlagsType > PrivateFlags
Definition: request.hh:328
gem5::Request::_localAccessor
LocalAccessor _localAccessor
Definition: request.hh:440
gem5::Request::_requestorId
RequestorID _requestorId
The requestor ID which is unique in the system for all ports that are capable of issuing a transactio...
Definition: request.hh:382
gem5::Request::hasAtomicOpFunctor
bool hasAtomicOpFunctor()
Accessor for atomic-op functor.
Definition: request.hh:706
gem5::Request::isStrictlyOrdered
bool isStrictlyOrdered() const
Definition: request.hh:940
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::Request::GL1_CACHE_INV
@ GL1_CACHE_INV
Definition: request.hh:308
gem5::Request::ACQUIRE
@ ACQUIRE
The request should be marked with ACQUIRE.
Definition: request.hh:168
gem5::Request::isPrefetch
bool isPrefetch() const
Definition: request.hh:942
gem5::Request::getAccessLatency
Tick getAccessLatency() const
Definition: request.hh:911
gem5::Request::isPTWalk
bool isPTWalk() const
Definition: request.hh:951
gem5::Request::isPrefetchEx
bool isPrefetchEx() const
Definition: request.hh:944
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::RiscvISA::Unknown
Static instruction class for unknown (illegal) instructions.
Definition: unknown.hh:53
gem5::Request::isUncacheable
bool isUncacheable() const
Accessor functions for flags.
Definition: request.hh:939
gem5::AtomicOpFunctor
Definition: amo.hh:43
amo.hh
gem5::Request::LocalAccessor
std::function< Cycles(ThreadContext *tc, Packet *pkt)> LocalAccessor
Definition: request.hh:324
gem5::Request::HTM_ABORT
@ HTM_ABORT
The request aborts a HTM transaction.
Definition: request.hh:214
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
gem5::Request::isSecure
bool isSecure() const
Definition: request.hh:950
gem5::Request::getSize
unsigned getSize() const
Definition: request.hh:650
gem5::Request::splitOnVaddr
void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
Generate two requests as if this request had been split into two pieces.
Definition: request.hh:568
gem5::Request::PT_WALK
@ PT_WALK
The request is a page table walk.
Definition: request.hh:186
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:247
gem5::Request::V_CACHE_INV
@ V_CACHE_INV
Definition: request.hh:306
gem5::Request::K_CACHE_INV
@ K_CACHE_INV
Definition: request.hh:307
gem5::Flags::clear
void clear()
Clear all flag's bits.
Definition: flags.hh:102
gem5::Request::VALID_PC
@ VALID_PC
Whether or not the pc is valid.
Definition: request.hh:341
gem5::Request::CACHE_BLOCK_ZERO
@ CACHE_BLOCK_ZERO
This is a write that is targeted and zeroing an entire cache block.
Definition: request.hh:143
gem5::Request::PF_EXCLUSIVE
@ PF_EXCLUSIVE
The request should be prefetched into the exclusive state.
Definition: request.hh:164
gem5::Request::_extraData
uint64_t _extraData
Extra data for the request, such as the return value of store conditional or the compare value for a ...
Definition: request.hh:426
gem5::Request::streamId
uint32_t streamId() const
Definition: request.hh:853
cur_tick.hh
gem5::Request::getInstCount
Counter getInstCount() const
Definition: request.hh:611
gem5::Request::Request
Request(const Request &other)
Definition: request.hh:479
htm.hh
gem5::Request::SLC_BIT
@ SLC_BIT
user-policy flags
Definition: request.hh:313
gem5::Request::isRelease
bool isRelease() const
Definition: request.hh:952
gem5::Request::setReqInstSeqNum
void setReqInstSeqNum(const InstSeqNum seq_num)
Definition: request.hh:931
gem5::Request::MEM_SWAP
@ MEM_SWAP
This request is for a memory swap.
Definition: request.hh:158
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::Request::HTM_CMD
static const FlagsType HTM_CMD
Definition: request.hh:247
gem5::Request::~Request
~Request()
Definition: request.hh:498
gem5::Request::getHtmAbortCause
HtmFailureFaultCause getHtmAbortCause() const
Definition: request.hh:728
gem5::Request::isInvL1
bool isInvL1() const
Accessor functions for the memory space configuration flags and used by GPU ISAs such as the Heteroge...
Definition: request.hh:993
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::Request::_paddr
Addr _paddr
The physical address of the request.
Definition: request.hh:367
std::vector< bool >
gem5::Request::isPriv
bool isPriv() const
Definition: request.hh:946
gem5::Request::VALID_SIZE
@ VALID_SIZE
Whether or not the size is valid.
Definition: request.hh:333
gem5::Request::getDest
Flags getDest() const
Definition: request.hh:984
gem5::Request::hasInstSeqNum
bool hasInstSeqNum() const
Accessor for the sequence number of instruction that creates the request.
Definition: request.hh:918
gem5::Request::FlagsType
uint64_t FlagsType
Definition: request.hh:100
gem5::Request::setPC
void setPC(Addr pc)
Definition: request.hh:873
gem5::Request::getPaddr
Addr getPaddr() const
Definition: request.hh:596
gem5::Request::Request
Request(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc, ContextID cid, AtomicOpFunctorPtr atomic_op=nullptr)
Definition: request.hh:470
gem5::Request::hasVaddr
bool hasVaddr() const
Accessor function for vaddr.
Definition: request.hh:771
gem5::Request::CLEAN
@ CLEAN
The request cleans a memory location.
Definition: request.hh:191
gem5::Request::isAtomic
bool isAtomic() const
Definition: request.hh:969
gem5::Request::setStreamId
void setStreamId(uint32_t sid)
Definition: request.hh:511
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Request::FLUSH_L2
@ FLUSH_L2
Definition: request.hh:310
gem5::Request::HTM_CANCEL
@ HTM_CANCEL
The request cancels a HTM transaction.
Definition: request.hh:211
gem5::Request::ATOMIC_RETURN_OP
@ ATOMIC_RETURN_OP
The request is an atomic that returns data.
Definition: request.hh:173
gem5::Request::STICKY_PRIVATE_FLAGS
@ STICKY_PRIVATE_FLAGS
These flags are not cleared when a Request object is reused (assigned a new address).
Definition: request.hh:358
gem5::Request::_taskId
uint32_t _taskId
The task id associated with this request.
Definition: request.hh:403
gem5::Request::isHTMAbort
bool isHTMAbort() const
Definition: request.hh:960
gem5::Request::Flags
gem5::Flags< FlagsType > Flags
Definition: request.hh:102
gem5::Request::getExtraData
uint64_t getExtraData() const
Accessor function for store conditional return value.
Definition: request.hh:818
gem5::Request::DST_POU
@ DST_POU
The request targets the point of unification.
Definition: request.hh:194
gem5::Request::taskId
uint32_t taskId() const
Definition: request.hh:791
gem5::Flags< FlagsType >
gem5::Request::_pc
Addr _pc
program counter of initiating access; for tracing/debugging
Definition: request.hh:432
gem5::context_switch_task_id::TaskId
TaskId
Definition: request.hh:80
gem5::Request::privateFlags
PrivateFlags privateFlags
Private flags for field validity checking.
Definition: request.hh:391
gem5::Request::STICKY_FLAGS
@ STICKY_FLAGS
These flags are not cleared when a Request object is reused (assigned a new address).
Definition: request.hh:242
gem5::Request::setHtmAbortCause
void setHtmAbortCause(HtmFailureFaultCause val)
Definition: request.hh:735
gem5::Request::ATOMIC_NO_RETURN_OP
@ ATOMIC_NO_RETURN_OP
The request is an atomic that does not return data.
Definition: request.hh:175
inst_seq.hh
gem5::Request::INV_L1
@ INV_L1
Definition: request.hh:305
gem5::Request::getFlags
Flags getFlags()
Accessor for flags.
Definition: request.hh:744
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::Request::SECURE
@ SECURE
The request targets the secure memory space.
Definition: request.hh:184
gem5::Request::DST_POC
@ DST_POC
The request targets the point of coherence.
Definition: request.hh:197
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::Request::hasSize
bool hasSize() const
Accessor for size.
Definition: request.hh:644
gem5::Request::isHTMStart
bool isHTMStart() const
Definition: request.hh:957
gem5::MaxAddr
const Addr MaxAddr
Definition: types.hh:171
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::Request::isSwap
bool isSwap() const
Definition: request.hh:948
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Request::GLC_BIT
@ GLC_BIT
Definition: request.hh:315
gem5::Request::substreamId
uint32_t substreamId() const
Definition: request.hh:866
gem5::Request::setPaddr
void setPaddr(Addr paddr)
Set just the physical address.
Definition: request.hh:555
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::Request::_time
Tick _time
The time this request was started.
Definition: request.hh:398
gem5::Request::CacheCoherenceFlagsType
uint64_t CacheCoherenceFlagsType
Definition: request.hh:271
gem5::Request::VALID_INST_COUNT
@ VALID_INST_COUNT
Whether or not the instruction count is valid.
Definition: request.hh:353
gem5::Request::_cacheCoherenceFlags
CacheCoherenceFlags _cacheCoherenceFlags
Flags that control how downstream cache system maintains coherence.
Definition: request.hh:388
gem5::Request::VALID_SUBSTREAM_ID
@ VALID_SUBSTREAM_ID
Definition: request.hh:348
gem5::Request::isAcquire
bool isAcquire() const
Definition: request.hh:986
gem5::context_switch_task_id::NumTaskId
@ NumTaskId
Definition: request.hh:86
gem5::MipsISA::be
Bitfield< 15 > be
Definition: pra_constants.hh:223
gem5::Request::GL2_CACHE_INV
@ GL2_CACHE_INV
Definition: request.hh:311
gem5::Request::setExtraData
void setExtraData(uint64_t extraData)
Accessor function for store conditional return value.
Definition: request.hh:826
gem5::Request::isAtomicReturn
bool isAtomicReturn() const
Definition: request.hh:954
gem5::Request::getAccessDepth
int getAccessDepth() const
Definition: request.hh:898
gem5::Request::isCacheMaintenance
bool isCacheMaintenance() const
Definition: request.hh:1015
gem5::Request::isInstFetch
bool isInstFetch() const
Definition: request.hh:941
gem5::Request::isLLSC
bool isLLSC() const
Definition: request.hh:945
gem5::HtmFailureFaultCause::INVALID
@ INVALID
compiler.hh
gem5::Request::hasSubstreamId
bool hasSubstreamId() const
Definition: request.hh:860
gem5::Request::hasPaddr
bool hasPaddr() const
Accessor for paddr.
Definition: request.hh:590
gem5::Request::setSubstreamId
void setSubstreamId(uint32_t ssid)
Definition: request.hh:518
gem5::Request::SHARED
@ SHARED
Definition: request.hh:319
gem5::Request::setContext
void setContext(ContextID context_id)
Set up Context numbers.
Definition: request.hh:504
gem5::Request::CACHED
@ CACHED
mtype flags
Definition: request.hh:317
gem5::Request::_substreamId
uint32_t _substreamId
The substream ID identifies an "execution context" within a device behind an SMMU/IOMMU.
Definition: request.hh:418
gem5::Request::VALID_STREAM_ID
@ VALID_STREAM_ID
Whether or not the stream ID and substream ID is valid.
Definition: request.hh:347
gem5::Request::RELEASE
@ RELEASE
The request should be marked with RELEASE.
Definition: request.hh:170
gem5::Request::isGL2CacheFlush
bool isGL2CacheFlush() const
Definition: request.hh:996
gem5::Request::isHTMCmd
bool isHTMCmd() const
Definition: request.hh:962
gem5::Request::KERNEL
@ KERNEL
The request should be marked with KERNEL.
Definition: request.hh:181
gem5::Request::isCacheInvalidate
bool isCacheInvalidate() const
Definition: request.hh:1014
gem5::Request::_htmAbortCause
HtmFailureFaultCause _htmAbortCause
The cause for HTM transaction abort.
Definition: request.hh:446
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Request::isKernel
bool isKernel() const
Definition: request.hh:953
gem5::Request::setFlags
void setFlags(Flags flags)
Note that unlike other accessors, this function sets specific flags (ORs them in); it does not assign...
Definition: request.hh:755
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::Request::getByteEnable
const std::vector< bool > & getByteEnable() const
Definition: request.hh:657
gem5::Request::CacheCoherenceFlags
gem5::Flags< CacheCoherenceFlagsType > CacheCoherenceFlags
Definition: request.hh:272
gem5::Request::requestorId
RequestorID requestorId() const
Accesssor for the requestor id.
Definition: request.hh:785
gem5::context_switch_task_id::DMA
@ DMA
Definition: request.hh:84
flags.hh
gem5::Request::PrivateFlagsType
uint16_t PrivateFlagsType
Definition: request.hh:327
gem5::Request::_reqInstSeqNum
InstSeqNum _reqInstSeqNum
Sequence number of the instruction that creates the request.
Definition: request.hh:435
gem5::Request::localAccessor
Cycles localAccessor(ThreadContext *tc, Packet *pkt)
Perform the installed local access.
Definition: request.hh:697
gem5::Request::isHTMCancel
bool isHTMCancel() const
Definition: request.hh:959
gem5::Request::isLockedRMW
bool isLockedRMW() const
Definition: request.hh:947
gem5::Request::setVirt
void setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc, AtomicOpFunctorPtr amo_op=nullptr)
Set up a virtual (e.g., CPU) request in a previously allocated Request object.
Definition: request.hh:530
gem5::Request::STORE_NO_DATA
static const FlagsType STORE_NO_DATA
Definition: request.hh:244
gem5::Request::VALID_PADDR
@ VALID_PADDR
Whether or not paddr is valid (has been written yet).
Definition: request.hh:335
gem5::Request::ArchFlagsType
uint8_t ArchFlagsType
Definition: request.hh:101
gem5::Request::MEM_SWAP_COND
@ MEM_SWAP_COND
Definition: request.hh:159
gem5::context_switch_task_id::Unknown
@ Unknown
Definition: request.hh:85
gem5::Request::ARCH_BITS
@ ARCH_BITS
Architecture specific flags.
Definition: request.hh:113
gem5::Request::atomicOpFunctor
AtomicOpFunctorPtr atomicOpFunctor
A pointer to an atomic operation.
Definition: request.hh:438
gem5::Request::contextId
ContextID contextId() const
Accessor function for context ID.
Definition: request.hh:840
gem5::Request::VALID_VADDR
@ VALID_VADDR
Whether or not the vaddr is valid.
Definition: request.hh:337
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:260
gem5::context_switch_task_id::MaxNormalTaskId
@ MaxNormalTaskId
Definition: request.hh:82
gem5::Request::K_CACHE_WB
@ K_CACHE_WB
Definition: request.hh:309
gem5::Request::setByteEnable
void setByteEnable(const std::vector< bool > &be)
Definition: request.hh:663
gem5::Request::LLSC
@ LLSC
The request is a Load locked/store conditional.
Definition: request.hh:156
gem5::Request::hasContextId
bool hasContextId() const
Definition: request.hh:833
gem5::Request::hasInstCount
bool hasInstCount() const
Accessor for instruction count.
Definition: request.hh:606
types.hh
gem5::Request
Definition: request.hh:97
gem5::Request::setTranslateLatency
void setTranslateLatency()
Set/Get the time taken for this request to be successfully translated.
Definition: request.hh:903
gem5::Request::_streamId
uint32_t _streamId
The stream ID uniquely identifies a device behind the SMMU/IOMMU Each transaction arriving at the SMM...
Definition: request.hh:410
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:246
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::Request::isCacheClean
bool isCacheClean() const
Accessor functions to determine whether this request is part of a cache maintenance operation.
Definition: request.hh:1013
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::Request::getAtomicOpFunctor
AtomicOpFunctor * getAtomicOpFunctor()
Definition: request.hh:712
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:250
gem5::Request::taskId
void taskId(uint32_t id)
Definition: request.hh:797
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::Request::INVALIDATE
@ INVALIDATE
The request invalidates a memory location.
Definition: request.hh:189
gem5::Request::hasPC
bool hasPC() const
Definition: request.hh:880
gem5::Request::wbRequestorId
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
Definition: request.hh:255
gem5::Request::time
Tick time() const
Accessor for time.
Definition: request.hh:685
gem5::Request::_byteEnable
std::vector< bool > _byteEnable
Byte-enable mask for writes.
Definition: request.hh:377
gem5::Request::_contextId
ContextID _contextId
The context ID (for statistics, locks, and wakeups).
Definition: request.hh:429
gem5::Request::LOCKED_RMW
@ LOCKED_RMW
This request will lock or unlock the accessed memory.
Definition: request.hh:154
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::Request::_vaddr
Addr _vaddr
The virtual address of the request.
Definition: request.hh:421
gem5::Request::getVaddr
Addr getVaddr() const
Definition: request.hh:777
gem5::Request::incAccessDepth
void incAccessDepth() const
Increment/Get the depth at which this request is responded to.
Definition: request.hh:897
gem5::Request::PREFETCH
@ PREFETCH
The request is a prefetch.
Definition: request.hh:162
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::Request::getTranslateLatency
Tick getTranslateLatency() const
Definition: request.hh:904
gem5::Request::isCondSwap
bool isCondSwap() const
Definition: request.hh:949
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::Request::PRIVILEGED
@ PRIVILEGED
This request is made in privileged mode.
Definition: request.hh:137
gem5::Request::isMasked
bool isMasked() const
Returns true if the memory request is masked, which means there is at least one byteEnable element wh...
Definition: request.hh:675
gem5::Request::translateDelta
Tick translateDelta
Time for the TLB/table walker to successfully translate this request.
Definition: request.hh:626
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:262
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::Request::isToPOC
bool isToPOC() const
Definition: request.hh:983
gem5::Request::VALID_HTM_ABORT_CAUSE
@ VALID_HTM_ABORT_CAUSE
Whether or not the abort cause is valid.
Definition: request.hh:351
gem5::Request::DLC_BIT
@ DLC_BIT
Definition: request.hh:314
gem5::Request::HTM_COMMIT
@ HTM_COMMIT
The request commits a HTM transaction.
Definition: request.hh:208
gem5::Request::Request
Request(Addr paddr, unsigned size, Flags flags, RequestorID id)
Constructor for physical (e.g.
Definition: request.hh:462
gem5::Request::isLocalAccess
bool isLocalAccess()
Is this request for a local memory mapped resource/register?
Definition: request.hh:692
gem5::Request::isToPOU
bool isToPOU() const
Accessor functions for the destination of a memory request.
Definition: request.hh:982
gem5::Request::setInstCount
void setInstCount(Counter val)
Definition: request.hh:617
gem5::Request::depth
int depth
Level of the cache hierachy where this request was responded to (e.g.
Definition: request.hh:638
gem5::Request::EVICT_NEXT
@ EVICT_NEXT
The request should be marked as LRU.
Definition: request.hh:166
gem5::Request::extraDataValid
bool extraDataValid() const
Accessor function to check if sc result is valid.
Definition: request.hh:811
gem5::Request::invldRequestorId
@ invldRequestorId
Invalid requestor id for assertion checking only.
Definition: request.hh:267
gem5::Request::getPC
Addr getPC() const
Accessor function for pc.
Definition: request.hh:887
gem5::Request::VALID_CONTEXT_ID
@ VALID_CONTEXT_ID
Whether or not the context ID is valid.
Definition: request.hh:343
gem5::Request::DST_BITS
@ DST_BITS
Bits to define the destination of a request.
Definition: request.hh:200
gem5::Request::isHTMCommit
bool isHTMCommit() const
Definition: request.hh:958
gem5::Request::accessDelta
Tick accessDelta
Access latency to complete this memory transaction not including translation time.
Definition: request.hh:632
gem5::Request::setCacheCoherenceFlags
void setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
Definition: request.hh:762

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