gem5  v22.0.0.2
request.hh
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41 
48 #ifndef __MEM_REQUEST_HH__
49 #define __MEM_REQUEST_HH__
50 
51 #include <algorithm>
52 #include <cassert>
53 #include <cstdint>
54 #include <functional>
55 #include <limits>
56 #include <memory>
57 #include <vector>
58 
59 #include "base/amo.hh"
60 #include "base/compiler.hh"
61 #include "base/flags.hh"
62 #include "base/types.hh"
63 #include "cpu/inst_seq.hh"
64 #include "mem/htm.hh"
65 #include "sim/cur_tick.hh"
66 
67 namespace gem5
68 {
69 
77 GEM5_DEPRECATED_NAMESPACE(ContextSwitchTaskId, context_switch_task_id);
78 namespace context_switch_task_id
79 {
80  enum TaskId
81  {
82  MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
83  Prefetcher = 1022, /* For cache lines brought in by prefetcher */
84  DMA = 1023, /* Mostly Table Walker */
85  Unknown = 1024,
87  };
88 }
89 
90 class Packet;
91 class Request;
93 
94 typedef std::shared_ptr<Request> RequestPtr;
95 typedef uint16_t RequestorID;
96 
97 class Request
98 {
99  public:
100  typedef uint64_t FlagsType;
101  typedef uint8_t ArchFlagsType;
103 
104  enum : FlagsType
105  {
113  ARCH_BITS = 0x000000FF,
115  INST_FETCH = 0x00000100,
117  PHYSICAL = 0x00000200,
125  UNCACHEABLE = 0x00000400,
135  STRICT_ORDER = 0x00000800,
137  PRIVILEGED = 0x00008000,
138 
143  CACHE_BLOCK_ZERO = 0x00010000,
144 
146  NO_ACCESS = 0x00080000,
154  LOCKED_RMW = 0x00100000,
156  LLSC = 0x00200000,
158  MEM_SWAP = 0x00400000,
159  MEM_SWAP_COND = 0x00800000,
161  READ_MODIFY_WRITE = 0x00020000,
162 
164  PREFETCH = 0x01000000,
166  PF_EXCLUSIVE = 0x02000000,
168  EVICT_NEXT = 0x04000000,
170  ACQUIRE = 0x00020000,
172  RELEASE = 0x00040000,
173 
175  ATOMIC_RETURN_OP = 0x40000000,
177  ATOMIC_NO_RETURN_OP = 0x80000000,
178 
183  KERNEL = 0x00001000,
184 
186  SECURE = 0x10000000,
188  PT_WALK = 0x20000000,
189 
191  INVALIDATE = 0x0000000100000000,
193  CLEAN = 0x0000000200000000,
194 
196  DST_POU = 0x0000001000000000,
197 
199  DST_POC = 0x0000002000000000,
200 
202  DST_BITS = 0x0000003000000000,
203 
207  HTM_START = 0x0000010000000000,
208 
210  HTM_COMMIT = 0x0000020000000000,
211 
213  HTM_CANCEL = 0x0000040000000000,
214 
216  HTM_ABORT = 0x0000080000000000,
217 
218  // What is the different between HTM cancel and abort?
219  //
220  // HTM_CANCEL will originate from a user instruction, e.g.
221  // Arm's TCANCEL or x86's XABORT. This is an explicit request
222  // to end a transaction and restore from the last checkpoint.
223  //
224  // HTM_ABORT is an internally generated request used to synchronize
225  // a transaction's failure between the core and memory subsystem.
226  // If a transaction fails in the core, e.g. because an instruction
227  // within the transaction generates an exception, the core will prepare
228  // itself to stop fetching/executing more instructions and send an
229  // HTM_ABORT to the memory subsystem before restoring the checkpoint.
230  // Similarly, the transaction could fail in the memory subsystem and
231  // this will be communicated to the core via the Packet object.
232  // Once the core notices, it will do the same as the above and send
233  // a HTM_ABORT to the memory subsystem.
234  // A HTM_CANCEL sent to the memory subsystem will ultimately return
235  // to the core which in turn will send a HTM_ABORT.
236  //
237  // This separation is necessary to ensure the disjoint components
238  // of the system work correctly together.
239 
241  TLBI = 0x0000100000000000,
242 
244  TLBI_SYNC = 0x0000200000000000,
245 
248  TLBI_EXT_SYNC = 0x0000400000000000,
249 
252  TLBI_EXT_SYNC_COMP = 0x0000800000000000,
253 
259  };
261  CLEAN | INVALIDATE;
262 
265 
266  static const FlagsType TLBI_CMD = TLBI | TLBI_SYNC |
268 
271  enum : RequestorID
272  {
286  invldRequestorId = std::numeric_limits<RequestorID>::max()
287  };
290  typedef uint64_t CacheCoherenceFlagsType;
292 
321  {
323  I_CACHE_INV = 0x00000001,
325  V_CACHE_INV = 0x00000002,
326  K_CACHE_INV = 0x00000004,
327  GL1_CACHE_INV = 0x00000008,
328  K_CACHE_WB = 0x00000010,
329  FLUSH_L2 = 0x00000020,
330  GL2_CACHE_INV = 0x00000040,
332  SLC_BIT = 0x00000080,
333  DLC_BIT = 0x00000100,
334  GLC_BIT = 0x00000200,
336  CACHED = 0x00000400,
337  READ_WRITE = 0x00000800,
338  SHARED = 0x00001000,
339 
340  };
341 
342  using LocalAccessor =
343  std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
344 
345  private:
346  typedef uint16_t PrivateFlagsType;
348 
349  enum : PrivateFlagsType
350  {
352  VALID_SIZE = 0x00000001,
354  VALID_PADDR = 0x00000002,
356  VALID_VADDR = 0x00000004,
358  VALID_INST_SEQ_NUM = 0x00000008,
360  VALID_PC = 0x00000010,
362  VALID_CONTEXT_ID = 0x00000020,
364  VALID_EXTRA_DATA = 0x00000080,
366  VALID_STREAM_ID = 0x00000100,
367  VALID_SUBSTREAM_ID = 0x00000200,
368  // hardware transactional memory
370  VALID_HTM_ABORT_CAUSE = 0x00000400,
372  VALID_INST_COUNT = 0x00000800,
378  };
379 
380  private:
381 
387 
393  unsigned _size = 0;
394 
397 
402 
405 
408 
411 
418 
423 
429  uint32_t _streamId = 0;
430 
437  uint32_t _substreamId = 0;
438 
443  bool _systemReq = 0;
444 
447 
451  uint64_t _extraData = 0;
452 
455 
458 
461 
464 
466 
469 
472 
473  public:
474 
480  Request() {}
481 
487  Request(Addr paddr, unsigned size, Flags flags, RequestorID id) :
488  _paddr(paddr), _size(size), _requestorId(id), _time(curTick())
489  {
490  _flags.set(flags);
492  _byteEnable = std::vector<bool>(size, true);
493  }
494 
495  Request(Addr vaddr, unsigned size, Flags flags,
496  RequestorID id, Addr pc, ContextID cid,
497  AtomicOpFunctorPtr atomic_op=nullptr)
498  {
499  setVirt(vaddr, size, flags, id, pc, std::move(atomic_op));
500  setContext(cid);
501  _byteEnable = std::vector<bool>(size, true);
502  }
503 
504  Request(const Request& other)
505  : _paddr(other._paddr), _size(other._size),
506  _byteEnable(other._byteEnable),
507  _requestorId(other._requestorId),
508  _flags(other._flags),
510  privateFlags(other.privateFlags),
511  _time(other._time),
512  _taskId(other._taskId), _vaddr(other._vaddr),
514  _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
517  accessDelta(other.accessDelta), depth(other.depth)
518  {
519  atomicOpFunctor.reset(other.atomicOpFunctor ?
520  other.atomicOpFunctor->clone() : nullptr);
521  }
522 
523  ~Request() {}
524 
529  static RequestPtr
531  {
532  auto mgmt_req = std::make_shared<Request>();
533  mgmt_req->_flags.set(flags);
534  mgmt_req->_requestorId = id;
535  mgmt_req->_time = curTick();
536 
537  assert(mgmt_req->isMemMgmt());
538  return mgmt_req;
539  }
540 
544  void
545  setContext(ContextID context_id)
546  {
547  _contextId = context_id;
549  }
550 
551  void
552  setStreamId(uint32_t sid)
553  {
554  _streamId = sid;
556  }
557 
558  void
559  setSubstreamId(uint32_t ssid)
560  {
561  assert(hasStreamId());
562  _substreamId = ssid;
564  }
565 
570  void
571  setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc,
572  AtomicOpFunctorPtr amo_op=nullptr)
573  {
574  _vaddr = vaddr;
575  _size = size;
576  _requestorId = id;
577  _pc = pc;
578  _time = curTick();
579 
581  _flags.set(flags);
584  depth = 0;
585  accessDelta = 0;
586  translateDelta = 0;
587  atomicOpFunctor = std::move(amo_op);
588  _localAccessor = nullptr;
589  }
590 
595  void
596  setPaddr(Addr paddr)
597  {
598  _paddr = paddr;
600  }
601 
606  // TODO: this function is still required by TimingSimpleCPU - should be
607  // removed once TimingSimpleCPU will support arbitrarily long multi-line
608  // mem. accesses
609  void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
610  {
611  assert(hasVaddr());
612  assert(!hasPaddr());
613  assert(split_addr > _vaddr && split_addr < _vaddr + _size);
614  req1 = std::make_shared<Request>(*this);
615  req2 = std::make_shared<Request>(*this);
616  req1->_size = split_addr - _vaddr;
617  req2->_vaddr = split_addr;
618  req2->_size = _size - req1->_size;
619  req1->_byteEnable = std::vector<bool>(
620  _byteEnable.begin(),
621  _byteEnable.begin() + req1->_size);
622  req2->_byteEnable = std::vector<bool>(
623  _byteEnable.begin() + req1->_size,
624  _byteEnable.end());
625  }
626 
630  bool
631  hasPaddr() const
632  {
634  }
635 
636  Addr
637  getPaddr() const
638  {
639  assert(hasPaddr());
640  return _paddr;
641  }
642 
646  bool
647  hasInstCount() const
648  {
650  }
651 
653  {
654  assert(hasInstCount());
655  return _instCount;
656  }
657 
659  {
661  _instCount = val;
662  }
663 
668 
674 
679  mutable int depth = 0;
680 
684  bool
685  hasSize() const
686  {
687  return privateFlags.isSet(VALID_SIZE);
688  }
689 
690  unsigned
691  getSize() const
692  {
693  assert(hasSize());
694  return _size;
695  }
696 
697  const std::vector<bool>&
699  {
700  return _byteEnable;
701  }
702 
703  void
705  {
706  assert(be.size() == _size);
707  _byteEnable = be;
708  }
709 
715  bool
716  isMasked() const
717  {
718  return std::find(
719  _byteEnable.begin(),
720  _byteEnable.end(),
721  false) != _byteEnable.end();
722  }
723 
725  Tick
726  time() const
727  {
728  assert(hasPaddr() || hasVaddr());
729  return _time;
730  }
731 
733  bool isLocalAccess() { return (bool)_localAccessor; }
737  Cycles
739  {
740  return _localAccessor(tc, pkt);
741  }
742 
746  bool
748  {
749  return (bool)atomicOpFunctor;
750  }
751 
754  {
755  assert(atomicOpFunctor);
756  return atomicOpFunctor.get();
757  }
758 
762  bool
764  {
766  }
767 
770  {
771  assert(hasHtmAbortCause());
772  return _htmAbortCause;
773  }
774 
775  void
777  {
778  assert(isHTMAbort());
781  }
782 
784  Flags
786  {
787  assert(hasPaddr() || hasVaddr());
788  return _flags;
789  }
790 
795  void
797  {
798  assert(hasPaddr() || hasVaddr());
799  _flags.set(flags);
800  }
801 
802  void
804  {
805  assert(hasPaddr() || hasVaddr());
806  _flags.clear(flags);
807  }
808 
809  void
811  {
812  // TODO: do mem_sync_op requests have valid paddr/vaddr?
813  assert(hasPaddr() || hasVaddr());
814  _cacheCoherenceFlags.set(extraFlags);
815  }
816 
817  void
819  {
820  // TODO: do mem_sync_op requests have valid paddr/vaddr?
821  assert(hasPaddr() || hasVaddr());
822  _cacheCoherenceFlags.clear(extraFlags);
823  }
824 
826  bool
827  hasVaddr() const
828  {
830  }
831 
832  Addr
833  getVaddr() const
834  {
835  assert(privateFlags.isSet(VALID_VADDR));
836  return _vaddr;
837  }
838 
841  requestorId() const
842  {
843  return _requestorId;
844  }
845 
846  void
848  {
849  _requestorId = rid;
850  }
851 
852  uint32_t
853  taskId() const
854  {
855  return _taskId;
856  }
857 
858  void
859  taskId(uint32_t id) {
860  _taskId = id;
861  }
862 
865  getArchFlags() const
866  {
867  assert(hasPaddr() || hasVaddr());
868  return _flags & ARCH_BITS;
869  }
870 
872  bool
874  {
876  }
877 
879  uint64_t
880  getExtraData() const
881  {
882  assert(extraDataValid());
883  return _extraData;
884  }
885 
887  void
888  setExtraData(uint64_t extraData)
889  {
890  _extraData = extraData;
892  }
893 
894  bool
895  hasContextId() const
896  {
898  }
899 
901  ContextID
902  contextId() const
903  {
904  assert(hasContextId());
905  return _contextId;
906  }
907 
908  /* For GPU fullsystem mark this request is not to device memory. */
909  void setSystemReq(bool sysReq) { _systemReq = sysReq; }
910  bool systemReq() const { return _systemReq; }
911 
912  bool
913  hasStreamId() const
914  {
916  }
917 
918  uint32_t
919  streamId() const
920  {
921  assert(hasStreamId());
922  return _streamId;
923  }
924 
925  bool
927  {
929  }
930 
931  uint32_t
932  substreamId() const
933  {
934  assert(hasSubstreamId());
935  return _substreamId;
936  }
937 
938  void
940  {
942  _pc = pc;
943  }
944 
945  bool
946  hasPC() const
947  {
948  return privateFlags.isSet(VALID_PC);
949  }
950 
952  Addr
953  getPC() const
954  {
955  assert(hasPC());
956  return _pc;
957  }
958 
963  void incAccessDepth() const { depth++; }
964  int getAccessDepth() const { return depth; }
965 
971 
977  Tick getAccessLatency() const { return accessDelta; }
978 
983  bool
985  {
987  }
988 
989  InstSeqNum
991  {
992  assert(hasInstSeqNum());
993  return _reqInstSeqNum;
994  }
995 
996  void
998  {
1000  _reqInstSeqNum = seq_num;
1001  }
1002 
1005  bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
1006  bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
1007  bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
1008  bool
1009  isPrefetch() const
1010  {
1011  return (_flags.isSet(PREFETCH | PF_EXCLUSIVE));
1012  }
1013  bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
1014  bool isLLSC() const { return _flags.isSet(LLSC); }
1015  bool isPriv() const { return _flags.isSet(PRIVILEGED); }
1016  bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
1017  bool isSwap() const { return _flags.isSet(MEM_SWAP | MEM_SWAP_COND); }
1018  bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
1019  bool
1021  {
1023  }
1024  bool isSecure() const { return _flags.isSet(SECURE); }
1025  bool isPTWalk() const { return _flags.isSet(PT_WALK); }
1026  bool isRelease() const { return _flags.isSet(RELEASE); }
1027  bool isKernel() const { return _flags.isSet(KERNEL); }
1028  bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
1030  // hardware transactional memory
1031  bool isHTMStart() const { return _flags.isSet(HTM_START); }
1032  bool isHTMCommit() const { return _flags.isSet(HTM_COMMIT); }
1033  bool isHTMCancel() const { return _flags.isSet(HTM_CANCEL); }
1034  bool isHTMAbort() const { return _flags.isSet(HTM_ABORT); }
1035  bool
1036  isHTMCmd() const
1037  {
1038  return (isHTMStart() || isHTMCommit() ||
1039  isHTMCancel() || isHTMAbort());
1040  }
1041 
1042  bool isTlbi() const { return _flags.isSet(TLBI); }
1043  bool isTlbiSync() const { return _flags.isSet(TLBI_SYNC); }
1044  bool isTlbiExtSync() const { return _flags.isSet(TLBI_EXT_SYNC); }
1046  bool
1047  isTlbiCmd() const
1048  {
1049  return (isTlbi() || isTlbiSync() ||
1051  }
1052  bool isMemMgmt() const { return isTlbiCmd() || isHTMCmd(); }
1053 
1054  bool
1055  isAtomic() const
1056  {
1057  return _flags.isSet(ATOMIC_RETURN_OP) ||
1059  }
1060 
1068  bool isToPOU() const { return _flags.isSet(DST_POU); }
1069  bool isToPOC() const { return _flags.isSet(DST_POC); }
1070  Flags getDest() const { return _flags & DST_BITS; }
1071 
1072  bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
1073 
1079  bool isInvL1() const { return _cacheCoherenceFlags.isSet(INV_L1); }
1080 
1081  bool
1083  {
1085  }
1086 
1099  bool isCacheClean() const { return _flags.isSet(CLEAN); }
1100  bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
1101  bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
1103 };
1104 
1105 } // namespace gem5
1106 
1107 #endif // __MEM_REQUEST_HH__
gem5::Request::getReqInstSeqNum
InstSeqNum getReqInstSeqNum() const
Definition: request.hh:990
gem5::Request::hasStreamId
bool hasStreamId() const
Definition: request.hh:913
gem5::Request::hasHtmAbortCause
bool hasHtmAbortCause() const
Accessor for hardware transactional memory abort cause.
Definition: request.hh:763
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::Request::_instCount
Counter _instCount
The instruction count at the time this request is created.
Definition: request.hh:468
gem5::Request::_flags
Flags _flags
Flag structure for the request.
Definition: request.hh:404
gem5::Request::CLEAN
@ CLEAN
The request cleans a memory location.
Definition: request.hh:193
gem5::Request::isTlbi
bool isTlbi() const
Definition: request.hh:1042
gem5::Request::isAtomicNoReturn
bool isAtomicNoReturn() const
Definition: request.hh:1029
gem5::Request::setLocalAccessor
void setLocalAccessor(LocalAccessor acc)
Set the function which will enact that access.
Definition: request.hh:735
gem5::Request::_size
unsigned _size
The size of the request.
Definition: request.hh:393
gem5::Request::ACQUIRE
@ ACQUIRE
The request should be marked with ACQUIRE.
Definition: request.hh:170
gem5::Request::isMemMgmt
bool isMemMgmt() const
Definition: request.hh:1052
gem5::Request::Request
Request()
Minimal constructor.
Definition: request.hh:480
gem5::Request::ATOMIC_NO_RETURN_OP
@ ATOMIC_NO_RETURN_OP
The request is an atomic that does not return data.
Definition: request.hh:177
gem5::Request::ATOMIC_RETURN_OP
@ ATOMIC_RETURN_OP
The request is an atomic that returns data.
Definition: request.hh:175
gem5::Request::getArchFlags
ArchFlagsType getArchFlags() const
Accessor function for architecture-specific flags.
Definition: request.hh:865
gem5::Request::setAccessLatency
void setAccessLatency()
Set/Get the time taken to complete this request's access, not including the time to successfully tran...
Definition: request.hh:976
gem5::Request::PrivateFlags
gem5::Flags< PrivateFlagsType > PrivateFlags
Definition: request.hh:347
gem5::Request::_localAccessor
LocalAccessor _localAccessor
Definition: request.hh:465
gem5::Request::_requestorId
RequestorID _requestorId
The requestor ID which is unique in the system for all ports that are capable of issuing a transactio...
Definition: request.hh:401
gem5::Request::TLBI_EXT_SYNC
@ TLBI_EXT_SYNC
The Request tells the CPU model that a remote TLB Sync has been requested.
Definition: request.hh:248
gem5::Request::hasAtomicOpFunctor
bool hasAtomicOpFunctor()
Accessor for atomic-op functor.
Definition: request.hh:747
gem5::Request::isStrictlyOrdered
bool isStrictlyOrdered() const
Definition: request.hh:1006
gem5::Request::HTM_CANCEL
@ HTM_CANCEL
The request cancels a HTM transaction.
Definition: request.hh:213
gem5::Request::DST_POC
@ DST_POC
The request targets the point of coherence.
Definition: request.hh:199
gem5::Request::isPrefetch
bool isPrefetch() const
Definition: request.hh:1009
gem5::Request::getAccessLatency
Tick getAccessLatency() const
Definition: request.hh:977
gem5::Request::isPTWalk
bool isPTWalk() const
Definition: request.hh:1025
gem5::Request::isPrefetchEx
bool isPrefetchEx() const
Definition: request.hh:1013
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::RiscvISA::Unknown
Static instruction class for unknown (illegal) instructions.
Definition: unknown.hh:53
gem5::Request::isUncacheable
bool isUncacheable() const
Accessor functions for flags.
Definition: request.hh:1005
gem5::AtomicOpFunctor
Definition: amo.hh:43
amo.hh
gem5::Request::LocalAccessor
std::function< Cycles(ThreadContext *tc, Packet *pkt)> LocalAccessor
Definition: request.hh:343
gem5::Request::VALID_INST_SEQ_NUM
@ VALID_INST_SEQ_NUM
Whether or not the instruction sequence number is valid.
Definition: request.hh:358
gem5::Flags::set
void set(Type mask)
Set all flag's bits matching the given mask.
Definition: flags.hh:116
gem5::Request::isSecure
bool isSecure() const
Definition: request.hh:1024
gem5::Request::KERNEL
@ KERNEL
The request should be marked with KERNEL.
Definition: request.hh:183
gem5::Request::getSize
unsigned getSize() const
Definition: request.hh:691
gem5::Request::HTM_ABORT
@ HTM_ABORT
The request aborts a HTM transaction.
Definition: request.hh:216
gem5::Request::splitOnVaddr
void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
Generate two requests as if this request had been split into two pieces.
Definition: request.hh:609
gem5::InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:240
gem5::Request::NO_ACCESS
@ NO_ACCESS
The request should not cause a memory access.
Definition: request.hh:146
gem5::Request::PHYSICAL
@ PHYSICAL
The virtual address is also the physical address.
Definition: request.hh:117
gem5::Flags::clear
void clear()
Clear all flag's bits.
Definition: flags.hh:102
gem5::Request::INST_FETCH
@ INST_FETCH
The request was an instruction fetch.
Definition: request.hh:115
gem5::Request::VALID_STREAM_ID
@ VALID_STREAM_ID
Whether or not the stream ID and substream ID is valid.
Definition: request.hh:366
gem5::Request::MEM_SWAP_COND
@ MEM_SWAP_COND
Definition: request.hh:159
gem5::Request::_extraData
uint64_t _extraData
Extra data for the request, such as the return value of store conditional or the compare value for a ...
Definition: request.hh:451
gem5::Request::streamId
uint32_t streamId() const
Definition: request.hh:919
cur_tick.hh
gem5::Request::getInstCount
Counter getInstCount() const
Definition: request.hh:652
gem5::Request::Request
Request(const Request &other)
Definition: request.hh:504
htm.hh
gem5::Request::SECURE
@ SECURE
The request targets the secure memory space.
Definition: request.hh:186
gem5::Request::CACHE_BLOCK_ZERO
@ CACHE_BLOCK_ZERO
This is a write that is targeted and zeroing an entire cache block.
Definition: request.hh:143
gem5::Request::LOCKED_RMW
@ LOCKED_RMW
This request will lock or unlock the accessed memory.
Definition: request.hh:154
gem5::Request::SLC_BIT
@ SLC_BIT
user-policy flags
Definition: request.hh:332
gem5::Request::isRelease
bool isRelease() const
Definition: request.hh:1026
gem5::Request::setReqInstSeqNum
void setReqInstSeqNum(const InstSeqNum seq_num)
Definition: request.hh:997
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::Request::HTM_CMD
static const FlagsType HTM_CMD
Definition: request.hh:263
gem5::Request::K_CACHE_WB
@ K_CACHE_WB
Definition: request.hh:328
gem5::Request::~Request
~Request()
Definition: request.hh:523
gem5::Request::getHtmAbortCause
HtmFailureFaultCause getHtmAbortCause() const
Definition: request.hh:769
gem5::Request::isInvL1
bool isInvL1() const
Accessor functions for the memory space configuration flags and used by GPU ISAs such as the Heteroge...
Definition: request.hh:1079
gem5::MaxTick
const Tick MaxTick
Definition: types.hh:60
gem5::Request::_paddr
Addr _paddr
The physical address of the request.
Definition: request.hh:386
gem5::Request::V_CACHE_INV
@ V_CACHE_INV
Definition: request.hh:325
std::vector< bool >
gem5::Request::TLBI_SYNC
@ TLBI_SYNC
The Request is a TLB shootdown sync.
Definition: request.hh:244
gem5::Request::K_CACHE_INV
@ K_CACHE_INV
Definition: request.hh:326
gem5::Request::isPriv
bool isPriv() const
Definition: request.hh:1015
gem5::Request::getDest
Flags getDest() const
Definition: request.hh:1070
gem5::Request::ARCH_BITS
@ ARCH_BITS
Architecture specific flags.
Definition: request.hh:113
gem5::Request::READ_MODIFY_WRITE
@ READ_MODIFY_WRITE
This request is a read which will be followed by a write.
Definition: request.hh:161
gem5::Request::INVALIDATE
@ INVALIDATE
The request invalidates a memory location.
Definition: request.hh:191
gem5::Request::READ_WRITE
@ READ_WRITE
Definition: request.hh:337
gem5::Request::CACHED
@ CACHED
mtype flags
Definition: request.hh:336
gem5::Request::hasInstSeqNum
bool hasInstSeqNum() const
Accessor for the sequence number of instruction that creates the request.
Definition: request.hh:984
gem5::Request::HTM_COMMIT
@ HTM_COMMIT
The request commits a HTM transaction.
Definition: request.hh:210
gem5::Request::FlagsType
uint64_t FlagsType
Definition: request.hh:100
gem5::Request::setPC
void setPC(Addr pc)
Definition: request.hh:939
gem5::Request::clearCacheCoherenceFlags
void clearCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
Definition: request.hh:818
gem5::Request::createMemManagement
static RequestPtr createMemManagement(Flags flags, RequestorID id)
Factory method for creating memory management requests, with unspecified addr and size.
Definition: request.hh:530
gem5::Request::getPaddr
Addr getPaddr() const
Definition: request.hh:637
gem5::Request::Request
Request(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc, ContextID cid, AtomicOpFunctorPtr atomic_op=nullptr)
Definition: request.hh:495
gem5::Request::hasVaddr
bool hasVaddr() const
Accessor function for vaddr.
Definition: request.hh:827
gem5::Request::isReadModifyWrite
bool isReadModifyWrite() const
Definition: request.hh:1020
gem5::Request::isAtomic
bool isAtomic() const
Definition: request.hh:1055
gem5::Request::setStreamId
void setStreamId(uint32_t sid)
Definition: request.hh:552
gem5::Request::systemReq
bool systemReq() const
Definition: request.hh:910
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::Request::intRequestorId
@ intRequestorId
This requestor id is used for message signaled interrupts.
Definition: request.hh:281
gem5::Request::_taskId
uint32_t _taskId
The task id associated with this request.
Definition: request.hh:422
gem5::Request::isHTMAbort
bool isHTMAbort() const
Definition: request.hh:1034
gem5::Request::Flags
gem5::Flags< FlagsType > Flags
Definition: request.hh:102
gem5::Request::getExtraData
uint64_t getExtraData() const
Accessor function for store conditional return value.
Definition: request.hh:880
gem5::Request::taskId
uint32_t taskId() const
Definition: request.hh:853
gem5::Flags< FlagsType >
gem5::Request::_pc
Addr _pc
program counter of initiating access; for tracing/debugging
Definition: request.hh:457
gem5::context_switch_task_id::TaskId
TaskId
Definition: request.hh:80
gem5::Request::privateFlags
PrivateFlags privateFlags
Private flags for field validity checking.
Definition: request.hh:410
gem5::Request::VALID_PC
@ VALID_PC
Whether or not the pc is valid.
Definition: request.hh:360
gem5::Request::UNCACHEABLE
@ UNCACHEABLE
The request is to an uncacheable address.
Definition: request.hh:125
gem5::Request::TLBI_CMD
static const FlagsType TLBI_CMD
Definition: request.hh:266
gem5::Request::setHtmAbortCause
void setHtmAbortCause(HtmFailureFaultCause val)
Definition: request.hh:776
inst_seq.hh
gem5::Request::getFlags
Flags getFlags()
Accessor for flags.
Definition: request.hh:785
gem5::Request::MEM_SWAP
@ MEM_SWAP
This request is for a memory swap.
Definition: request.hh:158
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Request::isTlbiExtSync
bool isTlbiExtSync() const
Definition: request.hh:1044
gem5::Flags::isSet
bool isSet(Type mask) const
Verifies whether any bit matching the given mask is set.
Definition: flags.hh:83
gem5::Request::hasSize
bool hasSize() const
Accessor for size.
Definition: request.hh:685
gem5::Request::isHTMStart
bool isHTMStart() const
Definition: request.hh:1031
gem5::MaxAddr
const Addr MaxAddr
Definition: types.hh:171
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:291
gem5::Request::wbRequestorId
@ wbRequestorId
This requestor id is used for writeback requests by the caches.
Definition: request.hh:274
gem5::Request::VALID_EXTRA_DATA
@ VALID_EXTRA_DATA
Whether or not the sc result is valid.
Definition: request.hh:364
gem5::Request::isSwap
bool isSwap() const
Definition: request.hh:1017
gem5::probing::Packet
ProbePointArg< PacketInfo > Packet
Packet probe point.
Definition: mem.hh:109
gem5::Request::VALID_CONTEXT_ID
@ VALID_CONTEXT_ID
Whether or not the context ID is valid.
Definition: request.hh:362
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::Request::substreamId
uint32_t substreamId() const
Definition: request.hh:932
gem5::Request::_systemReq
bool _systemReq
For fullsystem GPU simulation, this determines if a requests destination is system (host) memory or d...
Definition: request.hh:443
gem5::Request::setPaddr
void setPaddr(Addr paddr)
Set just the physical address.
Definition: request.hh:596
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
gem5::Request::_time
Tick _time
The time this request was started.
Definition: request.hh:417
gem5::Request::CacheCoherenceFlagsType
uint64_t CacheCoherenceFlagsType
Definition: request.hh:290
gem5::Request::_cacheCoherenceFlags
CacheCoherenceFlags _cacheCoherenceFlags
Flags that control how downstream cache system maintains coherence.
Definition: request.hh:407
gem5::Request::isAcquire
bool isAcquire() const
Definition: request.hh:1072
gem5::context_switch_task_id::NumTaskId
@ NumTaskId
Definition: request.hh:86
gem5::MipsISA::be
Bitfield< 15 > be
Definition: pra_constants.hh:223
gem5::Request::setExtraData
void setExtraData(uint64_t extraData)
Accessor function for store conditional return value.
Definition: request.hh:888
gem5::Request::isAtomicReturn
bool isAtomicReturn() const
Definition: request.hh:1028
gem5::Request::getAccessDepth
int getAccessDepth() const
Definition: request.hh:964
gem5::Request::isCacheMaintenance
bool isCacheMaintenance() const
Definition: request.hh:1101
gem5::Request::TLBI_EXT_SYNC_COMP
@ TLBI_EXT_SYNC_COMP
The Request tells the interconnect that a remote TLB Sync request has completed.
Definition: request.hh:252
gem5::Request::isInstFetch
bool isInstFetch() const
Definition: request.hh:1007
gem5::Request::isLLSC
bool isLLSC() const
Definition: request.hh:1014
gem5::HtmFailureFaultCause::INVALID
@ INVALID
compiler.hh
flags
uint8_t flags
Definition: helpers.cc:66
gem5::Request::hasSubstreamId
bool hasSubstreamId() const
Definition: request.hh:926
gem5::Request::VALID_SUBSTREAM_ID
@ VALID_SUBSTREAM_ID
Definition: request.hh:367
gem5::Request::hasPaddr
bool hasPaddr() const
Accessor for paddr.
Definition: request.hh:631
gem5::Request::setSubstreamId
void setSubstreamId(uint32_t ssid)
Definition: request.hh:559
gem5::Request::isTlbiSync
bool isTlbiSync() const
Definition: request.hh:1043
gem5::Request::LLSC
@ LLSC
The request is a Load locked/store conditional.
Definition: request.hh:156
gem5::Request::setContext
void setContext(ContextID context_id)
Set up Context numbers.
Definition: request.hh:545
gem5::Request::GL2_CACHE_INV
@ GL2_CACHE_INV
Definition: request.hh:330
gem5::Request::_substreamId
uint32_t _substreamId
The substream ID identifies an "execution context" within a device behind an SMMU/IOMMU.
Definition: request.hh:437
gem5::Request::HTM_START
@ HTM_START
hardware transactional memory
Definition: request.hh:207
gem5::Request::isGL2CacheFlush
bool isGL2CacheFlush() const
Definition: request.hh:1082
gem5::Request::isHTMCmd
bool isHTMCmd() const
Definition: request.hh:1036
gem5::Request::VALID_HTM_ABORT_CAUSE
@ VALID_HTM_ABORT_CAUSE
Whether or not the abort cause is valid.
Definition: request.hh:370
gem5::Request::isCacheInvalidate
bool isCacheInvalidate() const
Definition: request.hh:1100
gem5::Request::_htmAbortCause
HtmFailureFaultCause _htmAbortCause
The cause for HTM transaction abort.
Definition: request.hh:471
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::Request::isKernel
bool isKernel() const
Definition: request.hh:1027
gem5::Request::VALID_INST_COUNT
@ VALID_INST_COUNT
Whether or not the instruction count is valid.
Definition: request.hh:372
gem5::Request::setFlags
void setFlags(Flags flags)
Note that unlike other accessors, this function sets specific flags (ORs them in); it does not assign...
Definition: request.hh:796
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::Request::getByteEnable
const std::vector< bool > & getByteEnable() const
Definition: request.hh:698
gem5::Request::CacheCoherenceFlags
gem5::Flags< CacheCoherenceFlagsType > CacheCoherenceFlags
Definition: request.hh:291
gem5::Request::requestorId
RequestorID requestorId() const
Accesssor for the requestor id.
Definition: request.hh:841
gem5::context_switch_task_id::DMA
@ DMA
Definition: request.hh:84
gem5::Request::PREFETCH
@ PREFETCH
The request is a prefetch.
Definition: request.hh:164
flags.hh
gem5::Request::PrivateFlagsType
uint16_t PrivateFlagsType
Definition: request.hh:346
gem5::Request::isTlbiExtSyncComp
bool isTlbiExtSyncComp() const
Definition: request.hh:1045
gem5::Request::_reqInstSeqNum
InstSeqNum _reqInstSeqNum
Sequence number of the instruction that creates the request.
Definition: request.hh:460
gem5::Request::localAccessor
Cycles localAccessor(ThreadContext *tc, Packet *pkt)
Perform the installed local access.
Definition: request.hh:738
gem5::Request::funcRequestorId
@ funcRequestorId
This requestor id is used for functional requests that don't come from a particular device.
Definition: request.hh:279
gem5::Request::isHTMCancel
bool isHTMCancel() const
Definition: request.hh:1033
gem5::Request::isLockedRMW
bool isLockedRMW() const
Definition: request.hh:1016
gem5::Request::STRICT_ORDER
@ STRICT_ORDER
The request is required to be strictly ordered by CPU models and is non-speculative.
Definition: request.hh:135
gem5::Request::setVirt
void setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc, AtomicOpFunctorPtr amo_op=nullptr)
Set up a virtual (e.g., CPU) request in a previously allocated Request object.
Definition: request.hh:571
gem5::Request::STORE_NO_DATA
static const FlagsType STORE_NO_DATA
Definition: request.hh:260
gem5::Request::ArchFlagsType
uint8_t ArchFlagsType
Definition: request.hh:101
gem5::Request::RELEASE
@ RELEASE
The request should be marked with RELEASE.
Definition: request.hh:172
gem5::context_switch_task_id::Unknown
@ Unknown
Definition: request.hh:85
gem5::Request::DST_POU
@ DST_POU
The request targets the point of unification.
Definition: request.hh:196
gem5::Request::STICKY_FLAGS
@ STICKY_FLAGS
These flags are not cleared when a Request object is reused (assigned a new address).
Definition: request.hh:258
gem5::Request::atomicOpFunctor
AtomicOpFunctorPtr atomicOpFunctor
A pointer to an atomic operation.
Definition: request.hh:463
gem5::Request::FLUSH_L2
@ FLUSH_L2
Definition: request.hh:329
gem5::Request::contextId
ContextID contextId() const
Accessor function for context ID.
Definition: request.hh:902
gem5::Request::VALID_SIZE
@ VALID_SIZE
Whether or not the size is valid.
Definition: request.hh:352
gem5::Request::DST_BITS
@ DST_BITS
Bits to define the destination of a request.
Definition: request.hh:202
gem5::Request::PRIVILEGED
@ PRIVILEGED
This request is made in privileged mode.
Definition: request.hh:137
gem5::context_switch_task_id::MaxNormalTaskId
@ MaxNormalTaskId
Definition: request.hh:82
gem5::Request::setByteEnable
void setByteEnable(const std::vector< bool > &be)
Definition: request.hh:704
gem5::Request::SHARED
@ SHARED
Definition: request.hh:338
gem5::Request::hasContextId
bool hasContextId() const
Definition: request.hh:895
gem5::Request::hasInstCount
bool hasInstCount() const
Accessor for instruction count.
Definition: request.hh:647
gem5::Request::VALID_VADDR
@ VALID_VADDR
Whether or not the vaddr is valid.
Definition: request.hh:356
types.hh
gem5::Request
Definition: request.hh:97
gem5::Request::EVICT_NEXT
@ EVICT_NEXT
The request should be marked as LRU.
Definition: request.hh:168
gem5::Request::PF_EXCLUSIVE
@ PF_EXCLUSIVE
The request should be prefetched into the exclusive state.
Definition: request.hh:166
gem5::Request::invldRequestorId
@ invldRequestorId
Invalid requestor id for assertion checking only.
Definition: request.hh:286
gem5::Request::setTranslateLatency
void setTranslateLatency()
Set/Get the time taken for this request to be successfully translated.
Definition: request.hh:969
gem5::Request::_streamId
uint32_t _streamId
The stream ID uniquely identifies a device behind the SMMU/IOMMU Each transaction arriving at the SMM...
Definition: request.hh:429
gem5::Request::I_CACHE_INV
@ I_CACHE_INV
mem_sync_op flags
Definition: request.hh:323
gem5::Request::GLC_BIT
@ GLC_BIT
Definition: request.hh:334
gem5::ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:239
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::Request::GL1_CACHE_INV
@ GL1_CACHE_INV
Definition: request.hh:327
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::Request::isCacheClean
bool isCacheClean() const
Accessor functions to determine whether this request is part of a cache maintenance operation.
Definition: request.hh:1099
gem5::Request::getAtomicOpFunctor
AtomicOpFunctor * getAtomicOpFunctor()
Definition: request.hh:753
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:251
gem5::Request::taskId
void taskId(uint32_t id)
Definition: request.hh:859
gem5::Request::VALID_PADDR
@ VALID_PADDR
Whether or not paddr is valid (has been written yet).
Definition: request.hh:354
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::Request::hasPC
bool hasPC() const
Definition: request.hh:946
gem5::Request::PT_WALK
@ PT_WALK
The request is a page table walk.
Definition: request.hh:188
gem5::Request::time
Tick time() const
Accessor for time.
Definition: request.hh:726
gem5::Request::STICKY_PRIVATE_FLAGS
@ STICKY_PRIVATE_FLAGS
These flags are not cleared when a Request object is reused (assigned a new address).
Definition: request.hh:377
gem5::Request::_byteEnable
std::vector< bool > _byteEnable
Byte-enable mask for writes.
Definition: request.hh:396
gem5::Request::_contextId
ContextID _contextId
The context ID (for statistics, locks, and wakeups).
Definition: request.hh:454
gem5::Request::clearFlags
void clearFlags(Flags flags)
Definition: request.hh:803
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::Request::_vaddr
Addr _vaddr
The virtual address of the request.
Definition: request.hh:446
gem5::Request::getVaddr
Addr getVaddr() const
Definition: request.hh:833
gem5::Request::TLBI
@ TLBI
The Request is a TLB shootdown.
Definition: request.hh:241
gem5::Request::incAccessDepth
void incAccessDepth() const
Increment/Get the depth at which this request is responded to.
Definition: request.hh:963
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::Request::getTranslateLatency
Tick getTranslateLatency() const
Definition: request.hh:970
gem5::Request::isCondSwap
bool isCondSwap() const
Definition: request.hh:1018
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::Request::INV_L1
@ INV_L1
Definition: request.hh:324
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::Request::requestorId
void requestorId(RequestorID rid)
Definition: request.hh:847
gem5::Request::isMasked
bool isMasked() const
Returns true if the memory request is masked, which means there is at least one byteEnable element wh...
Definition: request.hh:716
gem5::Request::translateDelta
Tick translateDelta
Time for the TLB/table walker to successfully translate this request.
Definition: request.hh:667
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::Request::isToPOC
bool isToPOC() const
Definition: request.hh:1069
gem5::Request::Request
Request(Addr paddr, unsigned size, Flags flags, RequestorID id)
Constructor for physical (e.g.
Definition: request.hh:487
gem5::Request::isLocalAccess
bool isLocalAccess()
Is this request for a local memory mapped resource/register?
Definition: request.hh:733
gem5::Request::isToPOU
bool isToPOU() const
Accessor functions for the destination of a memory request.
Definition: request.hh:1068
gem5::Request::setInstCount
void setInstCount(Counter val)
Definition: request.hh:658
gem5::Request::depth
int depth
Level of the cache hierachy where this request was responded to (e.g.
Definition: request.hh:679
gem5::Request::extraDataValid
bool extraDataValid() const
Accessor function to check if sc result is valid.
Definition: request.hh:873
gem5::Request::getPC
Addr getPC() const
Accessor function for pc.
Definition: request.hh:953
gem5::Request::setSystemReq
void setSystemReq(bool sysReq)
Definition: request.hh:909
gem5::Request::isTlbiCmd
bool isTlbiCmd() const
Definition: request.hh:1047
gem5::Request::DLC_BIT
@ DLC_BIT
Definition: request.hh:333
gem5::Request::isHTMCommit
bool isHTMCommit() const
Definition: request.hh:1032
gem5::Request::accessDelta
Tick accessDelta
Access latency to complete this memory transaction not including translation time.
Definition: request.hh:673
gem5::Request::setCacheCoherenceFlags
void setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
Definition: request.hh:810

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