request.hh

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/*
 * Copyright (c) 2012-2013,2017-2022 Arm Limited
 * All rights reserved
 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
 
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <functional>
#include <limits>
#include <memory>
#include <vector>
 
#include "base/amo.hh"
#include "base/compiler.hh"
#include "base/extensible.hh"
#include "base/flags.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "mem/htm.hh"
#include "sim/cur_tick.hh"
 
namespace gem5
{
 
namespace context_switch_task_id
{
    enum TaskId
    {
        MaxNormalTaskId = 1021, /* Maximum number of normal tasks */
        Prefetcher = 1022, /* For cache lines brought in by prefetcher */
        DMA = 1023, /* Mostly Table Walker */
        Unknown = 1024,
        NumTaskId
    };
}
 
class Packet;
class Request;
class ThreadContext;
 
typedef std::shared_ptr<Request> RequestPtr;
typedef uint16_t RequestorID;
 
class Request : public Extensible<Request>
{
  public:
    typedef uint64_t FlagsType;
    typedef uint8_t ArchFlagsType;
    typedef gem5::Flags<FlagsType> Flags;
 
    enum : FlagsType
    {
        ARCH_BITS                   = 0x000000FF,
        INST_FETCH                  = 0x00000100,
        PHYSICAL                    = 0x00000200,
        UNCACHEABLE                 = 0x00000400,
        STRICT_ORDER                = 0x00000800,
        PRIVILEGED                  = 0x00008000,
 
        CACHE_BLOCK_ZERO            = 0x00010000,
 
        NO_ACCESS                   = 0x00080000,
        LOCKED_RMW                  = 0x00100000,
        LLSC                        = 0x00200000,
        MEM_SWAP                    = 0x00400000,
        MEM_SWAP_COND               = 0x00800000,
        READ_MODIFY_WRITE           = 0x0020000000000000,
 
        PREFETCH                    = 0x01000000,
        PF_EXCLUSIVE                = 0x02000000,
        EVICT_NEXT                  = 0x04000000,
        ACQUIRE                     = 0x00020000,
        RELEASE                     = 0x00040000,
 
        ATOMIC_RETURN_OP            = 0x40000000,
        ATOMIC_NO_RETURN_OP         = 0x80000000,
 
        KERNEL                      = 0x00001000,
 
        SECURE                      = 0x10000000,
        PT_WALK                     = 0x20000000,
 
        INVALIDATE                  = 0x0000000100000000,
        CLEAN                       = 0x0000000200000000,
 
        DST_POU                     = 0x0000001000000000,
 
        DST_POC                     = 0x0000002000000000,
 
        DST_BITS                    = 0x0000003000000000,
 
        HTM_START                   = 0x0000010000000000,
 
        HTM_COMMIT                  = 0x0000020000000000,
 
        HTM_CANCEL                  = 0x0000040000000000,
 
        HTM_ABORT                   = 0x0000080000000000,
 
        // What is the different between HTM cancel and abort?
        //
        // HTM_CANCEL will originate from a user instruction, e.g.
        // Arm's TCANCEL or x86's XABORT. This is an explicit request
        // to end a transaction and restore from the last checkpoint.
        //
        // HTM_ABORT is an internally generated request used to synchronize
        // a transaction's failure between the core and memory subsystem.
        // If a transaction fails in the core, e.g. because an instruction
        // within the transaction generates an exception, the core will prepare
        // itself to stop fetching/executing more instructions and send an
        // HTM_ABORT to the memory subsystem before restoring the checkpoint.
        // Similarly, the transaction could fail in the memory subsystem and
        // this will be communicated to the core via the Packet object.
        // Once the core notices, it will do the same as the above and send
        // a HTM_ABORT to the memory subsystem.
        // A HTM_CANCEL sent to the memory subsystem will ultimately return
        // to the core which in turn will send a HTM_ABORT.
        //
        // This separation is necessary to ensure the disjoint components
        // of the system work correctly together.
 
        TLBI                        = 0x0000100000000000,
 
        TLBI_SYNC                   = 0x0000200000000000,
 
        TLBI_EXT_SYNC               = 0x0000400000000000,
 
        TLBI_EXT_SYNC_COMP          = 0x0000800000000000,
 
        STICKY_FLAGS = INST_FETCH
    };
    static const FlagsType STORE_NO_DATA = CACHE_BLOCK_ZERO |
        CLEAN | INVALIDATE;
 
    static const FlagsType HTM_CMD = HTM_START | HTM_COMMIT |
        HTM_CANCEL | HTM_ABORT;
 
    static const FlagsType TLBI_CMD = TLBI | TLBI_SYNC |
        TLBI_EXT_SYNC | TLBI_EXT_SYNC_COMP;
 
    enum : RequestorID
    {
        wbRequestorId = 0,
        funcRequestorId = 1,
        intRequestorId = 2,
        invldRequestorId = std::numeric_limits<RequestorID>::max()
    };
    typedef uint64_t CacheCoherenceFlagsType;
    typedef gem5::Flags<CacheCoherenceFlagsType> CacheCoherenceFlags;
 
    enum : CacheCoherenceFlagsType
    {
        I_CACHE_INV             = 0x00000001,
        INV_L1                  = I_CACHE_INV,
        V_CACHE_INV             = 0x00000002,
        K_CACHE_INV             = 0x00000004,
        GL1_CACHE_INV           = 0x00000008,
        K_CACHE_WB              = 0x00000010,
        FLUSH_L2                = 0x00000020,
        GL2_CACHE_INV           = 0x00000040,
        SLC_BIT                 = 0x00000080,
        DLC_BIT                 = 0x00000100,
        GLC_BIT                 = 0x00000200,
        CACHED                  = 0x00000400,
        READ_WRITE              = 0x00000800,
        SHARED                  = 0x00001000,
 
    };
 
    using LocalAccessor =
        std::function<Cycles(ThreadContext *tc, Packet *pkt)>;
 
  private:
    typedef uint16_t PrivateFlagsType;
    typedef gem5::Flags<PrivateFlagsType> PrivateFlags;
 
    enum : PrivateFlagsType
    {
        VALID_SIZE           = 0x00000001,
        VALID_PADDR          = 0x00000002,
        VALID_VADDR          = 0x00000004,
        VALID_INST_SEQ_NUM   = 0x00000008,
        VALID_PC             = 0x00000010,
        VALID_CONTEXT_ID     = 0x00000020,
        VALID_EXTRA_DATA     = 0x00000080,
        VALID_STREAM_ID      = 0x00000100,
        VALID_SUBSTREAM_ID   = 0x00000200,
        // hardware transactional memory
        VALID_HTM_ABORT_CAUSE = 0x00000400,
        VALID_INST_COUNT      = 0x00000800,
        STICKY_PRIVATE_FLAGS = VALID_CONTEXT_ID
    };
 
  private:
 
    Addr _paddr = 0;
 
    unsigned _size = 0;
 
    std::vector<bool> _byteEnable;
 
    RequestorID _requestorId = invldRequestorId;
 
    Flags _flags;
 
    CacheCoherenceFlags _cacheCoherenceFlags;
 
    PrivateFlags privateFlags;
 
    Tick _time = MaxTick;
 
    uint32_t _taskId = context_switch_task_id::Unknown;
 
    uint32_t _streamId = 0;
 
    uint32_t _substreamId = 0;
 
    bool _systemReq = 0;
 
    Addr _vaddr = MaxAddr;
 
    uint64_t _extraData = 0;
 
    ContextID _contextId = InvalidContextID;
 
    Addr _pc = MaxAddr;
 
    InstSeqNum _reqInstSeqNum = 0;
 
    AtomicOpFunctorPtr atomicOpFunctor = nullptr;
 
    LocalAccessor _localAccessor;
 
    Counter _instCount = 0;
 
    HtmFailureFaultCause _htmAbortCause = HtmFailureFaultCause::INVALID;
 
  public:
 
    Request() {}
 
    Request(Addr paddr, unsigned size, Flags flags, RequestorID id) :
        _paddr(paddr), _size(size), _requestorId(id), _time(curTick())
    {
        _flags.set(flags);
        privateFlags.set(VALID_PADDR|VALID_SIZE);
        _byteEnable = std::vector<bool>(size, true);
    }
 
    Request(Addr vaddr, unsigned size, Flags flags,
            RequestorID id, Addr pc, ContextID cid,
            AtomicOpFunctorPtr atomic_op=nullptr)
    {
        setVirt(vaddr, size, flags, id, pc, std::move(atomic_op));
        setContext(cid);
        _byteEnable = std::vector<bool>(size, true);
    }
 
    Request(const Request& other)
        : Extensible<Request>(other),
          _paddr(other._paddr), _size(other._size),
          _byteEnable(other._byteEnable),
          _requestorId(other._requestorId),
          _flags(other._flags),
          _cacheCoherenceFlags(other._cacheCoherenceFlags),
          privateFlags(other.privateFlags),
          _time(other._time),
          _taskId(other._taskId), _vaddr(other._vaddr),
          _extraData(other._extraData), _contextId(other._contextId),
          _pc(other._pc), _reqInstSeqNum(other._reqInstSeqNum),
          _localAccessor(other._localAccessor),
          translateDelta(other.translateDelta),
          accessDelta(other.accessDelta), depth(other.depth)
    {
        atomicOpFunctor.reset(other.atomicOpFunctor ?
                                other.atomicOpFunctor->clone() : nullptr);
    }
 
    ~Request() {}
 
    static RequestPtr
    createMemManagement(Flags flags, RequestorID id)
    {
        auto mgmt_req = std::make_shared<Request>();
        mgmt_req->_flags.set(flags);
        mgmt_req->_requestorId = id;
        mgmt_req->_time = curTick();
 
        assert(mgmt_req->isMemMgmt());
        return mgmt_req;
    }
 
    void
    setContext(ContextID context_id)
    {
        _contextId = context_id;
        privateFlags.set(VALID_CONTEXT_ID);
    }
 
    void
    setStreamId(uint32_t sid)
    {
        _streamId = sid;
        privateFlags.set(VALID_STREAM_ID);
    }
 
    void
    setSubstreamId(uint32_t ssid)
    {
        assert(hasStreamId());
        _substreamId = ssid;
        privateFlags.set(VALID_SUBSTREAM_ID);
    }
 
    void
    setVirt(Addr vaddr, unsigned size, Flags flags, RequestorID id, Addr pc,
            AtomicOpFunctorPtr amo_op=nullptr)
    {
        _vaddr = vaddr;
        _size = size;
        _requestorId = id;
        _pc = pc;
        _time = curTick();
 
        _flags.clear(~STICKY_FLAGS);
        _flags.set(flags);
        privateFlags.clear(~STICKY_PRIVATE_FLAGS);
        privateFlags.set(VALID_VADDR|VALID_SIZE|VALID_PC);
        depth = 0;
        accessDelta = 0;
        translateDelta = 0;
        atomicOpFunctor = std::move(amo_op);
        _localAccessor = nullptr;
    }
 
    void
    setPaddr(Addr paddr)
    {
        _paddr = paddr;
        privateFlags.set(VALID_PADDR);
    }
 
    // TODO: this function is still required by TimingSimpleCPU - should be
    // removed once TimingSimpleCPU will support arbitrarily long multi-line
    // mem. accesses
    void splitOnVaddr(Addr split_addr, RequestPtr &req1, RequestPtr &req2)
    {
        assert(hasVaddr());
        assert(!hasPaddr());
        assert(split_addr > _vaddr && split_addr < _vaddr + _size);
        req1 = std::make_shared<Request>(*this);
        req2 = std::make_shared<Request>(*this);
        req1->_size = split_addr - _vaddr;
        req2->_vaddr = split_addr;
        req2->_size = _size - req1->_size;
        req1->_byteEnable = std::vector<bool>(
            _byteEnable.begin(),
            _byteEnable.begin() + req1->_size);
        req2->_byteEnable = std::vector<bool>(
            _byteEnable.begin() + req1->_size,
            _byteEnable.end());
    }
 
    bool
    hasPaddr() const
    {
        return privateFlags.isSet(VALID_PADDR);
    }
 
    Addr
    getPaddr() const
    {
        assert(hasPaddr());
        return _paddr;
    }
 
    bool
    hasInstCount() const
    {
      return privateFlags.isSet(VALID_INST_COUNT);
    }
 
    Counter getInstCount() const
    {
        assert(hasInstCount());
        return _instCount;
    }
 
    void setInstCount(Counter val)
    {
        privateFlags.set(VALID_INST_COUNT);
        _instCount = val;
    }
 
    Tick translateDelta = 0;
 
    Tick accessDelta = 0;
 
    mutable int depth = 0;
 
    bool
    hasSize() const
    {
        return privateFlags.isSet(VALID_SIZE);
    }
 
    unsigned
    getSize() const
    {
        assert(hasSize());
        return _size;
    }
 
    const std::vector<bool>&
    getByteEnable() const
    {
        return _byteEnable;
    }
 
    void
    setByteEnable(const std::vector<bool>& be)
    {
        assert(be.size() == _size);
        _byteEnable = be;
    }
 
    bool
    isMasked() const
    {
        return std::find(
            _byteEnable.begin(),
            _byteEnable.end(),
            false) != _byteEnable.end();
    }
 
    Tick
    time() const
    {
        assert(hasPaddr() || hasVaddr());
        return _time;
    }
 
    bool isLocalAccess() { return (bool)_localAccessor; }
    void setLocalAccessor(LocalAccessor acc) { _localAccessor = acc; }
    Cycles
    localAccessor(ThreadContext *tc, Packet *pkt)
    {
        return _localAccessor(tc, pkt);
    }
 
    bool
    hasAtomicOpFunctor()
    {
        return (bool)atomicOpFunctor;
    }
 
    AtomicOpFunctor *
    getAtomicOpFunctor()
    {
        assert(atomicOpFunctor);
        return atomicOpFunctor.get();
    }
 
    void
    setAtomicOpFunctor(AtomicOpFunctorPtr amo_op)
    {
        atomicOpFunctor = std::move(amo_op);
    }
 
 
    bool
    hasHtmAbortCause() const
    {
      return privateFlags.isSet(VALID_HTM_ABORT_CAUSE);
    }
 
    HtmFailureFaultCause
    getHtmAbortCause() const
    {
        assert(hasHtmAbortCause());
        return _htmAbortCause;
    }
 
    void
    setHtmAbortCause(HtmFailureFaultCause val)
    {
        assert(isHTMAbort());
        privateFlags.set(VALID_HTM_ABORT_CAUSE);
        _htmAbortCause = val;
    }
 
    Flags
    getFlags()
    {
        assert(hasPaddr() || hasVaddr());
        return _flags;
    }
 
    void
    setFlags(Flags flags)
    {
        assert(hasPaddr() || hasVaddr());
        _flags.set(flags);
    }
 
    void
    clearFlags(Flags flags)
    {
        assert(hasPaddr() || hasVaddr());
        _flags.clear(flags);
    }
 
    void
    setCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
    {
        // TODO: do mem_sync_op requests have valid paddr/vaddr?
        assert(hasPaddr() || hasVaddr());
        _cacheCoherenceFlags.set(extraFlags);
    }
 
    void
    clearCacheCoherenceFlags(CacheCoherenceFlags extraFlags)
    {
        // TODO: do mem_sync_op requests have valid paddr/vaddr?
        assert(hasPaddr() || hasVaddr());
        _cacheCoherenceFlags.clear(extraFlags);
    }
 
    bool
    hasVaddr() const
    {
        return privateFlags.isSet(VALID_VADDR);
    }
 
    Addr
    getVaddr() const
    {
        assert(privateFlags.isSet(VALID_VADDR));
        return _vaddr;
    }
 
    RequestorID
    requestorId() const
    {
        return _requestorId;
    }
 
    void
    requestorId(RequestorID rid)
    {
        _requestorId = rid;
    }
 
    uint32_t
    taskId() const
    {
        return _taskId;
    }
 
    void
    taskId(uint32_t id) {
        _taskId = id;
    }
 
    ArchFlagsType
    getArchFlags() const
    {
        assert(hasPaddr() || hasVaddr());
        return _flags & ARCH_BITS;
    }
 
    bool
    extraDataValid() const
    {
        return privateFlags.isSet(VALID_EXTRA_DATA);
    }
 
    uint64_t
    getExtraData() const
    {
        assert(extraDataValid());
        return _extraData;
    }
 
    void
    setExtraData(uint64_t extraData)
    {
        _extraData = extraData;
        privateFlags.set(VALID_EXTRA_DATA);
    }
 
    bool
    hasContextId() const
    {
        return privateFlags.isSet(VALID_CONTEXT_ID);
    }
 
    ContextID
    contextId() const
    {
        assert(hasContextId());
        return _contextId;
    }
 
    /* For GPU fullsystem mark this request is not to device memory. */
    void setSystemReq(bool sysReq) { _systemReq = sysReq; }
    bool systemReq() const { return _systemReq; }
 
    bool
    hasStreamId() const
    {
      return privateFlags.isSet(VALID_STREAM_ID);
    }
 
    uint32_t
    streamId() const
    {
        assert(hasStreamId());
        return _streamId;
    }
 
    bool
    hasSubstreamId() const
    {
        return privateFlags.isSet(VALID_SUBSTREAM_ID);
    }
 
    uint32_t
    substreamId() const
    {
        assert(hasSubstreamId());
        return _substreamId;
    }
 
    void
    setPC(Addr pc)
    {
        privateFlags.set(VALID_PC);
        _pc = pc;
    }
 
    bool
    hasPC() const
    {
        return privateFlags.isSet(VALID_PC);
    }
 
    Addr
    getPC() const
    {
        assert(hasPC());
        return _pc;
    }
 
    void incAccessDepth() const { depth++; }
    int getAccessDepth() const { return depth; }
 
    void setTranslateLatency() { translateDelta = curTick() - _time; }
    Tick getTranslateLatency() const { return translateDelta; }
 
    void setAccessLatency() { accessDelta = curTick() - _time - translateDelta; }
    Tick getAccessLatency() const { return accessDelta; }
 
    bool
    hasInstSeqNum() const
    {
        return privateFlags.isSet(VALID_INST_SEQ_NUM);
    }
 
    InstSeqNum
    getReqInstSeqNum() const
    {
        assert(hasInstSeqNum());
        return _reqInstSeqNum;
    }
 
    void
    setReqInstSeqNum(const InstSeqNum seq_num)
    {
        privateFlags.set(VALID_INST_SEQ_NUM);
        _reqInstSeqNum = seq_num;
    }
 
    bool isUncacheable() const { return _flags.isSet(UNCACHEABLE); }
    bool isStrictlyOrdered() const { return _flags.isSet(STRICT_ORDER); }
    bool isInstFetch() const { return _flags.isSet(INST_FETCH); }
    bool
    isPrefetch() const
    {
        return (_flags.isSet(PREFETCH | PF_EXCLUSIVE));
    }
    bool isPrefetchEx() const { return _flags.isSet(PF_EXCLUSIVE); }
    bool isLLSC() const { return _flags.isSet(LLSC); }
    bool isPriv() const { return _flags.isSet(PRIVILEGED); }
    bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); }
    bool isSwap() const { return _flags.isSet(MEM_SWAP | MEM_SWAP_COND); }
    bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
    bool
    isReadModifyWrite() const
    {
        return _flags.isSet(LOCKED_RMW | READ_MODIFY_WRITE);
    }
    bool isSecure() const { return _flags.isSet(SECURE); }
    bool isPTWalk() const { return _flags.isSet(PT_WALK); }
    bool isRelease() const { return _flags.isSet(RELEASE); }
    bool isKernel() const { return _flags.isSet(KERNEL); }
    bool isAtomicReturn() const { return _flags.isSet(ATOMIC_RETURN_OP); }
    bool isAtomicNoReturn() const { return _flags.isSet(ATOMIC_NO_RETURN_OP); }
    // hardware transactional memory
    bool isHTMStart() const { return _flags.isSet(HTM_START); }
    bool isHTMCommit() const { return _flags.isSet(HTM_COMMIT); }
    bool isHTMCancel() const { return _flags.isSet(HTM_CANCEL); }
    bool isHTMAbort() const { return _flags.isSet(HTM_ABORT); }
    bool
    isHTMCmd() const
    {
        return (isHTMStart() || isHTMCommit() ||
                isHTMCancel() || isHTMAbort());
    }
 
    bool isTlbi() const { return _flags.isSet(TLBI); }
    bool isTlbiSync() const { return _flags.isSet(TLBI_SYNC); }
    bool isTlbiExtSync() const { return _flags.isSet(TLBI_EXT_SYNC); }
    bool isTlbiExtSyncComp() const { return _flags.isSet(TLBI_EXT_SYNC_COMP); }
    bool
    isTlbiCmd() const
    {
        return (isTlbi() || isTlbiSync() ||
                isTlbiExtSync() || isTlbiExtSyncComp());
    }
    bool isMemMgmt() const { return isTlbiCmd() || isHTMCmd(); }
 
    bool
    isAtomic() const
    {
        return _flags.isSet(ATOMIC_RETURN_OP) ||
               _flags.isSet(ATOMIC_NO_RETURN_OP);
    }
 
    bool isToPOU() const { return _flags.isSet(DST_POU); }
    bool isToPOC() const { return _flags.isSet(DST_POC); }
    Flags getDest() const { return _flags & DST_BITS; }
 
    bool isAcquire() const { return _cacheCoherenceFlags.isSet(ACQUIRE); }
 
 
    bool isGLCSet() const {return _cacheCoherenceFlags.isSet(GLC_BIT); }
    bool isSLCSet() const {return _cacheCoherenceFlags.isSet(SLC_BIT); }
 
    bool isInvL1() const { return _cacheCoherenceFlags.isSet(INV_L1); }
    bool isInvL2() const { return _cacheCoherenceFlags.isSet(GL2_CACHE_INV); }
 
    bool
    isGL2CacheFlush() const
    {
        return _cacheCoherenceFlags.isSet(FLUSH_L2);
    }
 
    bool isCacheClean() const { return _flags.isSet(CLEAN); }
    bool isCacheInvalidate() const { return _flags.isSet(INVALIDATE); }
    bool isCacheMaintenance() const { return _flags.isSet(CLEAN|INVALIDATE); }
};
 
} // namespace gem5
 
#endif // __MEM_REQUEST_HH__