gem5  v21.2.1.1
tlb.hh
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40 
41 #ifndef __ARCH_GENERIC_TLB_HH__
42 #define __ARCH_GENERIC_TLB_HH__
43 
44 #include <type_traits>
45 
46 #include "arch/generic/mmu.hh"
47 #include "base/logging.hh"
48 #include "enums/TypeTLB.hh"
49 #include "mem/request.hh"
50 #include "params/BaseTLB.hh"
51 #include "sim/sim_object.hh"
52 
53 namespace gem5
54 {
55 
56 class ThreadContext;
57 
58 class BaseTLB : public SimObject
59 {
60  protected:
61  BaseTLB(const BaseTLBParams &p)
62  : SimObject(p), _type(p.entry_type), _nextLevel(p.next_level)
63  {}
64 
65  TypeTLB _type;
66 
68 
69  public:
70  virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
71 
72  virtual Fault translateAtomic(
73  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) = 0;
74  virtual void translateTiming(
75  const RequestPtr &req, ThreadContext *tc,
76  BaseMMU::Translation *translation, BaseMMU::Mode mode) = 0;
77  virtual Fault
80  {
81  panic("Not implemented.\n");
82  }
83 
98  virtual Fault finalizePhysical(
99  const RequestPtr &req, ThreadContext *tc,
100  BaseMMU::Mode mode) const = 0;
101 
105  virtual void flushAll() = 0;
106 
110  virtual void takeOverFrom(BaseTLB *otlb) = 0;
111 
121  virtual Port* getTableWalkerPort() { return NULL; }
122 
123  void memInvalidate() { flushAll(); }
124 
125  TypeTLB type() const { return _type; }
126 
127  BaseTLB* nextLevel() const { return _nextLevel; }
128 };
129 
138 inline auto
139 operator&(TypeTLB lhs, TypeTLB rhs)
140 {
141  using T = std::underlying_type_t<TypeTLB>;
142  return static_cast<T>(lhs) & static_cast<T>(rhs);
143 }
144 
145 } // namespace gem5
146 
147 #endif // __ARCH_GENERIC_TLB_HH__
gem5::BaseTLB::takeOverFrom
virtual void takeOverFrom(BaseTLB *otlb)=0
Take over from an old tlb context.
gem5::BaseTLB::nextLevel
BaseTLB * nextLevel() const
Definition: tlb.hh:127
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:56
gem5::BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const =0
Do post-translation physical address finalization.
gem5::BaseTLB::_type
TypeTLB _type
Definition: tlb.hh:65
request.hh
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::BaseTLB::type
TypeTLB type() const
Definition: tlb.hh:125
sim_object.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::BaseTLB::_nextLevel
BaseTLB * _nextLevel
Definition: tlb.hh:67
gem5::BaseTLB::memInvalidate
void memInvalidate()
Invalidate the contents of memory buffers.
Definition: tlb.hh:123
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
mmu.hh
gem5::BaseTLB
Definition: tlb.hh:58
gem5::BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
gem5::operator&
auto operator&(TypeTLB lhs, TypeTLB rhs)
Implementing the "&" bitwise operator for TypeTLB allows us to handle TypeTLB::unified efficiently.
Definition: tlb.hh:139
gem5::BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: tlb.hh:78
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode)=0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseTLB::BaseTLB
BaseTLB(const BaseTLBParams &p)
Definition: tlb.hh:61
gem5::BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::BaseMMU::Translation
Definition: mmu.hh:58
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
logging.hh
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::BaseTLB::getTableWalkerPort
virtual Port * getTableWalkerPort()
Get the table walker port if present.
Definition: tlb.hh:121
gem5::BaseTLB::flushAll
virtual void flushAll()=0
Remove all entries from the TLB.
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:74

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