gem5  v21.1.0.2
tlb.hh
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40 
41 #ifndef __ARCH_GENERIC_TLB_HH__
42 #define __ARCH_GENERIC_TLB_HH__
43 
44 #include "arch/generic/mmu.hh"
45 #include "base/logging.hh"
46 #include "mem/request.hh"
47 #include "sim/sim_object.hh"
48 
49 namespace gem5
50 {
51 
52 class ThreadContext;
53 
54 class BaseTLB : public SimObject
55 {
56  protected:
57  BaseTLB(const Params &p) : SimObject(p) {}
58 
59  public:
60  virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
61 
62  virtual Fault translateAtomic(
63  const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) = 0;
64  virtual void translateTiming(
65  const RequestPtr &req, ThreadContext *tc,
66  BaseMMU::Translation *translation, BaseMMU::Mode mode) = 0;
67  virtual Fault
70  {
71  panic("Not implemented.\n");
72  }
73 
88  virtual Fault finalizePhysical(
89  const RequestPtr &req, ThreadContext *tc,
90  BaseMMU::Mode mode) const = 0;
91 
95  virtual void flushAll() = 0;
96 
100  virtual void takeOverFrom(BaseTLB *otlb) = 0;
101 
111  virtual Port* getTableWalkerPort() { return NULL; }
112 
113  void memInvalidate() { flushAll(); }
114 };
115 
116 } // namespace gem5
117 
118 #endif // __ARCH_GENERIC_TLB_HH__
gem5::BaseTLB::takeOverFrom
virtual void takeOverFrom(BaseTLB *otlb)=0
Take over from an old tlb context.
gem5::BaseMMU::Mode
Mode
Definition: mmu.hh:53
gem5::BaseTLB::finalizePhysical
virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode) const =0
Do post-translation physical address finalization.
request.hh
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::BaseTLB::BaseTLB
BaseTLB(const Params &p)
Definition: tlb.hh:57
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
sim_object.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::BaseTLB::memInvalidate
void memInvalidate()
Invalidate the contents of memory buffers.
Definition: tlb.hh:113
gem5::RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:92
mmu.hh
gem5::BaseTLB
Definition: tlb.hh:54
gem5::BaseTLB::demapPage
virtual void demapPage(Addr vaddr, uint64_t asn)=0
gem5::BaseTLB::translateFunctional
virtual Fault translateFunctional(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)
Definition: tlb.hh:68
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::BaseTLB::translateTiming
virtual void translateTiming(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation *translation, BaseMMU::Mode mode)=0
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::BaseTLB::translateAtomic
virtual Fault translateAtomic(const RequestPtr &req, ThreadContext *tc, BaseMMU::Mode mode)=0
gem5::BaseMMU::Translation
Definition: mmu.hh:55
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
logging.hh
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::BaseTLB::getTableWalkerPort
virtual Port * getTableWalkerPort()
Get the table walker port if present.
Definition: tlb.hh:111
gem5::BaseTLB::flushAll
virtual void flushAll()=0
Remove all entries from the TLB.
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73

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