46 #ifndef __MEM_CACHE_PREFETCH_BASE_HH__
47 #define __MEM_CACHE_PREFETCH_BASE_HH__
66 struct BasePrefetcherParams;
78 const std::string &
name,
bool _isFill =
false,
209 template <
typename T>
211 get(ByteOrder endian)
const
213 if (
data ==
nullptr) {
214 panic(
"PrefetchInfo::get called with a request with no data.");
220 case ByteOrder::little:
224 panic(
"Illegal byte order in PrefetchInfo::get()\n");
371 Base(
const BasePrefetcherParams &
p);
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Definitions of a simple cache block class.
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
virtual std::string name() const
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i....
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
Abstract superclass for simulation objects.
Class containing the information needed by the prefetch to train and generate new prefetch requests.
bool validPC
Validity bit for the PC of this address.
PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
Constructs a PrefetchInfo using a PacketPtr.
Addr getPC() const
Returns the program counter that generated this request.
bool isSecure() const
Returns true if the address targets the secure memory space.
unsigned int getSize() const
Gets the size of the request triggering this event.
Addr getPaddr() const
Gets the physical address of the request.
bool write
Whether this event comes from a write request.
bool isWrite() const
Checks if the request that caused this prefetch event was a write request.
bool isCacheMiss() const
Check if this event comes from a cache miss.
RequestorID requestorId
The requestor ID that generated this address.
Addr address
The address used to train and generate prefetches.
Addr getAddr() const
Obtains the address value of this Prefetcher address.
bool cacheMiss
Whether this event comes from a cache miss.
Addr paddress
Physical address, needed because address can be virtual.
T get(ByteOrder endian) const
Gets the associated data of the request triggering the event.
bool hasPC() const
Returns true if the associated program counter is valid.
Addr pc
The program counter that generated this address.
unsigned int size
Size in bytes of the request triggering this event.
uint8_t * data
Pointer to the associated request data.
RequestorID getRequestorId() const
Gets the requestor ID that generated this address.
bool secure
Whether this address targets the secure memory space.
bool sameAddr(PrefetchInfo const &pfi) const
Check for equality.
void notify(const PacketPtr &pkt) override
PrefetchListener(Base &_parent, ProbeManager *pm, const std::string &name, bool _isFill=false, bool _miss=false)
Base(const BasePrefetcherParams &p)
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
void addTLB(BaseTLB *tlb)
Add a BaseTLB object to be used whenever a translation is needed.
const bool prefetchOnAccess
Prefetch on every access, not just misses.
const bool onRead
Consult prefetcher on reads?
unsigned blkSize
The block size of the parent cache.
uint64_t issuedPrefetches
Total prefetches issued.
bool observeAccess(const PacketPtr &pkt, bool miss) const
Determine if this access should be observed.
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
void incrDemandMhsrMisses()
void addEventProbe(SimObject *obj, const char *name)
Add a SimObject and a probe name to listen events from.
const RequestorID requestorId
Request id for prefetches.
std::vector< PrefetchListener * > listeners
BaseTLB * tlb
Registered tlb for address translations.
void regProbeListeners() override
Register probe points for this object.
Addr pageAddress(Addr a) const
Determine the address of the page in which a lays.
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
bool hasBeenPrefetched(Addr addr, bool is_secure) const
const bool onInst
Consult prefetcher on instruction accesses?
uint64_t usefulPrefetches
Total prefetches that has been useful.
gem5::prefetch::Base::StatGroup prefetchStats
Addr pageIthBlockAddress(Addr page, uint32_t i) const
Build the address of the i-th block inside the page.
BaseCache * cache
Pointr to the parent cache.
Addr pageOffset(Addr a) const
Determine the page-offset of a
virtual PacketPtr getPacket()=0
virtual void setCache(BaseCache *_cache)
const bool onData
Consult prefetcher on data accesses?
const bool prefetchOnPfHit
Prefetch on hit on prefetched lines.
void probeNotify(const PacketPtr &pkt, bool miss)
Process a notification event from the ProbeListener.
virtual void notifyFill(const PacketPtr &pkt)
Notify prefetcher of cache fill.
const bool onWrite
Consult prefetcher on reads?
virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi)=0
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....
unsigned lBlkSize
log_2(block size of the parent cache).
Addr blockIndex(Addr a) const
Determine the address of a at block granularity.
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
const bool onMiss
Only consult prefetcher on cache misses?
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
virtual Tick nextPrefetchReadyTime() const =0
This is a simple scalar statistic, like a counter.
ClockedObject declaration and implementation.
#define panic(...)
This implements a cprintf based panic() function.
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
uint64_t Tick
Tick count type.
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
Declaration of the Packet class.
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
Declaration of Statistics objects.
statistics::Formula accuracy
statistics::Scalar pfUsefulButMiss
The number of times there is a hit on prefetch but cache block is not in an usable state.
statistics::Scalar pfIssued
statistics::Scalar pfUseful
The number of times a HW-prefetch is useful.
statistics::Scalar pfHitInWB
The number of times a HW-prefetch hits in the Write Buffer (WB).
statistics::Scalar pfHitInMSHR
The number of times a HW-prefetch hits in a MSHR.
statistics::Formula pfLate
The number of times a HW-prefetch is late (hit in cache, MSHR, WB).
statistics::Scalar pfUnused
The number of times a HW-prefetched block is evicted w/o reference.
statistics::Scalar pfHitInCache
The number of times a HW-prefetch hits in cache.
statistics::Scalar demandMshrMisses
StatGroup(statistics::Group *parent)
statistics::Formula coverage