gem5  v21.2.0.0
base.hh
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40 
46 #ifndef __MEM_CACHE_PREFETCH_BASE_HH__
47 #define __MEM_CACHE_PREFETCH_BASE_HH__
48 
49 #include <cstdint>
50 
51 #include "arch/generic/tlb.hh"
52 #include "base/compiler.hh"
53 #include "base/statistics.hh"
54 #include "base/types.hh"
55 #include "mem/cache/cache_blk.hh"
56 #include "mem/packet.hh"
57 #include "mem/request.hh"
58 #include "sim/byteswap.hh"
59 #include "sim/clocked_object.hh"
60 #include "sim/probe/probe.hh"
61 
62 namespace gem5
63 {
64 
65 class BaseCache;
66 struct BasePrefetcherParams;
67 
69 namespace prefetch
70 {
71 
72 class Base : public ClockedObject
73 {
74  class PrefetchListener : public ProbeListenerArgBase<PacketPtr>
75  {
76  public:
78  const std::string &name, bool _isFill = false,
79  bool _miss = false)
81  parent(_parent), isFill(_isFill), miss(_miss) {}
82  void notify(const PacketPtr &pkt) override;
83  protected:
85  const bool isFill;
86  const bool miss;
87  };
88 
90 
91  public:
92 
98  {
106  bool validPC;
108  bool secure;
110  unsigned int size;
112  bool write;
116  bool cacheMiss;
118  uint8_t *data;
119 
120  public:
125  Addr getAddr() const
126  {
127  return address;
128  }
129 
134  bool isSecure() const
135  {
136  return secure;
137  }
138 
143  Addr getPC() const
144  {
145  assert(hasPC());
146  return pc;
147  }
148 
153  bool hasPC() const
154  {
155  return validPC;
156  }
157 
163  {
164  return requestorId;
165  }
166 
171  unsigned int getSize() const
172  {
173  return size;
174  }
175 
181  bool isWrite() const
182  {
183  return write;
184  }
185 
190  Addr getPaddr() const
191  {
192  return paddress;
193  }
194 
199  bool isCacheMiss() const
200  {
201  return cacheMiss;
202  }
203 
209  template <typename T>
210  inline T
211  get(ByteOrder endian) const
212  {
213  if (data == nullptr) {
214  panic("PrefetchInfo::get called with a request with no data.");
215  }
216  switch (endian) {
217  case ByteOrder::big:
218  return betoh(*(T*)data);
219 
220  case ByteOrder::little:
221  return letoh(*(T*)data);
222 
223  default:
224  panic("Illegal byte order in PrefetchInfo::get()\n");
225  };
226  }
227 
233  bool sameAddr(PrefetchInfo const &pfi) const
234  {
235  return this->getAddr() == pfi.getAddr() &&
236  this->isSecure() == pfi.isSecure();
237  }
238 
246  PrefetchInfo(PacketPtr pkt, Addr addr, bool miss);
247 
254  PrefetchInfo(PrefetchInfo const &pfi, Addr addr);
255 
257  {
258  delete[] data;
259  }
260  };
261 
262  protected:
263 
264  // PARAMETERS
265 
268 
270  unsigned blkSize;
271 
273  unsigned lBlkSize;
274 
276  const bool onMiss;
277 
279  const bool onRead;
280 
282  const bool onWrite;
283 
285  const bool onData;
286 
288  const bool onInst;
289 
292 
294 
296  const bool prefetchOnAccess;
297 
299  const bool prefetchOnPfHit;
300 
303 
309  bool observeAccess(const PacketPtr &pkt, bool miss) const;
310 
312  bool inCache(Addr addr, bool is_secure) const;
313 
315  bool inMissQueue(Addr addr, bool is_secure) const;
316 
317  bool hasBeenPrefetched(Addr addr, bool is_secure) const;
318 
320  bool samePage(Addr a, Addr b) const;
322  Addr blockAddress(Addr a) const;
324  Addr blockIndex(Addr a) const;
326  Addr pageAddress(Addr a) const;
328  Addr pageOffset(Addr a) const;
330  Addr pageIthBlockAddress(Addr page, uint32_t i) const;
331  struct StatGroup : public statistics::Group
332  {
333  StatGroup(statistics::Group *parent);
346 
349 
352 
356 
360  } prefetchStats;
361 
366 
369 
370  public:
371  Base(const BasePrefetcherParams &p);
372  virtual ~Base() = default;
373 
374  virtual void setCache(BaseCache *_cache);
375 
380  virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi) = 0;
381 
383  virtual void notifyFill(const PacketPtr &pkt)
384  {}
385 
386  virtual PacketPtr getPacket() = 0;
387 
388  virtual Tick nextPrefetchReadyTime() const = 0;
389 
390  void
392  {
394  }
395 
396  void
398  {
400  }
401 
402  void
404  {
406  }
407 
408  void
410  {
412  }
413 
414  void
416  {
418  }
419 
423  void regProbeListeners() override;
424 
430  void probeNotify(const PacketPtr &pkt, bool miss);
431 
437  void addEventProbe(SimObject *obj, const char *name);
438 
445  void addTLB(BaseTLB *tlb);
446 };
447 
448 } // namespace prefetch
449 } // namespace gem5
450 
451 #endif //__MEM_CACHE_PREFETCH_BASE_HH__
gem5::prefetch::Base::PrefetchInfo::getAddr
Addr getAddr() const
Obtains the address value of this Prefetcher address.
Definition: base.hh:125
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::prefetch::Base::StatGroup::demandMshrMisses
statistics::Scalar demandMshrMisses
Definition: base.hh:334
gem5::prefetch::Base::prefetchOnAccess
const bool prefetchOnAccess
Prefetch on every access, not just misses.
Definition: base.hh:296
gem5::prefetch::Base::StatGroup::pfUsefulButMiss
statistics::Scalar pfUsefulButMiss
The number of times there is a hit on prefetch but cache block is not in an usable state.
Definition: base.hh:343
gem5::prefetch::Base::blockIndex
Addr blockIndex(Addr a) const
Determine the address of a at block granularity.
Definition: base.cc:219
gem5::prefetch::Base::useVirtualAddresses
const bool useVirtualAddresses
Use Virtual Addresses for prefetching.
Definition: base.hh:302
gem5::prefetch::Base::~Base
virtual ~Base()=default
gem5::prefetch::Base::pageOffset
Addr pageOffset(Addr a) const
Determine the page-offset of a
Definition: base.cc:231
gem5::prefetch::Base::hasBeenPrefetched
bool hasBeenPrefetched(Addr addr, bool is_secure) const
Definition: base.cc:201
gem5::prefetch::Base::PrefetchInfo::write
bool write
Whether this event comes from a write request.
Definition: base.hh:112
gem5::prefetch::Base::StatGroup::StatGroup
StatGroup(statistics::Group *parent)
Definition: base.cc:121
gem5::prefetch::Base::setCache
virtual void setCache(BaseCache *_cache)
Definition: base.cc:111
gem5::prefetch::Base::PrefetchInfo::address
Addr address
The address used to train and generate prefetches.
Definition: base.hh:100
gem5::prefetch::Base::PrefetchInfo::isSecure
bool isSecure() const
Returns true if the address targets the secure memory space.
Definition: base.hh:134
gem5::prefetch::Base::StatGroup::pfIssued
statistics::Scalar pfIssued
Definition: base.hh:335
gem5::prefetch::Base::PrefetchInfo::data
uint8_t * data
Pointer to the associated request data.
Definition: base.hh:118
gem5::prefetch::Base::addEventProbe
void addEventProbe(SimObject *obj, const char *name)
Add a SimObject and a probe name to listen events from.
Definition: base.cc:295
gem5::prefetch::Base::listeners
std::vector< PrefetchListener * > listeners
Definition: base.hh:89
tlb.hh
gem5::betoh
T betoh(T value)
Definition: byteswap.hh:175
gem5::prefetch::Base::prefetchUnused
void prefetchUnused()
Definition: base.hh:391
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:66
gem5::prefetch::Base::PrefetchInfo::sameAddr
bool sameAddr(PrefetchInfo const &pfi) const
Check for equality.
Definition: base.hh:233
gem5::prefetch::Base::PrefetchInfo::pc
Addr pc
The program counter that generated this address.
Definition: base.hh:102
gem5::prefetch::Base::pageAddress
Addr pageAddress(Addr a) const
Determine the address of the page in which a lays.
Definition: base.cc:225
gem5::prefetch::Base::inMissQueue
bool inMissQueue(Addr addr, bool is_secure) const
Determine if address is in cache miss queue.
Definition: base.cc:195
gem5::prefetch::Base::PrefetchInfo::isCacheMiss
bool isCacheMiss() const
Check if this event comes from a cache miss.
Definition: base.hh:199
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector
STL vector class.
Definition: stl.hh:37
gem5::prefetch::Base::Base
Base(const BasePrefetcherParams &p)
Definition: base.cc:96
gem5::prefetch::Base::blockAddress
Addr blockAddress(Addr a) const
Determine the address of the block in which a lays.
Definition: base.cc:213
gem5::prefetch::Base::notifyFill
virtual void notifyFill(const PacketPtr &pkt)
Notify prefetcher of cache fill.
Definition: base.hh:383
gem5::prefetch::Base::PrefetchInfo::get
T get(ByteOrder endian) const
Gets the associated data of the request triggering the event.
Definition: base.hh:211
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::prefetch::Base::requestorId
const RequestorID requestorId
Request id for prefetches.
Definition: base.hh:291
gem5::prefetch::Base::PrefetchInfo::size
unsigned int size
Size in bytes of the request triggering this event.
Definition: base.hh:110
gem5::prefetch::Base::PrefetchInfo::getPaddr
Addr getPaddr() const
Gets the physical address of the request.
Definition: base.hh:190
gem5::prefetch::Base::PrefetchListener::miss
const bool miss
Definition: base.hh:86
gem5::prefetch::Base::onRead
const bool onRead
Consult prefetcher on reads?
Definition: base.hh:279
gem5::prefetch::Base::PrefetchInfo::getRequestorId
RequestorID getRequestorId() const
Gets the requestor ID that generated this address.
Definition: base.hh:162
request.hh
gem5::prefetch::Base::PrefetchInfo::validPC
bool validPC
Validity bit for the PC of this address.
Definition: base.hh:106
gem5::prefetch::Base::PrefetchListener::isFill
const bool isFill
Definition: base.hh:85
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
packet.hh
gem5::prefetch::Base::StatGroup::pfHitInWB
statistics::Scalar pfHitInWB
The number of times a HW-prefetch hits in the Write Buffer (WB).
Definition: base.hh:355
gem5::prefetch::Base::observeAccess
bool observeAccess(const PacketPtr &pkt, bool miss) const
Determine if this access should be observed.
Definition: base.cc:161
gem5::prefetch::Base::onInst
const bool onInst
Consult prefetcher on instruction accesses?
Definition: base.hh:288
gem5::prefetch::Base::PrefetchListener::parent
Base & parent
Definition: base.hh:84
gem5::prefetch::Base::PrefetchInfo::getPC
Addr getPC() const
Returns the program counter that generated this request.
Definition: base.hh:143
gem5::prefetch::Base::StatGroup::pfUnused
statistics::Scalar pfUnused
The number of times a HW-prefetched block is evicted w/o reference.
Definition: base.hh:338
gem5::prefetch::Base::samePage
bool samePage(Addr a, Addr b) const
Determine if addresses are on the same page.
Definition: base.cc:207
gem5::prefetch::Base::PrefetchInfo::requestorId
RequestorID requestorId
The requestor ID that generated this address.
Definition: base.hh:104
gem5::prefetch::Base::onMiss
const bool onMiss
Only consult prefetcher on cache misses?
Definition: base.hh:276
gem5::ArmISA::b
Bitfield< 7 > b
Definition: misc_types.hh:382
gem5::prefetch::Base::pageBytes
const Addr pageBytes
Definition: base.hh:293
gem5::prefetch::Base::pfHitInMSHR
void pfHitInMSHR()
Definition: base.hh:409
gem5::Named::name
virtual std::string name() const
Definition: named.hh:47
gem5::BaseCache
A basic cache interface.
Definition: base.hh:95
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::prefetch::Base::usefulPrefetches
uint64_t usefulPrefetches
Total prefetches that has been useful.
Definition: base.hh:365
gem5::prefetch::Base::PrefetchInfo::PrefetchInfo
PrefetchInfo(PacketPtr pkt, Addr addr, bool miss)
Constructs a PrefetchInfo using a PacketPtr.
Definition: base.cc:62
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
statistics.hh
gem5::prefetch::Base::StatGroup::pfLate
statistics::Formula pfLate
The number of times a HW-prefetch is late (hit in cache, MSHR, WB).
Definition: base.hh:359
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::BaseTLB
Definition: tlb.hh:58
gem5::prefetch::Base::probeNotify
void probeNotify(const PacketPtr &pkt, bool miss)
Process a notification event from the ProbeListener.
Definition: base.cc:243
gem5::prefetch::Base::onData
const bool onData
Consult prefetcher on data accesses?
Definition: base.hh:285
compiler.hh
gem5::prefetch::Base::PrefetchInfo::paddress
Addr paddress
Physical address, needed because address can be virtual.
Definition: base.hh:114
gem5::prefetch::Base::StatGroup::coverage
statistics::Formula coverage
Definition: base.hh:345
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::prefetch::Base::PrefetchListener::PrefetchListener
PrefetchListener(Base &_parent, ProbeManager *pm, const std::string &name, bool _isFill=false, bool _miss=false)
Definition: base.hh:77
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::prefetch::Base::PrefetchInfo::~PrefetchInfo
~PrefetchInfo()
Definition: base.hh:256
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
gem5::prefetch::Base::pfHitInWB
void pfHitInWB()
Definition: base.hh:415
gem5::prefetch::Base::pfHitInCache
void pfHitInCache()
Definition: base.hh:403
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::prefetch::Base::PrefetchInfo::isWrite
bool isWrite() const
Checks if the request that caused this prefetch event was a write request.
Definition: base.hh:181
gem5::prefetch::Base::nextPrefetchReadyTime
virtual Tick nextPrefetchReadyTime() const =0
gem5::ProbeManager
ProbeManager is a conduit class that lives on each SimObject, and is used to match up probe listeners...
Definition: probe.hh:163
gem5::prefetch::Base::PrefetchInfo::getSize
unsigned int getSize() const
Gets the size of the request triggering this event.
Definition: base.hh:171
gem5::prefetch::Base::PrefetchInfo::cacheMiss
bool cacheMiss
Whether this event comes from a cache miss.
Definition: base.hh:116
gem5::prefetch::Base::PrefetchInfo::secure
bool secure
Whether this address targets the secure memory space.
Definition: base.hh:108
gem5::prefetch::Base::prefetchStats
gem5::prefetch::Base::StatGroup prefetchStats
gem5::prefetch::Base::PrefetchListener::notify
void notify(const PacketPtr &pkt) override
Definition: base.cc:87
gem5::prefetch::Base::issuedPrefetches
uint64_t issuedPrefetches
Total prefetches issued.
Definition: base.hh:363
gem5::prefetch::Base::StatGroup
Definition: base.hh:331
gem5::prefetch::Base::lBlkSize
unsigned lBlkSize
log_2(block size of the parent cache).
Definition: base.hh:273
cache_blk.hh
gem5::prefetch::Base::regProbeListeners
void regProbeListeners() override
Register probe points for this object.
Definition: base.cc:276
gem5::ProbeListenerArgBase
ProbeListenerArgBase is used to define the base interface to a ProbeListenerArg (i....
Definition: probe.hh:211
types.hh
gem5::prefetch::Base::StatGroup::pfUseful
statistics::Scalar pfUseful
The number of times a HW-prefetch is useful.
Definition: base.hh:340
clocked_object.hh
gem5::prefetch::Base::StatGroup::accuracy
statistics::Formula accuracy
Definition: base.hh:344
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::prefetch::Base::cache
BaseCache * cache
Pointr to the parent cache.
Definition: base.hh:267
gem5::prefetch::Base::prefetchOnPfHit
const bool prefetchOnPfHit
Prefetch on hit on prefetched lines.
Definition: base.hh:299
gem5::prefetch::Base::incrDemandMhsrMisses
void incrDemandMhsrMisses()
Definition: base.hh:397
gem5::ProbeListener::name
const std::string name
Definition: probe.hh:138
gem5::prefetch::Base::blkSize
unsigned blkSize
The block size of the parent cache.
Definition: base.hh:270
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::prefetch::Base::tlb
BaseTLB * tlb
Registered tlb for address translations.
Definition: base.hh:368
gem5::context_switch_task_id::Prefetcher
@ Prefetcher
Definition: request.hh:83
gem5::prefetch::Base::inCache
bool inCache(Addr addr, bool is_secure) const
Determine if address is in cache.
Definition: base.cc:189
gem5::prefetch::Base::pageIthBlockAddress
Addr pageIthBlockAddress(Addr page, uint32_t i) const
Build the address of the i-th block inside the page.
Definition: base.cc:237
probe.hh
gem5::prefetch::Base::getPacket
virtual PacketPtr getPacket()=0
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::prefetch::Base::StatGroup::pfHitInMSHR
statistics::Scalar pfHitInMSHR
The number of times a HW-prefetch hits in a MSHR.
Definition: base.hh:351
gem5::prefetch::Base
Definition: base.hh:72
gem5::prefetch::Base::PrefetchInfo
Class containing the information needed by the prefetch to train and generate new prefetch requests.
Definition: base.hh:97
gem5::prefetch::Base::onWrite
const bool onWrite
Consult prefetcher on reads?
Definition: base.hh:282
gem5::prefetch::Base::StatGroup::pfHitInCache
statistics::Scalar pfHitInCache
The number of times a HW-prefetch hits in cache.
Definition: base.hh:348
byteswap.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::prefetch::Base::addTLB
void addTLB(BaseTLB *tlb)
Add a BaseTLB object to be used whenever a translation is needed.
Definition: base.cc:302
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::prefetch::Base::PrefetchInfo::hasPC
bool hasPC() const
Returns true if the associated program counter is valid.
Definition: base.hh:153
gem5::prefetch::Base::PrefetchListener
Definition: base.hh:74
gem5::prefetch::Base::notify
virtual void notify(const PacketPtr &pkt, const PrefetchInfo &pfi)=0
Notify prefetcher of cache access (may be any access or just misses, depending on cache parameters....

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