interrupts.cc File Reference

#include "arch/mips/interrupts.hh"
#include "arch/mips/pra_constants.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Interrupt.hh"

Go to the source code of this file.

Namespaces
namespace	gem5
	Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
namespace	gem5::MipsISA

Enumerations
enum	gem5::MipsISA::InterruptLevels {   gem5::MipsISA::INTLEVEL_SOFTWARE_MIN = 4 , gem5::MipsISA::INTLEVEL_SOFTWARE_MAX = 19 , gem5::MipsISA::INTLEVEL_EXTERNAL_MIN = 20 , gem5::MipsISA::INTLEVEL_EXTERNAL_MAX = 34 ,   gem5::MipsISA::INTLEVEL_IRQ0 = 20 , gem5::MipsISA::INTLEVEL_IRQ1 = 21 , gem5::MipsISA::INTINDEX_ETHERNET = 0 , gem5::MipsISA::INTINDEX_SCSI = 1 ,   gem5::MipsISA::INTLEVEL_IRQ2 = 22 , gem5::MipsISA::INTLEVEL_IRQ3 = 23 , gem5::MipsISA::INTLEVEL_SERIAL = 33 , gem5::MipsISA::NumInterruptLevels = INTLEVEL_EXTERNAL_MAX }

Functions
static uint8_t	gem5::MipsISA::getCauseIP (ThreadContext *tc)
static void	gem5::MipsISA::setCauseIP (ThreadContext *tc, uint8_t val)