gem5  v21.1.0.2
interrupts.cc
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #include "arch/mips/interrupts.hh"
31 
33 #include "base/trace.hh"
34 #include "cpu/thread_context.hh"
35 #include "debug/Interrupt.hh"
36 
37 namespace gem5
38 {
39 
40 namespace MipsISA
41 {
42 
44 {
47 
50 
57 
59 
61 };
62 
63 static inline uint8_t
65 {
66  CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
67  return cause.ip;
68 }
69 
70 static inline void
72 {
73  CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
74  cause.ip = val;
76 }
77 
78 void
79 Interrupts::post(int int_num)
80 {
81  DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
82  if (int_num < 0 || int_num >= NumInterruptLevels)
83  panic("int_num out of bounds\n");
84 
85  uint8_t intstatus = getCauseIP(tc);
86  intstatus |= 1 << int_num;
87  setCauseIP(tc, intstatus);
88 }
89 
90 void
91 Interrupts::post(int int_num, int index)
92 {
93  fatal("Must use Thread Context when posting MIPS Interrupts in M5");
94 }
95 
96 void
97 Interrupts::clear(int int_num)
98 {
99  DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
100  if (int_num < 0 || int_num >= NumInterruptLevels)
101  panic("int_num out of bounds\n");
102 
103  uint8_t intstatus = getCauseIP(tc);
104  intstatus &= ~(1 << int_num);
105  setCauseIP(tc, intstatus);
106 }
107 
108 void
109 Interrupts::clear(int int_num, int index)
110 {
111  fatal("Must use Thread Context when clearing MIPS Interrupts in M5");
112 }
113 
114 void
116 {
117  DPRINTF(Interrupt, "Interrupts all cleared\n");
118  uint8_t intstatus = 0;
119  setCauseIP(tc, intstatus);
120 }
121 
122 
123 bool
125 {
126  if (!interruptsPending())
127  return false;
128 
129  //Check if there are any outstanding interrupts
131  // Interrupts must be enabled, error level must be 0 or interrupts
132  // inhibited, and exception level must be 0 or interrupts inhibited
133  if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
134  // Software interrupts & hardware interrupts are handled in software.
135  // So if any interrupt that isn't masked is detected, jump to interrupt
136  // handler
137  CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
138  if (status.im && cause.ip)
139  return true;
140 
141  }
142 
143  return false;
144 }
145 
146 Fault
148 {
149  assert(checkInterrupts());
150 
151  GEM5_VAR_USED StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
152  GEM5_VAR_USED CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
153  DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
154  (unsigned)status.im, (unsigned)cause.ip);
155 
156  return std::make_shared<InterruptFault>();
157 }
158 
159 bool
161 {
164  if (compare == count && count != 0)
165  return true;
166  return false;
167 }
168 
169 void Interrupts::updateIntrInfo() {} // Nothing needs to be done.
170 
171 bool
173 {
174  //if there is a on cpu timer interrupt (i.e. Compare == Count)
175  //update CauseIP before proceeding to interrupt
176  if (onCpuTimerInterrupt()) {
177  DPRINTF(Interrupt, "Interrupts OnCpuTimerInterrupt() == true\n");
178  //determine timer interrupt IP #
179  IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
180  uint8_t intStatus = getCauseIP(tc);
181  intStatus |= 1 << intCtl.ipti;
182  setCauseIP(tc, intStatus);
183  }
184 
185  return (getCauseIP(tc) != 0);
186 
187 }
188 
189 } // namespace MipsISA
190 } // namespace gem5
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:189
gem5::MipsISA::Interrupts::clearAll
void clearAll() override
Definition: interrupts.cc:115
gem5::MipsISA::MISCREG_COUNT
@ MISCREG_COUNT
Definition: misc.hh:90
gem5::MipsISA::InterruptLevels
InterruptLevels
Definition: interrupts.cc:43
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::MipsISA::Interrupts::post
void post(int int_num)
Definition: interrupts.cc:79
gem5::MipsISA::MISCREG_STATUS
@ MISCREG_STATUS
Definition: misc.hh:96
gem5::MipsISA::Interrupts::onCpuTimerInterrupt
bool onCpuTimerInterrupt() const
Definition: interrupts.cc:160
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:44
gem5::MipsISA::getCauseIP
static uint8_t getCauseIP(ThreadContext *tc)
Definition: interrupts.cc:64
gem5::MipsISA::INTLEVEL_SERIAL
@ INTLEVEL_SERIAL
Definition: interrupts.cc:58
gem5::MipsISA::INTLEVEL_IRQ2
@ INTLEVEL_IRQ2
Definition: interrupts.cc:55
gem5::MipsISA::Interrupts::getInterrupt
Fault getInterrupt() override
Definition: interrupts.cc:147
pra_constants.hh
gem5::MipsISA::INTINDEX_ETHERNET
@ INTINDEX_ETHERNET
Definition: interrupts.cc:53
gem5::MipsISA::INTLEVEL_IRQ0
@ INTLEVEL_IRQ0
Definition: interrupts.cc:51
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::MipsISA::Interrupts::interruptsPending
bool interruptsPending() const
Definition: interrupts.cc:172
gem5::MipsISA::setCauseIP
static void setCauseIP(ThreadContext *tc, uint8_t val)
Definition: interrupts.cc:71
gem5::MipsISA::INTINDEX_SCSI
@ INTINDEX_SCSI
Definition: interrupts.cc:54
gem5::MipsISA::INTLEVEL_IRQ3
@ INTLEVEL_IRQ3
Definition: interrupts.cc:56
gem5::MipsISA::MISCREG_INTCTL
@ MISCREG_INTCTL
Definition: misc.hh:97
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
interrupts.hh
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::MipsISA::Interrupts::clear
void clear(int int_num)
Definition: interrupts.cc:97
gem5::MipsISA::Interrupts::updateIntrInfo
void updateIntrInfo() override
Definition: interrupts.cc:169
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
gem5::MipsISA::INTLEVEL_SOFTWARE_MAX
@ INTLEVEL_SOFTWARE_MAX
Definition: interrupts.cc:46
gem5::MipsISA::INTLEVEL_EXTERNAL_MIN
@ INTLEVEL_EXTERNAL_MIN
Definition: interrupts.cc:48
gem5::MipsISA::INTLEVEL_SOFTWARE_MIN
@ INTLEVEL_SOFTWARE_MIN
Definition: interrupts.cc:45
gem5::MipsISA::INTLEVEL_IRQ1
@ INTLEVEL_IRQ1
Definition: interrupts.cc:52
gem5::MipsISA::Interrupts::checkInterrupts
bool checkInterrupts() const override
Definition: interrupts.cc:124
trace.hh
gem5::MipsISA::MISCREG_COMPARE
@ MISCREG_COMPARE
Definition: misc.hh:94
gem5::MipsISA::INTLEVEL_EXTERNAL_MAX
@ INTLEVEL_EXTERNAL_MAX
Definition: interrupts.cc:49
gem5::MipsISA::MISCREG_CAUSE
@ MISCREG_CAUSE
Definition: misc.hh:101
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::Interrupt
Definition: faults.hh:557
thread_context.hh
gem5::MipsISA::NumInterruptLevels
@ NumInterruptLevels
Definition: interrupts.cc:60
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422
gem5::ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0

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