gem5  v22.0.0.2
interrupts.hh
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28 
29 #ifndef __ARCH_MIPS_INTERRUPT_HH__
30 #define __ARCH_MIPS_INTERRUPT_HH__
31 
32 #include <string>
33 
35 #include "arch/mips/faults.hh"
36 #include "base/compiler.hh"
37 #include "base/logging.hh"
38 #include "params/MipsInterrupts.hh"
39 #include "sim/serialize.hh"
40 
41 namespace gem5
42 {
43 
44 class BaseCPU;
45 class Checkpoint;
46 
47 namespace MipsISA
48 {
49 
50 class Interrupts : public BaseInterrupts
51 {
52  public:
53  using Params = MipsInterruptsParams;
54 
56 
57  // post(int int_num, int index) is responsible
58  // for posting an interrupt. It sets a bit
59  // in intstatus corresponding to Cause IP*. The
60  // MIPS register Cause is updated by updateIntrInfo
61  // which is called by checkInterrupts
62  //
63  void post(int int_num);
64  void post(int int_num, int index) override;
65 
66  // clear(int int_num, int index) is responsible
67  // for clearing an interrupt. It clear a bit
68  // in intstatus corresponding to Cause IP*. The
69  // MIPS register Cause is updated by updateIntrInfo
70  // which is called by checkInterrupts
71  //
72  void clear(int int_num);
73  void clear(int int_num, int index) override;
74 
75  // clearAll() is responsible
76  // for clearing all interrupts. It clears all bits
77  // in intstatus corresponding to Cause IP*. The
78  // MIPS register Cause is updated by updateIntrInfo
79  // which is called by checkInterrupts
80  //
81  void clearAll() override;
82 
83  // getInterrupt() checks if an interrupt
84  // should be returned. It ands the interrupt mask and
85  // and interrupt pending bits to see if one exists. It
86  // also makes sure interrupts are enabled (IE) and
87  // that ERL and ERX are not set
88  //
89  Fault getInterrupt() override;
90 
91  // updateIntrInfo() const syncs the
92  // MIPS cause register with the instatus variable. instatus
93  // is essentially a copy of the MIPS cause[IP7:IP0]
94  //
95  void updateIntrInfo() override;
96  bool interruptsPending() const;
97  bool onCpuTimerInterrupt() const;
98  bool checkInterrupts() const override;
99 
100  void
101  serialize(CheckpointOut &cp) const override
102  {
103  fatal("Serialization of Interrupts Unimplemented for MIPS");
104  }
105 
106  void
107  unserialize(CheckpointIn &cp) override
108  {
109  fatal("Unserialization of Interrupts Unimplemented for MIPS");
110  }
111 };
112 
113 } // namespace MipsISA
114 } // namespace gem5
115 
116 #endif
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:190
gem5::MipsISA::Interrupts::clearAll
void clearAll() override
Definition: interrupts.cc:115
gem5::MipsISA::Interrupts::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: interrupts.hh:101
serialize.hh
gem5::MipsISA::Interrupts::post
void post(int int_num)
Definition: interrupts.cc:79
gem5::MipsISA::Interrupts::onCpuTimerInterrupt
bool onCpuTimerInterrupt() const
Definition: interrupts.cc:161
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
faults.hh
gem5::BaseInterrupts
Definition: interrupts.hh:41
gem5::MipsISA::Interrupts::getInterrupt
Fault getInterrupt() override
Definition: interrupts.cc:147
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::MipsISA::Interrupts::interruptsPending
bool interruptsPending() const
Definition: interrupts.cc:173
gem5::MipsISA::Interrupts::Interrupts
Interrupts(const Params &p)
Definition: interrupts.hh:55
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::MipsISA::Interrupts::clear
void clear(int int_num)
Definition: interrupts.cc:97
gem5::MipsISA::Interrupts::updateIntrInfo
void updateIntrInfo() override
Definition: interrupts.cc:170
compiler.hh
gem5::MipsISA::Interrupts
Definition: interrupts.hh:50
interrupts.hh
gem5::MipsISA::Interrupts::checkInterrupts
bool checkInterrupts() const override
Definition: interrupts.cc:124
logging.hh
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::BaseInterrupts::Params
BaseInterruptsParams Params
Definition: interrupts.hh:47
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::MipsISA::Interrupts::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: interrupts.hh:107

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