gem5  v21.1.0.2
float.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * Copyright (c) 2007 MIPS Technologies, Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are
8  * met: redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer;
10  * redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution;
13  * neither the name of the copyright holders nor the names of its
14  * contributors may be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28  */
29 
30 #ifndef __ARCH_MIPS_REGS_FLOAT_HH__
31 #define __ARCH_MIPS_REGS_FLOAT_HH__
32 
33 #include <cstdint>
34 
35 namespace gem5
36 {
37 
38 namespace MipsISA
39 {
40 
41 // Constants Related to the number of registers
42 const int NumFloatArchRegs = 32;
43 const int NumFloatSpecialRegs = 5;
44 
46 
47 const uint32_t MIPS32_QNAN = 0x7fbfffff;
48 const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
49 
51 {
57 };
58 
60 {
61  Inexact = 1,
67 };
68 
70 {
74 };
75 
76 } // namespace MipsISA
77 } // namespace gem5
78 
79 #endif
gem5::MipsISA::NumFloatArchRegs
const int NumFloatArchRegs
Definition: float.hh:42
gem5::MipsISA::Flag_Field
@ Flag_Field
Definition: float.hh:71
gem5::MipsISA::FLOATREG_FEXR
@ FLOATREG_FEXR
Definition: float.hh:54
gem5::MipsISA::Invalid
@ Invalid
Definition: float.hh:65
gem5::MipsISA::NumFloatRegs
const int NumFloatRegs
Definition: float.hh:45
gem5::MipsISA::MIPS64_QNAN
const uint64_t MIPS64_QNAN
Definition: float.hh:48
gem5::MipsISA::Overflow
@ Overflow
Definition: float.hh:63
gem5::MipsISA::Enable_Field
@ Enable_Field
Definition: float.hh:72
gem5::MipsISA::NumFloatSpecialRegs
const int NumFloatSpecialRegs
Definition: float.hh:43
gem5::MipsISA::MIPS32_QNAN
const uint32_t MIPS32_QNAN
Definition: float.hh:47
gem5::MipsISA::FLOATREG_FCSR
@ FLOATREG_FCSR
Definition: float.hh:56
gem5::MipsISA::Inexact
@ Inexact
Definition: float.hh:61
gem5::MipsISA::FLOATREG_FIR
@ FLOATREG_FIR
Definition: float.hh:52
gem5::MipsISA::Underflow
@ Underflow
Definition: float.hh:62
gem5::MipsISA::FLOATREG_FCCR
@ FLOATREG_FCCR
Definition: float.hh:53
gem5::MipsISA::DivideByZero
@ DivideByZero
Definition: float.hh:64
gem5::MipsISA::FCSRBits
FCSRBits
Definition: float.hh:59
gem5::MipsISA::Cause_Field
@ Cause_Field
Definition: float.hh:73
gem5::MipsISA::FLOATREG_FENR
@ FLOATREG_FENR
Definition: float.hh:55
gem5::MipsISA::FCSRFields
FCSRFields
Definition: float.hh:69
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::MipsISA::FPControlRegNums
FPControlRegNums
Definition: float.hh:50
gem5::MipsISA::Unimplemented
@ Unimplemented
Definition: float.hh:66

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