gem5  v22.1.0.0
msr.cc
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28 
29 #include "arch/x86/regs/msr.hh"
30 
31 namespace gem5
32 {
33 
34 namespace X86ISA
35 {
36 
37 typedef MsrMap::value_type MsrVal;
38 
39 const MsrMap::value_type msrMapData[] = {
40  MsrVal(0x10, misc_reg::Tsc),
46  MsrVal(0x179, misc_reg::McgCap),
48  MsrVal(0x17B, misc_reg::McgCtl),
81  MsrVal(0x277, misc_reg::Pat),
82  MsrVal(0x2FF, misc_reg::DefType),
83  MsrVal(0x400, misc_reg::Mc0Ctl),
84  MsrVal(0x404, misc_reg::Mc1Ctl),
85  MsrVal(0x408, misc_reg::Mc2Ctl),
86  MsrVal(0x40C, misc_reg::Mc3Ctl),
87  MsrVal(0x410, misc_reg::Mc4Ctl),
88  MsrVal(0x414, misc_reg::Mc5Ctl),
89  MsrVal(0x418, misc_reg::Mc6Ctl),
90  MsrVal(0x41C, misc_reg::Mc7Ctl),
99  MsrVal(0x402, misc_reg::Mc0Addr),
100  MsrVal(0x406, misc_reg::Mc1Addr),
101  MsrVal(0x40A, misc_reg::Mc2Addr),
102  MsrVal(0x40E, misc_reg::Mc3Addr),
103  MsrVal(0x412, misc_reg::Mc4Addr),
104  MsrVal(0x416, misc_reg::Mc5Addr),
105  MsrVal(0x41A, misc_reg::Mc6Addr),
106  MsrVal(0x41E, misc_reg::Mc7Addr),
107  MsrVal(0x403, misc_reg::Mc0Misc),
108  MsrVal(0x407, misc_reg::Mc1Misc),
109  MsrVal(0x40B, misc_reg::Mc2Misc),
110  MsrVal(0x40F, misc_reg::Mc3Misc),
111  MsrVal(0x413, misc_reg::Mc4Misc),
112  MsrVal(0x417, misc_reg::Mc5Misc),
113  MsrVal(0x41B, misc_reg::Mc6Misc),
114  MsrVal(0x41F, misc_reg::Mc7Misc),
115  MsrVal(0xC0000080, misc_reg::Efer),
116  MsrVal(0xC0000081, misc_reg::Star),
117  MsrVal(0xC0000082, misc_reg::Lstar),
118  MsrVal(0xC0000083, misc_reg::Cstar),
119  MsrVal(0xC0000084, misc_reg::SfMask),
120  MsrVal(0xC0000100, misc_reg::FsBase),
121  MsrVal(0xC0000101, misc_reg::GsBase),
122  MsrVal(0xC0000102, misc_reg::KernelGsBase),
123  MsrVal(0xC0000103, misc_reg::TscAux),
124  MsrVal(0xC0010000, misc_reg::PerfEvtSel0),
125  MsrVal(0xC0010001, misc_reg::PerfEvtSel1),
126  MsrVal(0xC0010002, misc_reg::PerfEvtSel2),
127  MsrVal(0xC0010003, misc_reg::PerfEvtSel3),
128  MsrVal(0xC0010004, misc_reg::PerfEvtCtr0),
129  MsrVal(0xC0010005, misc_reg::PerfEvtCtr1),
130  MsrVal(0xC0010006, misc_reg::PerfEvtCtr2),
131  MsrVal(0xC0010007, misc_reg::PerfEvtCtr3),
132  MsrVal(0xC0010010, misc_reg::Syscfg),
133  MsrVal(0xC0010016, misc_reg::IorrBase0),
134  MsrVal(0xC0010017, misc_reg::IorrBase1),
135  MsrVal(0xC0010018, misc_reg::IorrMask0),
136  MsrVal(0xC0010019, misc_reg::IorrMask1),
137  MsrVal(0xC001001A, misc_reg::TopMem),
138  MsrVal(0xC001001D, misc_reg::TopMem2),
139  MsrVal(0xC0010114, misc_reg::VmCr),
140  MsrVal(0xC0010115, misc_reg::Ignne),
141  MsrVal(0xC0010116, misc_reg::SmmCtl),
142  MsrVal(0xC0010117, misc_reg::VmHsavePa)
143 };
144 
145 static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
146 
148 
149 bool
151 {
152  auto it = msrMap.find(addr);
153  if (it == msrMap.end()) {
154  return false;
155  } else {
156  reg_num = it->second;
157  return true;
158  }
159 }
160 
161 } // namespace X86ISA
162 } // namespace gem5
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
std::unordered_map< Addr, RegIndex > MsrMap
Definition: msr.hh:43
Bitfield< 3 > addr
Definition: types.hh:84
static const unsigned msrMapSize
Definition: msr.cc:145
MsrMap::value_type MsrVal
Definition: msr.cc:37
bool msrAddrToIndex(RegIndex &reg_num, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition: msr.cc:150
const MsrMap::value_type msrMapData[]
Definition: msr.cc:39
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
uint16_t RegIndex
Definition: types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147

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