gem5  v21.1.0.2
msr.cc
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28 
29 #include "arch/x86/regs/msr.hh"
30 
31 namespace gem5
32 {
33 
34 namespace X86ISA
35 {
36 
37 typedef MsrMap::value_type MsrVal;
38 
39 const MsrMap::value_type msrMapData[] = {
40  MsrVal(0x10, MISCREG_TSC),
42  MsrVal(0xFE, MISCREG_MTRRCAP),
46  MsrVal(0x179, MISCREG_MCG_CAP),
47  MsrVal(0x17A, MISCREG_MCG_STATUS),
48  MsrVal(0x17B, MISCREG_MCG_CTL),
81  MsrVal(0x277, MISCREG_PAT),
82  MsrVal(0x2FF, MISCREG_DEF_TYPE),
83  MsrVal(0x400, MISCREG_MC0_CTL),
84  MsrVal(0x404, MISCREG_MC1_CTL),
85  MsrVal(0x408, MISCREG_MC2_CTL),
86  MsrVal(0x40C, MISCREG_MC3_CTL),
87  MsrVal(0x410, MISCREG_MC4_CTL),
88  MsrVal(0x414, MISCREG_MC5_CTL),
89  MsrVal(0x418, MISCREG_MC6_CTL),
90  MsrVal(0x41C, MISCREG_MC7_CTL),
91  MsrVal(0x401, MISCREG_MC0_STATUS),
92  MsrVal(0x405, MISCREG_MC1_STATUS),
93  MsrVal(0x409, MISCREG_MC2_STATUS),
94  MsrVal(0x40D, MISCREG_MC3_STATUS),
95  MsrVal(0x411, MISCREG_MC4_STATUS),
96  MsrVal(0x415, MISCREG_MC5_STATUS),
97  MsrVal(0x419, MISCREG_MC6_STATUS),
98  MsrVal(0x41D, MISCREG_MC7_STATUS),
99  MsrVal(0x402, MISCREG_MC0_ADDR),
100  MsrVal(0x406, MISCREG_MC1_ADDR),
101  MsrVal(0x40A, MISCREG_MC2_ADDR),
102  MsrVal(0x40E, MISCREG_MC3_ADDR),
103  MsrVal(0x412, MISCREG_MC4_ADDR),
104  MsrVal(0x416, MISCREG_MC5_ADDR),
105  MsrVal(0x41A, MISCREG_MC6_ADDR),
106  MsrVal(0x41E, MISCREG_MC7_ADDR),
107  MsrVal(0x403, MISCREG_MC0_MISC),
108  MsrVal(0x407, MISCREG_MC1_MISC),
109  MsrVal(0x40B, MISCREG_MC2_MISC),
110  MsrVal(0x40F, MISCREG_MC3_MISC),
111  MsrVal(0x413, MISCREG_MC4_MISC),
112  MsrVal(0x417, MISCREG_MC5_MISC),
113  MsrVal(0x41B, MISCREG_MC6_MISC),
114  MsrVal(0x41F, MISCREG_MC7_MISC),
115  MsrVal(0xC0000080, MISCREG_EFER),
116  MsrVal(0xC0000081, MISCREG_STAR),
117  MsrVal(0xC0000082, MISCREG_LSTAR),
118  MsrVal(0xC0000083, MISCREG_CSTAR),
119  MsrVal(0xC0000084, MISCREG_SF_MASK),
120  MsrVal(0xC0000100, MISCREG_FS_BASE),
121  MsrVal(0xC0000101, MISCREG_GS_BASE),
122  MsrVal(0xC0000102, MISCREG_KERNEL_GS_BASE),
123  MsrVal(0xC0000103, MISCREG_TSC_AUX),
124  MsrVal(0xC0010000, MISCREG_PERF_EVT_SEL0),
125  MsrVal(0xC0010001, MISCREG_PERF_EVT_SEL1),
126  MsrVal(0xC0010002, MISCREG_PERF_EVT_SEL2),
127  MsrVal(0xC0010003, MISCREG_PERF_EVT_SEL3),
128  MsrVal(0xC0010004, MISCREG_PERF_EVT_CTR0),
129  MsrVal(0xC0010005, MISCREG_PERF_EVT_CTR1),
130  MsrVal(0xC0010006, MISCREG_PERF_EVT_CTR2),
131  MsrVal(0xC0010007, MISCREG_PERF_EVT_CTR3),
132  MsrVal(0xC0010010, MISCREG_SYSCFG),
133  MsrVal(0xC0010016, MISCREG_IORR_BASE0),
134  MsrVal(0xC0010017, MISCREG_IORR_BASE1),
135  MsrVal(0xC0010018, MISCREG_IORR_MASK0),
136  MsrVal(0xC0010019, MISCREG_IORR_MASK1),
137  MsrVal(0xC001001A, MISCREG_TOP_MEM),
138  MsrVal(0xC001001D, MISCREG_TOP_MEM2),
139  MsrVal(0xC0010114, MISCREG_VM_CR),
140  MsrVal(0xC0010115, MISCREG_IGNNE),
141  MsrVal(0xC0010116, MISCREG_SMM_CTL),
142  MsrVal(0xC0010117, MISCREG_VM_HSAVE_PA)
143 };
144 
145 static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
146 
148 
149 bool
151 {
152  MsrMap::const_iterator it(msrMap.find(addr));
153  if (it == msrMap.end()) {
154  return false;
155  } else {
156  regNum = it->second;
157  return true;
158  }
159 }
160 
161 } // namespace X86ISA
162 } // namespace gem5
gem5::X86ISA::MISCREG_PERF_EVT_CTR1
@ MISCREG_PERF_EVT_CTR1
Definition: misc.hh:272
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_4
@ MISCREG_MTRR_PHYS_MASK_4
Definition: misc.hh:184
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_2
@ MISCREG_MTRR_PHYS_BASE_2
Definition: misc.hh:171
gem5::X86ISA::MISCREG_LAST_EXCEPTION_TO_IP
@ MISCREG_LAST_EXCEPTION_TO_IP
Definition: misc.hh:166
gem5::X86ISA::MISCREG_FS_BASE
@ MISCREG_FS_BASE
Definition: misc.hh:322
gem5::X86ISA::MISCREG_MC2_ADDR
@ MISCREG_MC2_ADDR
Definition: misc.hh:231
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_7
@ MISCREG_MTRR_PHYS_MASK_7
Definition: misc.hh:187
gem5::X86ISA::MISCREG_MC3_MISC
@ MISCREG_MC3_MISC
Definition: misc.hh:243
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_7
@ MISCREG_MTRR_PHYS_BASE_7
Definition: misc.hh:176
gem5::X86ISA::msrMap
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_1
@ MISCREG_MTRR_PHYS_BASE_1
Definition: misc.hh:170
gem5::X86ISA::MISCREG_MTRR_FIX_4K_F8000
@ MISCREG_MTRR_FIX_4K_F8000
Definition: misc.hh:200
gem5::X86ISA::MISCREG_DEBUG_CTL_MSR
@ MISCREG_DEBUG_CTL_MSR
Definition: misc.hh:161
gem5::X86ISA::MISCREG_MC6_CTL
@ MISCREG_MC6_CTL
Definition: misc.hh:213
gem5::X86ISA::MISCREG_MC5_MISC
@ MISCREG_MC5_MISC
Definition: misc.hh:245
gem5::X86ISA::MISCREG_PERF_EVT_SEL0
@ MISCREG_PERF_EVT_SEL0
Definition: misc.hh:264
gem5::X86ISA::MISCREG_MC5_ADDR
@ MISCREG_MC5_ADDR
Definition: misc.hh:234
gem5::X86ISA::MISCREG_MTRR_FIX_4K_E8000
@ MISCREG_MTRR_FIX_4K_E8000
Definition: misc.hh:198
gem5::X86ISA::MISCREG_APIC_BASE
@ MISCREG_APIC_BASE
Definition: misc.hh:399
gem5::X86ISA::MISCREG_MC0_MISC
@ MISCREG_MC0_MISC
Definition: misc.hh:240
gem5::X86ISA::MISCREG_VM_HSAVE_PA
@ MISCREG_VM_HSAVE_PA
Definition: misc.hh:295
gem5::X86ISA::MISCREG_MTRR_FIX_4K_E0000
@ MISCREG_MTRR_FIX_4K_E0000
Definition: misc.hh:197
gem5::X86ISA::MISCREG_MCG_STATUS
@ MISCREG_MCG_STATUS
Definition: misc.hh:158
gem5::X86ISA::MISCREG_MTRR_FIX_4K_C0000
@ MISCREG_MTRR_FIX_4K_C0000
Definition: misc.hh:193
gem5::X86ISA::MISCREG_MTRRCAP
@ MISCREG_MTRRCAP
Definition: misc.hh:151
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_3
@ MISCREG_MTRR_PHYS_MASK_3
Definition: misc.hh:183
gem5::X86ISA::MISCREG_MC0_CTL
@ MISCREG_MC0_CTL
Definition: misc.hh:207
gem5::X86ISA::MISCREG_SYSENTER_ESP
@ MISCREG_SYSENTER_ESP
Definition: misc.hh:154
gem5::X86ISA::MISCREG_IORR_BASE0
@ MISCREG_IORR_BASE0
Definition: misc.hh:280
gem5::X86ISA::MISCREG_MTRR_FIX_4K_D8000
@ MISCREG_MTRR_FIX_4K_D8000
Definition: misc.hh:196
gem5::X86ISA::MISCREG_PERF_EVT_CTR2
@ MISCREG_PERF_EVT_CTR2
Definition: misc.hh:273
gem5::X86ISA::MISCREG_MC1_ADDR
@ MISCREG_MC1_ADDR
Definition: misc.hh:230
gem5::X86ISA::MISCREG_MC6_ADDR
@ MISCREG_MC6_ADDR
Definition: misc.hh:235
gem5::X86ISA::MISCREG_MC7_ADDR
@ MISCREG_MC7_ADDR
Definition: misc.hh:236
gem5::X86ISA::MISCREG_MC2_CTL
@ MISCREG_MC2_CTL
Definition: misc.hh:209
gem5::X86ISA::MISCREG_MCG_CAP
@ MISCREG_MCG_CAP
Definition: misc.hh:157
gem5::X86ISA::MISCREG_STAR
@ MISCREG_STAR
Definition: misc.hh:253
gem5::X86ISA::MISCREG_MC0_ADDR
@ MISCREG_MC0_ADDR
Definition: misc.hh:229
gem5::X86ISA::MISCREG_MTRR_FIX_4K_F0000
@ MISCREG_MTRR_FIX_4K_F0000
Definition: misc.hh:199
gem5::X86ISA::MISCREG_DEF_TYPE
@ MISCREG_DEF_TYPE
Definition: misc.hh:204
gem5::X86ISA::MISCREG_IORR_MASK1
@ MISCREG_IORR_MASK1
Definition: misc.hh:286
gem5::X86ISA::MISCREG_MC4_ADDR
@ MISCREG_MC4_ADDR
Definition: misc.hh:233
gem5::X86ISA::MISCREG_SF_MASK
@ MISCREG_SF_MASK
Definition: misc.hh:257
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_5
@ MISCREG_MTRR_PHYS_BASE_5
Definition: misc.hh:174
gem5::X86ISA::MISCREG_MC4_STATUS
@ MISCREG_MC4_STATUS
Definition: misc.hh:222
gem5::X86ISA::MISCREG_PERF_EVT_CTR0
@ MISCREG_PERF_EVT_CTR0
Definition: misc.hh:271
gem5::X86ISA::MISCREG_LSTAR
@ MISCREG_LSTAR
Definition: misc.hh:254
gem5::X86ISA::MISCREG_MC6_STATUS
@ MISCREG_MC6_STATUS
Definition: misc.hh:224
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_0
@ MISCREG_MTRR_PHYS_MASK_0
Definition: misc.hh:180
gem5::X86ISA::MISCREG_MC2_STATUS
@ MISCREG_MC2_STATUS
Definition: misc.hh:220
gem5::X86ISA::msrMapSize
static const unsigned msrMapSize
Definition: msr.cc:145
gem5::X86ISA::MISCREG_MTRR_FIX_4K_D0000
@ MISCREG_MTRR_FIX_4K_D0000
Definition: misc.hh:195
gem5::X86ISA::MISCREG_TOP_MEM
@ MISCREG_TOP_MEM
Definition: misc.hh:289
gem5::X86ISA::MISCREG_LAST_BRANCH_FROM_IP
@ MISCREG_LAST_BRANCH_FROM_IP
Definition: misc.hh:163
gem5::X86ISA::MISCREG_MC7_STATUS
@ MISCREG_MC7_STATUS
Definition: misc.hh:225
gem5::X86ISA::MISCREG_TOP_MEM2
@ MISCREG_TOP_MEM2
Definition: misc.hh:290
gem5::X86ISA::MISCREG_PAT
@ MISCREG_PAT
Definition: misc.hh:202
msr.hh
gem5::X86ISA::MISCREG_MC7_MISC
@ MISCREG_MC7_MISC
Definition: misc.hh:247
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_6
@ MISCREG_MTRR_PHYS_BASE_6
Definition: misc.hh:175
gem5::X86ISA::MISCREG_TSC
@ MISCREG_TSC
Definition: misc.hh:149
gem5::X86ISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:106
gem5::X86ISA::MISCREG_IORR_MASK0
@ MISCREG_IORR_MASK0
Definition: misc.hh:285
gem5::X86ISA::MISCREG_SMM_CTL
@ MISCREG_SMM_CTL
Definition: misc.hh:294
gem5::X86ISA::MISCREG_KERNEL_GS_BASE
@ MISCREG_KERNEL_GS_BASE
Definition: misc.hh:259
gem5::X86ISA::MISCREG_PERF_EVT_SEL1
@ MISCREG_PERF_EVT_SEL1
Definition: misc.hh:265
gem5::X86ISA::MISCREG_MC2_MISC
@ MISCREG_MC2_MISC
Definition: misc.hh:242
gem5::X86ISA::MISCREG_PERF_EVT_SEL2
@ MISCREG_PERF_EVT_SEL2
Definition: misc.hh:266
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
gem5::X86ISA::MISCREG_LAST_BRANCH_TO_IP
@ MISCREG_LAST_BRANCH_TO_IP
Definition: misc.hh:164
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_2
@ MISCREG_MTRR_PHYS_MASK_2
Definition: misc.hh:182
gem5::X86ISA::MISCREG_MTRR_FIX_4K_C8000
@ MISCREG_MTRR_FIX_4K_C8000
Definition: misc.hh:194
gem5::X86ISA::MISCREG_MC3_ADDR
@ MISCREG_MC3_ADDR
Definition: misc.hh:232
gem5::X86ISA::msrMapData
const MsrMap::value_type msrMapData[]
Definition: msr.cc:39
gem5::X86ISA::MsrMap
std::unordered_map< Addr, MiscRegIndex > MsrMap
Definition: msr.hh:43
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_3
@ MISCREG_MTRR_PHYS_BASE_3
Definition: misc.hh:172
gem5::X86ISA::MISCREG_MC4_MISC
@ MISCREG_MC4_MISC
Definition: misc.hh:244
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::msrAddrToIndex
bool msrAddrToIndex(MiscRegIndex &regNum, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition: msr.cc:150
gem5::X86ISA::MISCREG_SYSENTER_CS
@ MISCREG_SYSENTER_CS
Definition: misc.hh:153
gem5::X86ISA::MISCREG_MC1_STATUS
@ MISCREG_MC1_STATUS
Definition: misc.hh:219
gem5::X86ISA::MISCREG_MC4_CTL
@ MISCREG_MC4_CTL
Definition: misc.hh:211
gem5::X86ISA::MISCREG_MC6_MISC
@ MISCREG_MC6_MISC
Definition: misc.hh:246
gem5::X86ISA::MISCREG_MC5_CTL
@ MISCREG_MC5_CTL
Definition: misc.hh:212
gem5::X86ISA::MsrVal
MsrMap::value_type MsrVal
Definition: msr.cc:37
gem5::X86ISA::MISCREG_MC3_STATUS
@ MISCREG_MC3_STATUS
Definition: misc.hh:221
gem5::X86ISA::MISCREG_MTRR_FIX_16K_A0000
@ MISCREG_MTRR_FIX_16K_A0000
Definition: misc.hh:192
gem5::X86ISA::MISCREG_MC1_MISC
@ MISCREG_MC1_MISC
Definition: misc.hh:241
gem5::X86ISA::MISCREG_MCG_CTL
@ MISCREG_MCG_CTL
Definition: misc.hh:159
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_0
@ MISCREG_MTRR_PHYS_BASE_0
Definition: misc.hh:169
gem5::X86ISA::MISCREG_GS_BASE
@ MISCREG_GS_BASE
Definition: misc.hh:323
gem5::X86ISA::MISCREG_MC5_STATUS
@ MISCREG_MC5_STATUS
Definition: misc.hh:223
gem5::X86ISA::MISCREG_SYSCFG
@ MISCREG_SYSCFG
Definition: misc.hh:277
gem5::X86ISA::MISCREG_VM_CR
@ MISCREG_VM_CR
Definition: misc.hh:292
gem5::X86ISA::MISCREG_MC0_STATUS
@ MISCREG_MC0_STATUS
Definition: misc.hh:218
gem5::X86ISA::MISCREG_LAST_EXCEPTION_FROM_IP
@ MISCREG_LAST_EXCEPTION_FROM_IP
Definition: misc.hh:165
gem5::X86ISA::MISCREG_IGNNE
@ MISCREG_IGNNE
Definition: misc.hh:293
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_5
@ MISCREG_MTRR_PHYS_MASK_5
Definition: misc.hh:185
gem5::X86ISA::MISCREG_PERF_EVT_SEL3
@ MISCREG_PERF_EVT_SEL3
Definition: misc.hh:267
gem5::X86ISA::MISCREG_SYSENTER_EIP
@ MISCREG_SYSENTER_EIP
Definition: misc.hh:155
gem5::X86ISA::MISCREG_IORR_BASE1
@ MISCREG_IORR_BASE1
Definition: misc.hh:281
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::MISCREG_MC7_CTL
@ MISCREG_MC7_CTL
Definition: misc.hh:214
gem5::X86ISA::MISCREG_TSC_AUX
@ MISCREG_TSC_AUX
Definition: misc.hh:261
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_1
@ MISCREG_MTRR_PHYS_MASK_1
Definition: misc.hh:181
gem5::X86ISA::MISCREG_MC3_CTL
@ MISCREG_MC3_CTL
Definition: misc.hh:210
gem5::X86ISA::MISCREG_MC1_CTL
@ MISCREG_MC1_CTL
Definition: misc.hh:208
gem5::X86ISA::MISCREG_MTRR_FIX_16K_80000
@ MISCREG_MTRR_FIX_16K_80000
Definition: misc.hh:191
gem5::X86ISA::MISCREG_MTRR_FIX_64K_00000
@ MISCREG_MTRR_FIX_64K_00000
Definition: misc.hh:190
gem5::X86ISA::MISCREG_CSTAR
@ MISCREG_CSTAR
Definition: misc.hh:255
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_6
@ MISCREG_MTRR_PHYS_MASK_6
Definition: misc.hh:186
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::X86ISA::MISCREG_PERF_EVT_CTR3
@ MISCREG_PERF_EVT_CTR3
Definition: misc.hh:274
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_4
@ MISCREG_MTRR_PHYS_BASE_4
Definition: misc.hh:173

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