gem5 v24.0.0.0
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msr.cc
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1/*
2 * Copyright (c) 2011 Google
3 * All rights reserved.
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7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
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14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 */
28
29#include "arch/x86/regs/msr.hh"
30
31namespace gem5
32{
33
34namespace X86ISA
35{
36
37typedef MsrMap::value_type MsrVal;
38
39const MsrMap::value_type msrMapData[] = {
40 MsrVal(0x10, misc_reg::Tsc),
81 MsrVal(0x277, misc_reg::Pat),
115 MsrVal(0xC0000080, misc_reg::Efer),
116 MsrVal(0xC0000081, misc_reg::Star),
117 MsrVal(0xC0000082, misc_reg::Lstar),
118 MsrVal(0xC0000083, misc_reg::Cstar),
119 MsrVal(0xC0000084, misc_reg::SfMask),
120 MsrVal(0xC0000100, misc_reg::FsBase),
121 MsrVal(0xC0000101, misc_reg::GsBase),
122 MsrVal(0xC0000102, misc_reg::KernelGsBase),
123 MsrVal(0xC0000103, misc_reg::TscAux),
124 MsrVal(0xC0010000, misc_reg::PerfEvtSel0),
125 MsrVal(0xC0010001, misc_reg::PerfEvtSel1),
126 MsrVal(0xC0010002, misc_reg::PerfEvtSel2),
127 MsrVal(0xC0010003, misc_reg::PerfEvtSel3),
128 MsrVal(0xC0010004, misc_reg::PerfEvtCtr0),
129 MsrVal(0xC0010005, misc_reg::PerfEvtCtr1),
130 MsrVal(0xC0010006, misc_reg::PerfEvtCtr2),
131 MsrVal(0xC0010007, misc_reg::PerfEvtCtr3),
132 MsrVal(0xC0010010, misc_reg::Syscfg),
133 MsrVal(0xC0010016, misc_reg::IorrBase0),
134 MsrVal(0xC0010017, misc_reg::IorrBase1),
135 MsrVal(0xC0010018, misc_reg::IorrMask0),
136 MsrVal(0xC0010019, misc_reg::IorrMask1),
137 MsrVal(0xC001001A, misc_reg::TopMem),
138 MsrVal(0xC001001D, misc_reg::TopMem2),
139 MsrVal(0xC0010114, misc_reg::VmCr),
140 MsrVal(0xC0010115, misc_reg::Ignne),
141 MsrVal(0xC0010116, misc_reg::SmmCtl),
142 MsrVal(0xC0010117, misc_reg::VmHsavePa)
143};
144
145static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0]);
146
148
149bool
151{
152 auto it = msrMap.find(addr);
153 if (it == msrMap.end()) {
154 return false;
155 } else {
156 reg_num = it->second;
157 return true;
158 }
159}
160
161} // namespace X86ISA
162} // namespace gem5
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
std::unordered_map< Addr, RegIndex > MsrMap
Definition msr.hh:43
Bitfield< 3 > addr
Definition types.hh:84
static const unsigned msrMapSize
Definition msr.cc:145
MsrMap::value_type MsrVal
Definition msr.cc:37
bool msrAddrToIndex(RegIndex &reg_num, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition msr.cc:150
const MsrMap::value_type msrMapData[]
Definition msr.cc:39
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147

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