gem5
v24.0.0.0
Loading...
Searching...
No Matches
arch
x86
regs
msr.cc
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2011 Google
3
* All rights reserved.
4
*
5
* Redistribution and use in source and binary forms, with or without
6
* modification, are permitted provided that the following conditions are
7
* met: redistributions of source code must retain the above copyright
8
* notice, this list of conditions and the following disclaimer;
9
* redistributions in binary form must reproduce the above copyright
10
* notice, this list of conditions and the following disclaimer in the
11
* documentation and/or other materials provided with the distribution;
12
* neither the name of the copyright holders nor the names of its
13
* contributors may be used to endorse or promote products derived from
14
* this software without specific prior written permission.
15
*
16
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
*/
28
29
#include "
arch/x86/regs/msr.hh
"
30
31
namespace
gem5
32
{
33
34
namespace
X86ISA
35
{
36
37
typedef
MsrMap::value_type
MsrVal
;
38
39
const
MsrMap::value_type
msrMapData
[] = {
40
MsrVal
(0x10,
misc_reg::Tsc
),
41
MsrVal
(0x1B,
misc_reg::ApicBase
),
42
MsrVal
(0xFE,
misc_reg::Mtrrcap
),
43
MsrVal
(0x174,
misc_reg::SysenterCs
),
44
MsrVal
(0x175,
misc_reg::SysenterEsp
),
45
MsrVal
(0x176,
misc_reg::SysenterEip
),
46
MsrVal
(0x179,
misc_reg::McgCap
),
47
MsrVal
(0x17A,
misc_reg::McgStatus
),
48
MsrVal
(0x17B,
misc_reg::McgCtl
),
49
MsrVal
(0x1D9,
misc_reg::DebugCtlMsr
),
50
MsrVal
(0x1DB,
misc_reg::LastBranchFromIp
),
51
MsrVal
(0x1DC,
misc_reg::LastBranchToIp
),
52
MsrVal
(0x1DD,
misc_reg::LastExceptionFromIp
),
53
MsrVal
(0x1DE,
misc_reg::LastExceptionToIp
),
54
MsrVal
(0x200,
misc_reg::MtrrPhysBase0
),
55
MsrVal
(0x201,
misc_reg::MtrrPhysMask0
),
56
MsrVal
(0x202,
misc_reg::MtrrPhysBase1
),
57
MsrVal
(0x203,
misc_reg::MtrrPhysMask1
),
58
MsrVal
(0x204,
misc_reg::MtrrPhysBase2
),
59
MsrVal
(0x205,
misc_reg::MtrrPhysMask2
),
60
MsrVal
(0x206,
misc_reg::MtrrPhysBase3
),
61
MsrVal
(0x207,
misc_reg::MtrrPhysMask3
),
62
MsrVal
(0x208,
misc_reg::MtrrPhysBase4
),
63
MsrVal
(0x209,
misc_reg::MtrrPhysMask4
),
64
MsrVal
(0x20A,
misc_reg::MtrrPhysBase5
),
65
MsrVal
(0x20B,
misc_reg::MtrrPhysMask5
),
66
MsrVal
(0x20C,
misc_reg::MtrrPhysBase6
),
67
MsrVal
(0x20D,
misc_reg::MtrrPhysMask6
),
68
MsrVal
(0x20E,
misc_reg::MtrrPhysBase7
),
69
MsrVal
(0x20F,
misc_reg::MtrrPhysMask7
),
70
MsrVal
(0x250,
misc_reg::MtrrFix64k00000
),
71
MsrVal
(0x258,
misc_reg::MtrrFix16k80000
),
72
MsrVal
(0x259,
misc_reg::MtrrFix16kA0000
),
73
MsrVal
(0x268,
misc_reg::MtrrFix4kC0000
),
74
MsrVal
(0x269,
misc_reg::MtrrFix4kC8000
),
75
MsrVal
(0x26A,
misc_reg::MtrrFix4kD0000
),
76
MsrVal
(0x26B,
misc_reg::MtrrFix4kD8000
),
77
MsrVal
(0x26C,
misc_reg::MtrrFix4kE0000
),
78
MsrVal
(0x26D,
misc_reg::MtrrFix4kE8000
),
79
MsrVal
(0x26E,
misc_reg::MtrrFix4kF0000
),
80
MsrVal
(0x26F,
misc_reg::MtrrFix4kF8000
),
81
MsrVal
(0x277,
misc_reg::Pat
),
82
MsrVal
(0x2FF,
misc_reg::DefType
),
83
MsrVal
(0x400,
misc_reg::Mc0Ctl
),
84
MsrVal
(0x404,
misc_reg::Mc1Ctl
),
85
MsrVal
(0x408,
misc_reg::Mc2Ctl
),
86
MsrVal
(0x40C,
misc_reg::Mc3Ctl
),
87
MsrVal
(0x410,
misc_reg::Mc4Ctl
),
88
MsrVal
(0x414,
misc_reg::Mc5Ctl
),
89
MsrVal
(0x418,
misc_reg::Mc6Ctl
),
90
MsrVal
(0x41C,
misc_reg::Mc7Ctl
),
91
MsrVal
(0x401,
misc_reg::Mc0Status
),
92
MsrVal
(0x405,
misc_reg::Mc1Status
),
93
MsrVal
(0x409,
misc_reg::Mc2Status
),
94
MsrVal
(0x40D,
misc_reg::Mc3Status
),
95
MsrVal
(0x411,
misc_reg::Mc4Status
),
96
MsrVal
(0x415,
misc_reg::Mc5Status
),
97
MsrVal
(0x419,
misc_reg::Mc6Status
),
98
MsrVal
(0x41D,
misc_reg::Mc7Status
),
99
MsrVal
(0x402,
misc_reg::Mc0Addr
),
100
MsrVal
(0x406,
misc_reg::Mc1Addr
),
101
MsrVal
(0x40A,
misc_reg::Mc2Addr
),
102
MsrVal
(0x40E,
misc_reg::Mc3Addr
),
103
MsrVal
(0x412,
misc_reg::Mc4Addr
),
104
MsrVal
(0x416,
misc_reg::Mc5Addr
),
105
MsrVal
(0x41A,
misc_reg::Mc6Addr
),
106
MsrVal
(0x41E,
misc_reg::Mc7Addr
),
107
MsrVal
(0x403,
misc_reg::Mc0Misc
),
108
MsrVal
(0x407,
misc_reg::Mc1Misc
),
109
MsrVal
(0x40B,
misc_reg::Mc2Misc
),
110
MsrVal
(0x40F,
misc_reg::Mc3Misc
),
111
MsrVal
(0x413,
misc_reg::Mc4Misc
),
112
MsrVal
(0x417,
misc_reg::Mc5Misc
),
113
MsrVal
(0x41B,
misc_reg::Mc6Misc
),
114
MsrVal
(0x41F,
misc_reg::Mc7Misc
),
115
MsrVal
(0xC0000080,
misc_reg::Efer
),
116
MsrVal
(0xC0000081,
misc_reg::Star
),
117
MsrVal
(0xC0000082,
misc_reg::Lstar
),
118
MsrVal
(0xC0000083,
misc_reg::Cstar
),
119
MsrVal
(0xC0000084,
misc_reg::SfMask
),
120
MsrVal
(0xC0000100,
misc_reg::FsBase
),
121
MsrVal
(0xC0000101,
misc_reg::GsBase
),
122
MsrVal
(0xC0000102,
misc_reg::KernelGsBase
),
123
MsrVal
(0xC0000103,
misc_reg::TscAux
),
124
MsrVal
(0xC0010000,
misc_reg::PerfEvtSel0
),
125
MsrVal
(0xC0010001,
misc_reg::PerfEvtSel1
),
126
MsrVal
(0xC0010002,
misc_reg::PerfEvtSel2
),
127
MsrVal
(0xC0010003,
misc_reg::PerfEvtSel3
),
128
MsrVal
(0xC0010004,
misc_reg::PerfEvtCtr0
),
129
MsrVal
(0xC0010005,
misc_reg::PerfEvtCtr1
),
130
MsrVal
(0xC0010006,
misc_reg::PerfEvtCtr2
),
131
MsrVal
(0xC0010007,
misc_reg::PerfEvtCtr3
),
132
MsrVal
(0xC0010010,
misc_reg::Syscfg
),
133
MsrVal
(0xC0010016,
misc_reg::IorrBase0
),
134
MsrVal
(0xC0010017,
misc_reg::IorrBase1
),
135
MsrVal
(0xC0010018,
misc_reg::IorrMask0
),
136
MsrVal
(0xC0010019,
misc_reg::IorrMask1
),
137
MsrVal
(0xC001001A,
misc_reg::TopMem
),
138
MsrVal
(0xC001001D,
misc_reg::TopMem2
),
139
MsrVal
(0xC0010114,
misc_reg::VmCr
),
140
MsrVal
(0xC0010115,
misc_reg::Ignne
),
141
MsrVal
(0xC0010116,
misc_reg::SmmCtl
),
142
MsrVal
(0xC0010117,
misc_reg::VmHsavePa
)
143
};
144
145
static
const
unsigned
msrMapSize
=
sizeof
(
msrMapData
) /
sizeof
(
msrMapData
[0]);
146
147
const
MsrMap
msrMap
(
msrMapData
,
msrMapData
+
msrMapSize
);
148
149
bool
150
msrAddrToIndex
(
RegIndex
®_num,
Addr
addr
)
151
{
152
auto
it =
msrMap
.find(
addr
);
153
if
(it ==
msrMap
.end()) {
154
return
false
;
155
}
else
{
156
reg_num = it->second;
157
return
true
;
158
}
159
}
160
161
}
// namespace X86ISA
162
}
// namespace gem5
msr.hh
gem5::X86ISA::misc_reg::PerfEvtSel0
@ PerfEvtSel0
Definition
misc.hh:269
gem5::X86ISA::misc_reg::Mc3Misc
@ Mc3Misc
Definition
misc.hh:248
gem5::X86ISA::misc_reg::MtrrFix4kF0000
@ MtrrFix4kF0000
Definition
misc.hh:204
gem5::X86ISA::misc_reg::MtrrPhysMask1
@ MtrrPhysMask1
Definition
misc.hh:186
gem5::X86ISA::misc_reg::Mc0Ctl
@ Mc0Ctl
Definition
misc.hh:212
gem5::X86ISA::misc_reg::Mc0Addr
@ Mc0Addr
Definition
misc.hh:234
gem5::X86ISA::misc_reg::TscAux
@ TscAux
Definition
misc.hh:266
gem5::X86ISA::misc_reg::PerfEvtSel1
@ PerfEvtSel1
Definition
misc.hh:270
gem5::X86ISA::misc_reg::Mc6Addr
@ Mc6Addr
Definition
misc.hh:240
gem5::X86ISA::misc_reg::Mc2Ctl
@ Mc2Ctl
Definition
misc.hh:214
gem5::X86ISA::misc_reg::Mc4Status
@ Mc4Status
Definition
misc.hh:227
gem5::X86ISA::misc_reg::Mc5Addr
@ Mc5Addr
Definition
misc.hh:239
gem5::X86ISA::misc_reg::DefType
@ DefType
Definition
misc.hh:209
gem5::X86ISA::misc_reg::Mc7Ctl
@ Mc7Ctl
Definition
misc.hh:219
gem5::X86ISA::misc_reg::Mc5Status
@ Mc5Status
Definition
misc.hh:228
gem5::X86ISA::misc_reg::MtrrFix4kC8000
@ MtrrFix4kC8000
Definition
misc.hh:199
gem5::X86ISA::misc_reg::MtrrPhysBase4
@ MtrrPhysBase4
Definition
misc.hh:178
gem5::X86ISA::misc_reg::PerfEvtCtr2
@ PerfEvtCtr2
Definition
misc.hh:278
gem5::X86ISA::misc_reg::Mc1Addr
@ Mc1Addr
Definition
misc.hh:235
gem5::X86ISA::misc_reg::Mc0Misc
@ Mc0Misc
Definition
misc.hh:245
gem5::X86ISA::misc_reg::McgCap
@ McgCap
Definition
misc.hh:162
gem5::X86ISA::misc_reg::PerfEvtSel2
@ PerfEvtSel2
Definition
misc.hh:271
gem5::X86ISA::misc_reg::MtrrFix4kD8000
@ MtrrFix4kD8000
Definition
misc.hh:201
gem5::X86ISA::misc_reg::Mc3Ctl
@ Mc3Ctl
Definition
misc.hh:215
gem5::X86ISA::misc_reg::McgCtl
@ McgCtl
Definition
misc.hh:164
gem5::X86ISA::misc_reg::MtrrFix16kA0000
@ MtrrFix16kA0000
Definition
misc.hh:197
gem5::X86ISA::misc_reg::Mc3Addr
@ Mc3Addr
Definition
misc.hh:237
gem5::X86ISA::misc_reg::Mc3Status
@ Mc3Status
Definition
misc.hh:226
gem5::X86ISA::misc_reg::IorrMask1
@ IorrMask1
Definition
misc.hh:291
gem5::X86ISA::misc_reg::MtrrFix4kE0000
@ MtrrFix4kE0000
Definition
misc.hh:202
gem5::X86ISA::misc_reg::McgStatus
@ McgStatus
Definition
misc.hh:163
gem5::X86ISA::misc_reg::TopMem2
@ TopMem2
Definition
misc.hh:295
gem5::X86ISA::misc_reg::MtrrPhysBase7
@ MtrrPhysBase7
Definition
misc.hh:181
gem5::X86ISA::misc_reg::Mc1Status
@ Mc1Status
Definition
misc.hh:224
gem5::X86ISA::misc_reg::SysenterEsp
@ SysenterEsp
Definition
misc.hh:159
gem5::X86ISA::misc_reg::Mc0Status
@ Mc0Status
Definition
misc.hh:223
gem5::X86ISA::misc_reg::IorrBase1
@ IorrBase1
Definition
misc.hh:286
gem5::X86ISA::misc_reg::MtrrPhysBase1
@ MtrrPhysBase1
Definition
misc.hh:175
gem5::X86ISA::misc_reg::DebugCtlMsr
@ DebugCtlMsr
Definition
misc.hh:166
gem5::X86ISA::misc_reg::PerfEvtCtr0
@ PerfEvtCtr0
Definition
misc.hh:276
gem5::X86ISA::misc_reg::VmHsavePa
@ VmHsavePa
Definition
misc.hh:300
gem5::X86ISA::misc_reg::Mc2Status
@ Mc2Status
Definition
misc.hh:225
gem5::X86ISA::misc_reg::PerfEvtCtr3
@ PerfEvtCtr3
Definition
misc.hh:279
gem5::X86ISA::misc_reg::MtrrFix4kE8000
@ MtrrFix4kE8000
Definition
misc.hh:203
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition
misc.hh:256
gem5::X86ISA::misc_reg::Mc2Misc
@ Mc2Misc
Definition
misc.hh:247
gem5::X86ISA::misc_reg::Mc6Status
@ Mc6Status
Definition
misc.hh:229
gem5::X86ISA::misc_reg::VmCr
@ VmCr
Definition
misc.hh:297
gem5::X86ISA::misc_reg::Mc7Misc
@ Mc7Misc
Definition
misc.hh:252
gem5::X86ISA::misc_reg::LastExceptionToIp
@ LastExceptionToIp
Definition
misc.hh:171
gem5::X86ISA::misc_reg::Mc7Status
@ Mc7Status
Definition
misc.hh:230
gem5::X86ISA::misc_reg::MtrrPhysMask4
@ MtrrPhysMask4
Definition
misc.hh:189
gem5::X86ISA::misc_reg::MtrrFix16k80000
@ MtrrFix16k80000
Definition
misc.hh:196
gem5::X86ISA::misc_reg::MtrrPhysBase2
@ MtrrPhysBase2
Definition
misc.hh:176
gem5::X86ISA::misc_reg::Star
@ Star
Definition
misc.hh:258
gem5::X86ISA::misc_reg::MtrrFix4kC0000
@ MtrrFix4kC0000
Definition
misc.hh:198
gem5::X86ISA::misc_reg::Cstar
@ Cstar
Definition
misc.hh:260
gem5::X86ISA::misc_reg::IorrBase0
@ IorrBase0
Definition
misc.hh:285
gem5::X86ISA::misc_reg::SfMask
@ SfMask
Definition
misc.hh:262
gem5::X86ISA::misc_reg::MtrrPhysBase0
@ MtrrPhysBase0
Definition
misc.hh:174
gem5::X86ISA::misc_reg::Mc4Misc
@ Mc4Misc
Definition
misc.hh:249
gem5::X86ISA::misc_reg::SmmCtl
@ SmmCtl
Definition
misc.hh:299
gem5::X86ISA::misc_reg::PerfEvtCtr1
@ PerfEvtCtr1
Definition
misc.hh:277
gem5::X86ISA::misc_reg::Mc5Misc
@ Mc5Misc
Definition
misc.hh:250
gem5::X86ISA::misc_reg::Mc1Misc
@ Mc1Misc
Definition
misc.hh:246
gem5::X86ISA::misc_reg::MtrrPhysBase3
@ MtrrPhysBase3
Definition
misc.hh:177
gem5::X86ISA::misc_reg::Mc7Addr
@ Mc7Addr
Definition
misc.hh:241
gem5::X86ISA::misc_reg::MtrrPhysMask2
@ MtrrPhysMask2
Definition
misc.hh:187
gem5::X86ISA::misc_reg::Tsc
@ Tsc
Definition
misc.hh:154
gem5::X86ISA::misc_reg::Mc4Ctl
@ Mc4Ctl
Definition
misc.hh:216
gem5::X86ISA::misc_reg::KernelGsBase
@ KernelGsBase
Definition
misc.hh:264
gem5::X86ISA::misc_reg::Pat
@ Pat
Definition
misc.hh:207
gem5::X86ISA::misc_reg::FsBase
@ FsBase
Definition
misc.hh:327
gem5::X86ISA::misc_reg::ApicBase
@ ApicBase
Definition
misc.hh:403
gem5::X86ISA::misc_reg::Mc6Misc
@ Mc6Misc
Definition
misc.hh:251
gem5::X86ISA::misc_reg::MtrrPhysMask7
@ MtrrPhysMask7
Definition
misc.hh:192
gem5::X86ISA::misc_reg::TopMem
@ TopMem
Definition
misc.hh:294
gem5::X86ISA::misc_reg::MtrrFix4kF8000
@ MtrrFix4kF8000
Definition
misc.hh:205
gem5::X86ISA::misc_reg::Mc6Ctl
@ Mc6Ctl
Definition
misc.hh:218
gem5::X86ISA::misc_reg::MtrrPhysMask0
@ MtrrPhysMask0
Definition
misc.hh:185
gem5::X86ISA::misc_reg::MtrrFix4kD0000
@ MtrrFix4kD0000
Definition
misc.hh:200
gem5::X86ISA::misc_reg::SysenterCs
@ SysenterCs
Definition
misc.hh:158
gem5::X86ISA::misc_reg::Lstar
@ Lstar
Definition
misc.hh:259
gem5::X86ISA::misc_reg::MtrrPhysBase6
@ MtrrPhysBase6
Definition
misc.hh:180
gem5::X86ISA::misc_reg::LastBranchFromIp
@ LastBranchFromIp
Definition
misc.hh:168
gem5::X86ISA::misc_reg::Mc4Addr
@ Mc4Addr
Definition
misc.hh:238
gem5::X86ISA::misc_reg::Mc1Ctl
@ Mc1Ctl
Definition
misc.hh:213
gem5::X86ISA::misc_reg::SysenterEip
@ SysenterEip
Definition
misc.hh:160
gem5::X86ISA::misc_reg::Ignne
@ Ignne
Definition
misc.hh:298
gem5::X86ISA::misc_reg::MtrrPhysBase5
@ MtrrPhysBase5
Definition
misc.hh:179
gem5::X86ISA::misc_reg::MtrrPhysMask3
@ MtrrPhysMask3
Definition
misc.hh:188
gem5::X86ISA::misc_reg::MtrrPhysMask6
@ MtrrPhysMask6
Definition
misc.hh:191
gem5::X86ISA::misc_reg::Syscfg
@ Syscfg
Definition
misc.hh:282
gem5::X86ISA::misc_reg::LastExceptionFromIp
@ LastExceptionFromIp
Definition
misc.hh:170
gem5::X86ISA::misc_reg::Mc2Addr
@ Mc2Addr
Definition
misc.hh:236
gem5::X86ISA::misc_reg::MtrrFix64k00000
@ MtrrFix64k00000
Definition
misc.hh:195
gem5::X86ISA::misc_reg::PerfEvtSel3
@ PerfEvtSel3
Definition
misc.hh:272
gem5::X86ISA::misc_reg::LastBranchToIp
@ LastBranchToIp
Definition
misc.hh:169
gem5::X86ISA::misc_reg::MtrrPhysMask5
@ MtrrPhysMask5
Definition
misc.hh:190
gem5::X86ISA::misc_reg::Mc5Ctl
@ Mc5Ctl
Definition
misc.hh:217
gem5::X86ISA::misc_reg::GsBase
@ GsBase
Definition
misc.hh:328
gem5::X86ISA::misc_reg::IorrMask0
@ IorrMask0
Definition
misc.hh:290
gem5::X86ISA::misc_reg::Mtrrcap
@ Mtrrcap
Definition
misc.hh:156
gem5::X86ISA::msrMap
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
gem5::X86ISA::MsrMap
std::unordered_map< Addr, RegIndex > MsrMap
Definition
msr.hh:43
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition
types.hh:84
gem5::X86ISA::msrMapSize
static const unsigned msrMapSize
Definition
msr.cc:145
gem5::X86ISA::MsrVal
MsrMap::value_type MsrVal
Definition
msr.cc:37
gem5::X86ISA::msrAddrToIndex
bool msrAddrToIndex(RegIndex ®_num, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition
msr.cc:150
gem5::X86ISA::msrMapData
const MsrMap::value_type msrMapData[]
Definition
msr.cc:39
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::RegIndex
uint16_t RegIndex
Definition
types.hh:176
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
Generated on Tue Jun 18 2024 16:24:00 for gem5 by
doxygen
1.11.0