gem5  v22.0.0.2
misc.hh
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37 
38 #ifndef __ARCH_X86_MISCREGS_HH__
39 #define __ARCH_X86_MISCREGS_HH__
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "arch/x86/x86_traits.hh"
43 #include "base/bitunion.hh"
44 #include "base/logging.hh"
45 
46 //These get defined in some system headers (at least termbits.h). That confuses
47 //things here significantly.
48 #undef CR0
49 #undef CR2
50 #undef CR3
51 
52 namespace gem5
53 {
54 namespace X86ISA
55 {
56 
58 {
59  CFBit = 1 << 0,
60  PFBit = 1 << 2,
61  ECFBit = 1 << 3,
62  AFBit = 1 << 4,
63  EZFBit = 1 << 5,
64  ZFBit = 1 << 6,
65  SFBit = 1 << 7,
66  DFBit = 1 << 10,
67  OFBit = 1 << 11
68 };
69 
70 constexpr uint32_t CfofMask = CFBit | OFBit;
71 constexpr uint32_t CcFlagMask = PFBit | AFBit | ZFBit | SFBit;
72 
74 {
75  TFBit = 1 << 8,
76  IFBit = 1 << 9,
77  NTBit = 1 << 14,
78  RFBit = 1 << 16,
79  VMBit = 1 << 17,
80  ACBit = 1 << 18,
81  VIFBit = 1 << 19,
82  VIPBit = 1 << 20,
83  IDBit = 1 << 21
84 };
85 
87 {
88  // Exception Flags
89  IEBit = 1 << 0,
90  DEBit = 1 << 1,
91  ZEBit = 1 << 2,
92  OEBit = 1 << 3,
93  UEBit = 1 << 4,
94  PEBit = 1 << 5,
95 
96  // !Exception Flags
97  StackFaultBit = 1 << 6,
98  ErrSummaryBit = 1 << 7,
99  CC0Bit = 1 << 8,
100  CC1Bit = 1 << 9,
101  CC2Bit = 1 << 10,
102  CC3Bit = 1 << 14,
103  BusyBit = 1 << 15,
104 };
105 
106 namespace misc_reg
107 {
108 
109 enum : RegIndex
110 {
111  // Control registers
112  // Most of these are invalid. See isValid() below.
130 
131  // Debug registers
141 
142  // Flags register
144 
145  //Register to keep handy values like the CPU mode in.
147 
148  /*
149  * Model Specific Registers
150  */
151  // Time stamp counter
153 
155 
159 
163 
165 
170 
181 
192 
204 
206 
208 
219 
230 
241 
252 
253  // Extended feature enable register
255 
259 
261 
263 
265 
272 
279 
281 
286 
291 
294 
299 
300  /*
301  * Segment registers
302  */
303  // Segment selectors
306  Cs,
307  Ss,
308  Ds,
309  Fs,
310  Gs,
311  Hs,
314  Ls,
315  Ms,
316  Tr,
318 
319  // Hidden segment base field
334 
335  // The effective segment base, ie what is actually added to an
336  // address. In 64 bit mode this can be different from the above,
337  // namely 0.
352 
353  // Hidden segment limit field
368 
369  // Hidden segment limit attributes
384 
385  // Floating point control registers
387 
398 
399  //XXX Add "Model-Specific Registers"
400 
402 
403  // "Fake" MSRs for internally implemented devices
405 
407 };
408 
409 static inline bool
411 {
412  return (index >= Cr0 && index < NumRegs &&
413  index != Cr1 &&
414  !(index > Cr4 && index < Cr8) &&
415  !(index > Cr8 && index <= Cr15));
416 }
417 
418 static inline RegIndex
419 cr(int index)
420 {
421  assert(index >= 0 && index < NumCRegs);
422  return CrBase + index;
423 }
424 
425 static inline RegIndex
426 dr(int index)
427 {
428  assert(index >= 0 && index < NumDRegs);
429  return DrBase + index;
430 }
431 
432 static inline RegIndex
434 {
435  assert(index >= 0 && index < (MtrrPhysBaseEnd - MtrrPhysBaseBase));
436  return MtrrPhysBaseBase + index;
437 }
438 
439 static inline RegIndex
441 {
442  assert(index >= 0 && index < (MtrrPhysMaskEnd - MtrrPhysMaskBase));
443  return MtrrPhysMaskBase + index;
444 }
445 
446 static inline RegIndex
448 {
449  assert(index >= 0 && index < (McCtlEnd - McCtlBase));
450  return McCtlBase + index;
451 }
452 
453 static inline RegIndex
455 {
456  assert(index >= 0 && index < (McStatusEnd - McStatusBase));
457  return McStatusBase + index;
458 }
459 
460 static inline RegIndex
462 {
463  assert(index >= 0 && index < (McAddrEnd - McAddrBase));
464  return McAddrBase + index;
465 }
466 
467 static inline RegIndex
469 {
470  assert(index >= 0 && index < (McMiscEnd - McMiscBase));
471  return McMiscBase + index;
472 }
473 
474 static inline RegIndex
476 {
477  assert(index >= 0 && index < (PerfEvtSelEnd - PerfEvtSelBase));
478  return PerfEvtSelBase + index;
479 }
480 
481 static inline RegIndex
483 {
484  assert(index >= 0 && index < (PerfEvtCtrEnd - PerfEvtCtrBase));
485  return PerfEvtCtrBase + index;
486 }
487 
488 static inline RegIndex
490 {
491  assert(index >= 0 && index < (IorrBaseEnd - IorrBaseBase));
492  return IorrBaseBase + index;
493 }
494 
495 static inline RegIndex
497 {
498  assert(index >= 0 && index < (IorrMaskEnd - IorrMaskBase));
499  return IorrMaskBase + index;
500 }
501 
502 static inline RegIndex
504 {
505  assert(index >= 0 && index < segment_idx::NumIdxs);
506  return SegSelBase + index;
507 }
508 
509 static inline RegIndex
511 {
512  assert(index >= 0 && index < segment_idx::NumIdxs);
513  return SegBaseBase + index;
514 }
515 
516 static inline RegIndex
518 {
519  assert(index >= 0 && index < segment_idx::NumIdxs);
520  return SegEffBaseBase + index;
521 }
522 
523 static inline RegIndex
525 {
526  assert(index >= 0 && index < segment_idx::NumIdxs);
527  return SegLimitBase + index;
528 }
529 
530 static inline RegIndex
532 {
533  assert(index >= 0 && index < segment_idx::NumIdxs);
534  return SegAttrBase + index;
535 }
536 
537 } // namespace misc_reg
538 
543 BitUnion64(CCFlagBits)
544  Bitfield<11> of;
545  Bitfield<7> sf;
546  Bitfield<6> zf;
547  Bitfield<5> ezf;
548  Bitfield<4> af;
549  Bitfield<3> ecf;
550  Bitfield<2> pf;
551  Bitfield<0> cf;
552 EndBitUnion(CCFlagBits)
553 
554 
557 BitUnion64(RFLAGS)
558  Bitfield<21> id; // ID Flag
559  Bitfield<20> vip; // Virtual Interrupt Pending
560  Bitfield<19> vif; // Virtual Interrupt Flag
561  Bitfield<18> ac; // Alignment Check
562  Bitfield<17> vm; // Virtual-8086 Mode
563  Bitfield<16> rf; // Resume Flag
564  Bitfield<14> nt; // Nested Task
565  Bitfield<13, 12> iopl; // I/O Privilege Level
566  Bitfield<11> of; // Overflow Flag
567  Bitfield<10> df; // Direction Flag
568  Bitfield<9> intf; // Interrupt Flag
569  Bitfield<8> tf; // Trap Flag
570  Bitfield<7> sf; // Sign Flag
571  Bitfield<6> zf; // Zero Flag
572  Bitfield<4> af; // Auxiliary Flag
573  Bitfield<2> pf; // Parity Flag
574  Bitfield<0> cf; // Carry Flag
575 EndBitUnion(RFLAGS)
576 
577 BitUnion64(HandyM5Reg)
578  Bitfield<0> mode;
579  Bitfield<3, 1> submode;
580  Bitfield<5, 4> cpl;
581  Bitfield<6> paging;
582  Bitfield<7> prot;
583  Bitfield<9, 8> defOp;
584  Bitfield<11, 10> altOp;
585  Bitfield<13, 12> defAddr;
586  Bitfield<15, 14> altAddr;
587  Bitfield<17, 16> stack;
588 EndBitUnion(HandyM5Reg)
589 
590 
593 BitUnion64(CR0)
594  Bitfield<31> pg; // Paging
595  Bitfield<30> cd; // Cache Disable
596  Bitfield<29> nw; // Not Writethrough
597  Bitfield<18> am; // Alignment Mask
598  Bitfield<16> wp; // Write Protect
599  Bitfield<5> ne; // Numeric Error
600  Bitfield<4> et; // Extension Type
601  Bitfield<3> ts; // Task Switched
602  Bitfield<2> em; // Emulation
603  Bitfield<1> mp; // Monitor Coprocessor
604  Bitfield<0> pe; // Protection Enabled
605 EndBitUnion(CR0)
606 
607 // Page Fault Virtual Address
608 BitUnion64(CR2)
609  Bitfield<31, 0> legacy;
610 EndBitUnion(CR2)
611 
612 BitUnion64(CR3)
613  Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
614  // Base Address
615  Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
616  // Base Address
617  Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
618  // Base Address
619  Bitfield<4> pcd; // Page-Level Cache Disable
620  Bitfield<3> pwt; // Page-Level Writethrough
621 EndBitUnion(CR3)
622 
623 BitUnion64(CR4)
624  Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
625  Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
626  // WRGSBASE instructions
627  Bitfield<10> osxmmexcpt; // Operating System Unmasked
628  // Exception Support
629  Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
630  Bitfield<8> pce; // Performance-Monitoring Counter Enable
631  Bitfield<7> pge; // Page-Global Enable
632  Bitfield<6> mce; // Machine Check Enable
633  Bitfield<5> pae; // Physical-Address Extension
634  Bitfield<4> pse; // Page Size Extensions
635  Bitfield<3> de; // Debugging Extensions
636  Bitfield<2> tsd; // Time Stamp Disable
637  Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
638  Bitfield<0> vme; // Virtual-8086 Mode Extensions
639 EndBitUnion(CR4)
640 
641 BitUnion64(CR8)
642  Bitfield<3, 0> tpr; // Task Priority Register
643 EndBitUnion(CR8)
644 
645 BitUnion64(DR6)
646  Bitfield<0> b0;
647  Bitfield<1> b1;
648  Bitfield<2> b2;
649  Bitfield<3> b3;
650  Bitfield<13> bd;
651  Bitfield<14> bs;
652  Bitfield<15> bt;
653 EndBitUnion(DR6)
654 
655 BitUnion64(DR7)
656  Bitfield<0> l0;
657  Bitfield<1> g0;
658  Bitfield<2> l1;
659  Bitfield<3> g1;
660  Bitfield<4> l2;
661  Bitfield<5> g2;
662  Bitfield<6> l3;
663  Bitfield<7> g3;
664  Bitfield<8> le;
665  Bitfield<9> ge;
666  Bitfield<13> gd;
667  Bitfield<17, 16> rw0;
668  Bitfield<19, 18> len0;
669  Bitfield<21, 20> rw1;
670  Bitfield<23, 22> len1;
671  Bitfield<25, 24> rw2;
672  Bitfield<27, 26> len2;
673  Bitfield<29, 28> rw3;
674  Bitfield<31, 30> len3;
675 EndBitUnion(DR7)
676 
677 // MTRR capabilities
678 BitUnion64(MTRRcap)
679  Bitfield<7, 0> vcnt; // Variable-Range Register Count
680  Bitfield<8> fix; // Fixed-Range Registers
681  Bitfield<10> wc; // Write-Combining
682 EndBitUnion(MTRRcap)
683 
687 BitUnion64(SysenterCS)
688  Bitfield<15, 0> targetCS;
689 EndBitUnion(SysenterCS)
690 
691 BitUnion64(SysenterESP)
692  Bitfield<31, 0> targetESP;
693 EndBitUnion(SysenterESP)
694 
695 BitUnion64(SysenterEIP)
696  Bitfield<31, 0> targetEIP;
697 EndBitUnion(SysenterEIP)
698 
703  Bitfield<7, 0> count; // Number of error reporting register banks
704  Bitfield<8> MCGCP; // MCG_CTL register present.
706 
708  Bitfield<0> ripv; // Restart-IP valid
709  Bitfield<1> eipv; // Error-IP valid
710  Bitfield<2> mcip; // Machine check in-progress
712 
714  Bitfield<0> lbr; // Last-branch record
715  Bitfield<1> btf; // Branch single step
716  Bitfield<2> pb0; // Performance monitoring pin control 0
717  Bitfield<3> pb1; // Performance monitoring pin control 1
718  Bitfield<4> pb2; // Performance monitoring pin control 2
719  Bitfield<5> pb3; // Performance monitoring pin control 3
720  /*uint64_t pb(int index)
721  {
722  return bits(__data, index + 2);
723  }*/
725 
726 BitUnion64(MtrrPhysBase)
727  Bitfield<7, 0> type; // Default memory type
728  Bitfield<51, 12> physbase; // Range physical base address
729 EndBitUnion(MtrrPhysBase)
730 
731 BitUnion64(MtrrPhysMask)
732  Bitfield<11> valid; // MTRR pair enable
733  Bitfield<51, 12> physmask; // Range physical mask
734 EndBitUnion(MtrrPhysMask)
735 
736 BitUnion64(MtrrFixed)
737  /*uint64_t type(int index)
738  {
739  return bits(__data, index * 8 + 7, index * 8);
740  }*/
741 EndBitUnion(MtrrFixed)
742 
744  /*uint64_t pa(int index)
745  {
746  return bits(__data, index * 8 + 2, index * 8);
747  }*/
749 
750 BitUnion64(MtrrDefType)
751  Bitfield<7, 0> type; // Default type
752  Bitfield<10> fe; // Fixed range enable
753  Bitfield<11> e; // MTRR enable
754 EndBitUnion(MtrrDefType)
755 
759 BitUnion64(McStatus)
760  Bitfield<15,0> mcaErrorCode;
761  Bitfield<31,16> modelSpecificCode;
762  Bitfield<56,32> otherInfo;
763  Bitfield<57> pcc; // Processor-context corrupt
764  Bitfield<58> addrv; // Error-address register valid
765  Bitfield<59> miscv; // Miscellaneous-error register valid
766  Bitfield<60> en; // Error condition enabled
767  Bitfield<61> uc; // Uncorrected error
768  Bitfield<62> over; // Status register overflow
769  Bitfield<63> val; // Valid
770 EndBitUnion(McStatus)
771 
772 BitUnion64(McCtl)
773  /*uint64_t en(int index)
774  {
775  return bits(__data, index);
776  }*/
777 EndBitUnion(McCtl)
778 
779 // Extended feature enable register
781  Bitfield<0> sce; // System call extensions
782  Bitfield<8> lme; // Long mode enable
783  Bitfield<10> lma; // Long mode active
784  Bitfield<11> nxe; // No-execute enable
785  Bitfield<12> svme; // Secure virtual machine enable
786  Bitfield<14> ffxsr; // Fast fxsave/fxrstor
788 
790  Bitfield<31,0> targetEip;
791  Bitfield<47,32> syscallCsAndSs;
792  Bitfield<63,48> sysretCsAndSs;
794 
796  Bitfield<31,0> mask;
798 
799 BitUnion64(PerfEvtSel)
800  Bitfield<7,0> eventMask;
801  Bitfield<15,8> unitMask;
802  Bitfield<16> usr; // User mode
803  Bitfield<17> os; // Operating-system mode
804  Bitfield<18> e; // Edge detect
805  Bitfield<19> pc; // Pin control
806  Bitfield<20> intEn; // Interrupt enable
807  Bitfield<22> en; // Counter enable
808  Bitfield<23> inv; // Invert mask
809  Bitfield<31,24> counterMask;
810 EndBitUnion(PerfEvtSel)
811 
813  Bitfield<18> mfde; // MtrrFixDramEn
814  Bitfield<19> mfdm; // MtrrFixDramModEn
815  Bitfield<20> mvdm; // MtrrVarDramEn
816  Bitfield<21> tom2; // MtrrTom2En
818 
819 BitUnion64(IorrBase)
820  Bitfield<3> wr; // WrMem Enable
821  Bitfield<4> rd; // RdMem Enable
822  Bitfield<51,12> physbase; // Range physical base address
823 EndBitUnion(IorrBase)
824 
825 BitUnion64(IorrMask)
826  Bitfield<11> v; // I/O register pair enable (valid)
827  Bitfield<51,12> physmask; // Range physical mask
828 EndBitUnion(IorrMask)
829 
830 BitUnion64(Tom)
831  Bitfield<51,23> physAddr; // Top of memory physical address
832 EndBitUnion(Tom)
833 
834 BitUnion64(VmCrMsr)
835  Bitfield<0> dpd;
836  Bitfield<1> rInit;
837  Bitfield<2> disA20M;
838 EndBitUnion(VmCrMsr)
839 
840 BitUnion64(IgnneMsr)
841  Bitfield<0> ignne;
842 EndBitUnion(IgnneMsr)
843 
844 BitUnion64(SmmCtlMsr)
845  Bitfield<0> dismiss;
846  Bitfield<1> enter;
847  Bitfield<2> smiCycle;
848  Bitfield<3> exit;
849  Bitfield<4> rsmCycle;
850 EndBitUnion(SmmCtlMsr)
851 
855 BitUnion64(SegSelector)
856  // The following bitfield is not defined in the ISA, but it's useful
857  // when checking selectors in larger data types to make sure they
858  // aren't too large.
859  Bitfield<63, 3> esi; // Extended selector
860  Bitfield<15, 3> si; // Selector Index
861  Bitfield<2> ti; // Table Indicator
862  Bitfield<1, 0> rpl; // Requestor Privilege Level
863 EndBitUnion(SegSelector)
864 
869 class SegDescriptorBase
870 {
871  public:
872  uint32_t
873  getter(const uint64_t &storage) const
874  {
875  return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16);
876  }
877 
878  void
879  setter(uint64_t &storage, uint32_t base)
880  {
881  replaceBits(storage, 63, 56, bits(base, 31, 24));
882  replaceBits(storage, 39, 16, bits(base, 23, 0));
883  }
884 };
885 
887 {
888  public:
889  uint32_t
890  getter(const uint64_t &storage) const
891  {
892  uint32_t limit = (bits(storage, 51, 48) << 16) |
893  bits(storage, 15, 0);
894  if (bits(storage, 55))
895  limit = (limit << 12) | mask(12);
896  return limit;
897  }
898 
899  void
900  setter(uint64_t &storage, uint32_t limit)
901  {
902  bool g = (bits(limit, 31, 24) != 0);
903  panic_if(g && bits(limit, 11, 0) != mask(12),
904  "Inlimitid segment limit %#x", limit);
905  if (g)
906  limit = limit >> 12;
907  replaceBits(storage, 51, 48, bits(limit, 23, 16));
908  replaceBits(storage, 15, 0, bits(limit, 15, 0));
909  replaceBits(storage, 55, g ? 1 : 0);
910  }
911 };
912 
913 BitUnion64(SegDescriptor)
914  Bitfield<63, 56> baseHigh;
915  Bitfield<39, 16> baseLow;
916  BitfieldType<SegDescriptorBase> base;
917  Bitfield<55> g; // Granularity
918  Bitfield<54> d; // Default Operand Size
919  Bitfield<54> b; // Default Operand Size
920  Bitfield<53> l; // Long Attribute Bit
921  Bitfield<52> avl; // Available To Software
922  Bitfield<51, 48> limitHigh;
923  Bitfield<15, 0> limitLow;
925  Bitfield<47> p; // Present
926  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
927  Bitfield<44> s; // System
928  SubBitUnion(type, 43, 40)
929  // Specifies whether this descriptor is for code or data.
930  Bitfield<43> codeOrData;
931 
932  // These bit fields are for code segments
933  Bitfield<42> c; // Conforming
934  Bitfield<41> r; // Readable
935 
936  // These bit fields are for data segments
937  Bitfield<42> e; // Expand-Down
938  Bitfield<41> w; // Writable
939 
940  // This is used for both code and data segments.
941  Bitfield<40> a; // Accessed
943 EndBitUnion(SegDescriptor)
944 
949 BitUnion64(TSSlow)
950  Bitfield<63, 56> baseHigh;
951  Bitfield<39, 16> baseLow;
952  BitfieldType<SegDescriptorBase> base;
953  Bitfield<55> g; // Granularity
954  Bitfield<52> avl; // Available To Software
955  Bitfield<51, 48> limitHigh;
956  Bitfield<15, 0> limitLow;
958  Bitfield<47> p; // Present
959  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
960  SubBitUnion(type, 43, 40)
961  // Specifies whether this descriptor is for code or data.
962  Bitfield<43> codeOrData;
963 
964  // These bit fields are for code segments
965  Bitfield<42> c; // Conforming
966  Bitfield<41> r; // Readable
967 
968  // These bit fields are for data segments
969  Bitfield<42> e; // Expand-Down
970  Bitfield<41> w; // Writable
971 
972  // This is used for both code and data segments.
973  Bitfield<40> a; // Accessed
975 EndBitUnion(TSSlow)
976 
981 BitUnion64(TSShigh)
982  Bitfield<31, 0> base;
983 EndBitUnion(TSShigh)
984 
985 BitUnion64(SegAttr)
986  Bitfield<1, 0> dpl;
987  Bitfield<2> unusable;
988  Bitfield<3> defaultSize;
989  Bitfield<4> longMode;
990  Bitfield<5> avl;
991  Bitfield<6> granularity;
992  Bitfield<7> present;
993  Bitfield<11, 8> type;
994  Bitfield<12> writable;
995  Bitfield<13> readable;
996  Bitfield<14> expandDown;
997  Bitfield<15> system;
998 EndBitUnion(SegAttr)
999 
1000 BitUnion64(GateDescriptor)
1001  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1002  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1003  Bitfield<31, 16> selector; // Target Code-Segment Selector
1004  Bitfield<47> p; // Present
1005  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1006  Bitfield<43, 40> type;
1007  Bitfield<36, 32> count; // Parameter Count
1008 EndBitUnion(GateDescriptor)
1009 
1013 BitUnion64(GateDescriptorLow)
1014  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1015  Bitfield<47> p; // Present
1016  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1017  Bitfield<43, 40> type;
1018  Bitfield<35, 32> IST; // IST pointer to TSS, new stack for exceptions
1019  Bitfield<31, 16> selector; // Target Code-Segment Selector
1020  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1021 EndBitUnion(GateDescriptorLow)
1022 
1023 BitUnion64(GateDescriptorHigh)
1024  Bitfield<31, 0> offset; // Target Code-Segment Offset
1025 EndBitUnion(GateDescriptorHigh)
1026 
1030 BitUnion64(GDTR)
1031 EndBitUnion(GDTR)
1032 
1033 BitUnion64(IDTR)
1034 EndBitUnion(IDTR)
1035 
1036 BitUnion64(LDTR)
1037 EndBitUnion(LDTR)
1038 
1042 BitUnion64(TR)
1043 EndBitUnion(TR)
1044 
1045 
1049 BitUnion64(LocalApicBase)
1050  Bitfield<51, 12> base;
1051  Bitfield<11> enable;
1052  Bitfield<8> bsp;
1053 EndBitUnion(LocalApicBase)
1054 
1055 } // namespace X86ISA
1056 } // namespace gem5
1057 
1058 #endif // __ARCH_X86_INTREGS_HH__
gem5::X86ISA::intf
Bitfield< 9 > intf
Definition: misc.hh:568
gem5::X86ISA::tom2
Bitfield< 21 > tom2
Definition: misc.hh:816
gem5::X86ISA::misc_reg::DefType
@ DefType
Definition: misc.hh:207
gem5::X86ISA::misc_reg::Mc0Status
@ Mc0Status
Definition: misc.hh:221
gem5::X86ISA::misc_reg::Lstar
@ Lstar
Definition: misc.hh:257
gem5::X86ISA::IST
Bitfield< 35, 32 > IST
Definition: misc.hh:1018
gem5::X86ISA::misc_reg::MtrrFix4kD0000
@ MtrrFix4kD0000
Definition: misc.hh:198
gem5::X86ISA::mask
mask
Definition: misc.hh:796
gem5::X86ISA::iopl
Bitfield< 13, 12 > iopl
Definition: misc.hh:565
gem5::X86ISA::misc_reg::mcStatus
static RegIndex mcStatus(int index)
Definition: misc.hh:454
gem5::X86ISA::misc_reg::Dr7
@ Dr7
Definition: misc.hh:140
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:805
gem5::X86ISA::DFBit
@ DFBit
Definition: misc.hh:66
gem5::X86ISA::misc_reg::McCtlEnd
@ McCtlEnd
Definition: misc.hh:218
gem5::X86ISA::targetEIP
targetEIP
Definition: misc.hh:696
gem5::X86ISA::fe
Bitfield< 10 > fe
Definition: misc.hh:752
gem5::X86ISA::misc_reg::Ftag
@ Ftag
Definition: misc.hh:392
gem5::X86ISA::misc_reg::PerfEvtCtr3
@ PerfEvtCtr3
Definition: misc.hh:277
gem5::X86ISA::misc_reg::Ms
@ Ms
Definition: misc.hh:315
x86_traits.hh
gem5::X86ISA::misc_reg::Mc1Misc
@ Mc1Misc
Definition: misc.hh:244
gem5::X86ISA::SFBit
@ SFBit
Definition: misc.hh:65
gem5::X86ISA::longMode
Bitfield< 4 > longMode
Definition: misc.hh:989
gem5::X86ISA::bt
Bitfield< 15 > bt
Definition: misc.hh:652
gem5::X86ISA::misc_reg::PerfEvtSel2
@ PerfEvtSel2
Definition: misc.hh:269
gem5::X86ISA::misc_reg::TslAttr
@ TslAttr
Definition: misc.hh:378
gem5::X86ISA::pcc
Bitfield< 57 > pcc
Definition: misc.hh:763
gem5::X86ISA::CcFlagMask
constexpr uint32_t CcFlagMask
Definition: misc.hh:71
gem5::X86ISA::misc_reg::DebugCtlMsr
@ DebugCtlMsr
Definition: misc.hh:164
gem5::X86ISA::misc_reg::Mc6Status
@ Mc6Status
Definition: misc.hh:227
gem5::X86ISA::pvi
Bitfield< 1 > pvi
Definition: misc.hh:637
gem5::X86ISA::misc_reg::TslEffBase
@ TslEffBase
Definition: misc.hh:346
gem5::X86ISA::misc_reg::Mc1Addr
@ Mc1Addr
Definition: misc.hh:233
gem5::X86ISA::misc_reg::Ftw
@ Ftw
Definition: misc.hh:391
gem5::X86ISA::misc_reg::Star
@ Star
Definition: misc.hh:256
gem5::X86ISA::misc_reg::Fioff
@ Fioff
Definition: misc.hh:394
gem5::X86ISA::misc_reg::MsLimit
@ MsLimit
Definition: misc.hh:365
gem5::X86ISA::cpl
Bitfield< 5, 4 > cpl
Definition: misc.hh:580
gem5::X86ISA::misc_reg::PciConfigAddress
@ PciConfigAddress
Definition: misc.hh:404
gem5::X86ISA::misc_reg::SegSelBase
@ SegSelBase
Definition: misc.hh:304
gem5::X86ISA::misc_reg::PerfEvtCtr2
@ PerfEvtCtr2
Definition: misc.hh:276
gem5::X86ISA::IDBit
@ IDBit
Definition: misc.hh:83
gem5::X86ISA::misc_reg::Mc2Status
@ Mc2Status
Definition: misc.hh:223
gem5::X86ISA::misc_reg::Mc2Addr
@ Mc2Addr
Definition: misc.hh:234
gem5::X86ISA::paging
Bitfield< 6 > paging
Definition: misc.hh:581
gem5::X86ISA::misc_reg::MsAttr
@ MsAttr
Definition: misc.hh:381
gem5::X86ISA::l3
Bitfield< 6 > l3
Definition: misc.hh:662
gem5::X86ISA::misc_reg::MtrrPhysBaseBase
@ MtrrPhysBaseBase
Definition: misc.hh:171
gem5::X86ISA::mode
Bitfield< 3 > mode
Definition: types.hh:192
gem5::X86ISA::ZEBit
@ ZEBit
Definition: misc.hh:91
gem5::X86ISA::misc_reg::MtrrFix4kE8000
@ MtrrFix4kE8000
Definition: misc.hh:201
gem5::X86ISA::e
Bitfield< 11 > e
Definition: misc.hh:753
gem5::X86ISA::zf
Bitfield< 6 > zf
Definition: misc.hh:546
gem5::X86ISA::misc_reg::GsAttr
@ GsAttr
Definition: misc.hh:376
gem5::X86ISA::misc_reg::PerfEvtSel0
@ PerfEvtSel0
Definition: misc.hh:267
gem5::X86ISA::rw3
Bitfield< 29, 28 > rw3
Definition: misc.hh:673
gem5::X86ISA::mvdm
Bitfield< 20 > mvdm
Definition: misc.hh:815
gem5::X86ISA::misc_reg::Mc1Ctl
@ Mc1Ctl
Definition: misc.hh:211
gem5::X86ISA::IEBit
@ IEBit
Definition: misc.hh:89
gem5::X86ISA::mce
Bitfield< 6 > mce
Definition: misc.hh:632
gem5::X86ISA::defOp
Bitfield< 9, 8 > defOp
Definition: misc.hh:583
gem5::X86ISA::misc_reg::MtrrFix4kC0000
@ MtrrFix4kC0000
Definition: misc.hh:196
gem5::X86ISA::misc_reg::FsAttr
@ FsAttr
Definition: misc.hh:375
gem5::X86ISA::misc_reg::HsAttr
@ HsAttr
Definition: misc.hh:377
gem5::X86ISA::misc_reg::McStatusBase
@ McStatusBase
Definition: misc.hh:220
gem5::X86ISA::misc_reg::KernelGsBase
@ KernelGsBase
Definition: misc.hh:262
gem5::X86ISA::misc_reg::MtrrPhysBaseEnd
@ MtrrPhysBaseEnd
Definition: misc.hh:180
gem5::X86ISA::CC2Bit
@ CC2Bit
Definition: misc.hh:101
gem5::X86ISA::df
Bitfield< 10 > df
Definition: misc.hh:567
gem5::X86ISA::MCGCP
Bitfield< 8 > MCGCP
Definition: misc.hh:704
gem5::X86ISA::ErrSummaryBit
@ ErrSummaryBit
Definition: misc.hh:98
gem5::X86ISA::misc_reg::dr
static RegIndex dr(int index)
Definition: misc.hh:426
gem5::X86ISA::len3
Bitfield< 31, 30 > len3
Definition: misc.hh:674
gem5::X86ISA::misc_reg::PerfEvtCtr1
@ PerfEvtCtr1
Definition: misc.hh:275
gem5::X86ISA::misc_reg::M5Reg
@ M5Reg
Definition: misc.hh:146
gem5::X86ISA::wc
Bitfield< 10 > wc
Definition: misc.hh:681
gem5::X86ISA::len1
Bitfield< 23, 22 > len1
Definition: misc.hh:670
gem5::X86ISA::misc_reg::Mc2Misc
@ Mc2Misc
Definition: misc.hh:245
gem5::X86ISA::misc_reg::Mc5Status
@ Mc5Status
Definition: misc.hh:226
gem5::X86ISA::misc_reg::TopMem
@ TopMem
Definition: misc.hh:292
gem5::X86ISA::ZFBit
@ ZFBit
Definition: misc.hh:64
gem5::X86ISA::misc_reg::Mc0Addr
@ Mc0Addr
Definition: misc.hh:232
gem5::X86ISA::pb3
Bitfield< 5 > pb3
Definition: misc.hh:719
gem5::X86ISA::misc_reg::Ss
@ Ss
Definition: misc.hh:307
gem5::X86ISA::misc_reg::Dr6
@ Dr6
Definition: misc.hh:139
gem5::X86ISA::CC0Bit
@ CC0Bit
Definition: misc.hh:99
gem5::X86ISA::misc_reg::McgStatus
@ McgStatus
Definition: misc.hh:161
gem5::X86ISA::g2
Bitfield< 5 > g2
Definition: misc.hh:661
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::X86ISA::misc_reg::CsBase
@ CsBase
Definition: misc.hh:322
gem5::X86ISA::misc_reg::CsLimit
@ CsLimit
Definition: misc.hh:356
gem5::X86ISA::v
Bitfield< 6, 3 > v
Definition: types.hh:125
gem5::SparcISA::id
Bitfield< 11 > id
Definition: misc.hh:124
gem5::X86ISA::b
Bitfield< 54 > b
Definition: misc.hh:919
gem5::X86ISA::mcip
Bitfield< 2 > mcip
Definition: misc.hh:710
gem5::X86ISA::misc_reg::Mc5Ctl
@ Mc5Ctl
Definition: misc.hh:215
gem5::X86ISA::misc_reg::MtrrPhysMask1
@ MtrrPhysMask1
Definition: misc.hh:184
gem5::X86ISA::NumDRegs
const int NumDRegs
Definition: x86_traits.hh:57
gem5::X86ISA::offset
offset
Definition: misc.hh:1024
gem5::X86ISA::misc_reg::Cr6
@ Cr6
Definition: misc.hh:120
gem5::X86ISA::pge
Bitfield< 7 > pge
Definition: misc.hh:631
gem5::X86ISA::misc_reg::DsEffBase
@ DsEffBase
Definition: misc.hh:342
gem5::X86ISA::baseHigh
baseHigh
Definition: misc.hh:914
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::X86ISA::misc_reg::McgCtl
@ McgCtl
Definition: misc.hh:162
gem5::X86ISA::misc_reg::mcMisc
static RegIndex mcMisc(int index)
Definition: misc.hh:468
gem5::X86ISA::misc_reg::Tr
@ Tr
Definition: misc.hh:316
gem5::X86ISA::misc_reg::McAddrBase
@ McAddrBase
Definition: misc.hh:231
gem5::X86ISA::misc_reg::segEffBase
static RegIndex segEffBase(int index)
Definition: misc.hh:517
gem5::X86ISA::g3
Bitfield< 7 > g3
Definition: misc.hh:663
gem5::X86ISA::osxmmexcpt
Bitfield< 10 > osxmmexcpt
Definition: misc.hh:627
gem5::X86ISA::SegDescriptorLimit
Definition: misc.hh:886
gem5::X86ISA::ACBit
@ ACBit
Definition: misc.hh:80
gem5::X86ISA::le
Bitfield< 8 > le
Definition: misc.hh:664
gem5::X86ISA::misc_reg::ApicBase
@ ApicBase
Definition: misc.hh:401
gem5::X86ISA::misc_reg::MtrrFix64k00000
@ MtrrFix64k00000
Definition: misc.hh:193
gem5::X86ISA::misc_reg::Cr1
@ Cr1
Definition: misc.hh:115
gem5::X86ISA::smiCycle
Bitfield< 2 > smiCycle
Definition: misc.hh:847
gem5::X86ISA::misc_reg::IorrMaskBase
@ IorrMaskBase
Definition: misc.hh:287
gem5::X86ISA::defaultSize
Bitfield< 3 > defaultSize
Definition: misc.hh:988
gem5::X86ISA::of
Bitfield< 11 > of
Definition: misc.hh:566
gem5::X86ISA::pb1
Bitfield< 3 > pb1
Definition: misc.hh:717
gem5::X86ISA::b2
Bitfield< 2 > b2
Definition: misc.hh:648
gem5::X86ISA::misc_reg::segAttr
static RegIndex segAttr(int index)
Definition: misc.hh:531
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:997
gem5::X86ISA::l
Bitfield< 53 > l
Definition: misc.hh:920
gem5::X86ISA::misc_reg::Mc7Misc
@ Mc7Misc
Definition: misc.hh:250
gem5::X86ISA::rw0
Bitfield< 17, 16 > rw0
Definition: misc.hh:667
gem5::X86ISA::vcnt
vcnt
Definition: misc.hh:679
gem5::X86ISA::pb2
Bitfield< 4 > pb2
Definition: misc.hh:718
gem5::X86ISA::tpr
tpr
Definition: misc.hh:642
gem5::X86ISA::misc_reg::Fcw
@ Fcw
Definition: misc.hh:389
gem5::X86ISA::limit
BitfieldType< SegDescriptorLimit > limit
Definition: misc.hh:924
gem5::X86ISA::misc_reg::Cr9
@ Cr9
Definition: misc.hh:123
gem5::X86ISA::UEBit
@ UEBit
Definition: misc.hh:93
gem5::X86ISA::misc_reg::LsBase
@ LsBase
Definition: misc.hh:330
gem5::X86ISA::len0
Bitfield< 19, 18 > len0
Definition: misc.hh:668
gem5::X86ISA::rInit
Bitfield< 1 > rInit
Definition: misc.hh:836
gem5::X86ISA::misc_reg::DsBase
@ DsBase
Definition: misc.hh:324
gem5::X86ISA::rf
Bitfield< 16 > rf
Definition: misc.hh:563
gem5::X86ISA::misc_reg::Mc5Misc
@ Mc5Misc
Definition: misc.hh:248
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::X86ISA::misc_reg::Dr5
@ Dr5
Definition: misc.hh:138
gem5::X86ISA::misc_reg::MtrrPhysBase3
@ MtrrPhysBase3
Definition: misc.hh:175
gem5::X86ISA::misc_reg::CsEffBase
@ CsEffBase
Definition: misc.hh:340
gem5::X86ISA::misc_reg::Mc7Ctl
@ Mc7Ctl
Definition: misc.hh:217
gem5::X86ISA::misc_reg::SegLimitBase
@ SegLimitBase
Definition: misc.hh:354
gem5::X86ISA::misc_reg::LsEffBase
@ LsEffBase
Definition: misc.hh:348
gem5::X86ISA::misc_reg::GsLimit
@ GsLimit
Definition: misc.hh:360
gem5::X86ISA::SegDescriptorLimit::setter
void setter(uint64_t &storage, uint32_t limit)
Definition: misc.hh:900
gem5::X86ISA::ne
Bitfield< 5 > ne
Definition: misc.hh:599
gem5::X86ISA::defAddr
Bitfield< 13, 12 > defAddr
Definition: misc.hh:585
gem5::X86ISA::VIPBit
@ VIPBit
Definition: misc.hh:82
gem5::X86ISA::bs
Bitfield< 14 > bs
Definition: misc.hh:651
gem5::X86ISA::misc_reg::MtrrFix16kA0000
@ MtrrFix16kA0000
Definition: misc.hh:195
gem5::X86ISA::misc_reg::LastExceptionToIp
@ LastExceptionToIp
Definition: misc.hh:169
gem5::X86ISA::misc_reg::MtrrFix4kD8000
@ MtrrFix4kD8000
Definition: misc.hh:199
gem5::X86ISA::misc_reg::MtrrPhysBase7
@ MtrrPhysBase7
Definition: misc.hh:179
gem5::X86ISA::ts
Bitfield< 3 > ts
Definition: misc.hh:601
gem5::X86ISA::misc_reg::Cstar
@ Cstar
Definition: misc.hh:258
gem5::X86ISA::altAddr
Bitfield< 15, 14 > altAddr
Definition: misc.hh:586
gem5::X86ISA::lma
Bitfield< 10 > lma
Definition: misc.hh:783
gem5::X86ISA::misc_reg::Ignne
@ Ignne
Definition: misc.hh:296
gem5::X86ISA::misc_reg::SsEffBase
@ SsEffBase
Definition: misc.hh:341
gem5::X86ISA::misc_reg::Dr1
@ Dr1
Definition: misc.hh:134
gem5::X86ISA::wp
Bitfield< 16 > wp
Definition: misc.hh:598
gem5::X86ISA::writable
Bitfield< 12 > writable
Definition: misc.hh:994
gem5::X86ISA::BusyBit
@ BusyBit
Definition: misc.hh:103
gem5::X86ISA::tsd
Bitfield< 2 > tsd
Definition: misc.hh:636
gem5::X86ISA::misc_reg::Dr0
@ Dr0
Definition: misc.hh:133
gem5::X86ISA::fsgsbase
Bitfield< 16 > fsgsbase
Definition: misc.hh:625
gem5::X86ISA::misc_reg::Cr15
@ Cr15
Definition: misc.hh:129
gem5::X86ISA::VIFBit
@ VIFBit
Definition: misc.hh:81
gem5::X86ISA::b3
Bitfield< 3 > b3
Definition: misc.hh:649
gem5::X86ISA::misc_reg::SfMask
@ SfMask
Definition: misc.hh:260
gem5::X86ISA::uc
Bitfield< 61 > uc
Definition: misc.hh:767
gem5::X86ISA::misc_reg::TsgEffBase
@ TsgEffBase
Definition: misc.hh:347
gem5::X86ISA::misc_reg::Dr2
@ Dr2
Definition: misc.hh:135
gem5::X86ISA::misc_reg::TsgBase
@ TsgBase
Definition: misc.hh:329
gem5::X86ISA::CondFlagBit
CondFlagBit
Definition: misc.hh:57
gem5::X86ISA::misc_reg::CrBase
@ CrBase
Definition: misc.hh:113
gem5::X86ISA::en
Bitfield< 60 > en
Definition: misc.hh:766
gem5::X86ISA::DEBit
@ DEBit
Definition: misc.hh:90
gem5::X86ISA::misc_reg::McMiscEnd
@ McMiscEnd
Definition: misc.hh:251
gem5::X86ISA::OEBit
@ OEBit
Definition: misc.hh:92
gem5::X86ISA::misc_reg::McStatusEnd
@ McStatusEnd
Definition: misc.hh:229
gem5::X86ISA::readable
Bitfield< 13 > readable
Definition: misc.hh:995
gem5::X86ISA::misc_reg::IorrBase1
@ IorrBase1
Definition: misc.hh:284
gem5::X86ISA::misc_reg::segSel
static RegIndex segSel(int index)
Definition: misc.hh:503
gem5::X86ISA::ge
Bitfield< 9 > ge
Definition: misc.hh:665
gem5::X86ISA::misc_reg::isValid
static bool isValid(int index)
Definition: misc.hh:410
gem5::X86ISA::nxe
Bitfield< 11 > nxe
Definition: misc.hh:784
gem5::X86ISA::RFBit
@ RFBit
Definition: misc.hh:78
gem5::X86ISA::altOp
Bitfield< 11, 10 > altOp
Definition: misc.hh:584
gem5::X86ISA::misc_reg::Mc3Addr
@ Mc3Addr
Definition: misc.hh:235
gem5::X86ISA::misc_reg::SegEffBaseBase
@ SegEffBaseBase
Definition: misc.hh:338
gem5::X86ISA::misc_reg::TrAttr
@ TrAttr
Definition: misc.hh:382
gem5::X86ISA::misc_reg::PerfEvtCtrEnd
@ PerfEvtCtrEnd
Definition: misc.hh:278
gem5::X86ISA::misc_reg::segBase
static RegIndex segBase(int index)
Definition: misc.hh:510
gem5::X86ISA::de
Bitfield< 3 > de
Definition: misc.hh:635
gem5::X86ISA::misc_reg::MtrrPhysMask0
@ MtrrPhysMask0
Definition: misc.hh:183
gem5::X86ISA::misc_reg::mtrrPhysBase
static RegIndex mtrrPhysBase(int index)
Definition: misc.hh:433
gem5::X86ISA::misc_reg::Mc0Misc
@ Mc0Misc
Definition: misc.hh:243
gem5::X86ISA::CC3Bit
@ CC3Bit
Definition: misc.hh:102
gem5::X86ISA::em
Bitfield< 2 > em
Definition: misc.hh:602
gem5::X86ISA::misc_reg::LsLimit
@ LsLimit
Definition: misc.hh:364
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:992
gem5::X86ISA::misc_reg::Mc3Ctl
@ Mc3Ctl
Definition: misc.hh:213
gem5::X86ISA::pcd
Bitfield< 4 > pcd
Definition: pagetable.hh:147
gem5::X86ISA::targetESP
targetESP
Definition: misc.hh:692
gem5::X86ISA::misc_reg::IorrBaseBase
@ IorrBaseBase
Definition: misc.hh:282
gem5::X86ISA::misc_reg::Tsc
@ Tsc
Definition: misc.hh:152
gem5::X86ISA::r
Bitfield< 41 > r
Definition: misc.hh:934
gem5::X86ISA::c
Bitfield< 42 > c
Definition: misc.hh:933
gem5::X86ISA::rw1
Bitfield< 21, 20 > rw1
Definition: misc.hh:669
gem5::X86ISA::CFBit
@ CFBit
Definition: misc.hh:59
gem5::X86ISA::misc_reg::perfEvtCtr
static RegIndex perfEvtCtr(int index)
Definition: misc.hh:482
gem5::X86ISA::misc_reg::LastBranchToIp
@ LastBranchToIp
Definition: misc.hh:167
gem5::X86ISA::offsetHigh
offsetHigh
Definition: misc.hh:1001
gem5::X86ISA::misc_reg::PerfEvtSel1
@ PerfEvtSel1
Definition: misc.hh:268
gem5::X86ISA::misc_reg::TscAux
@ TscAux
Definition: misc.hh:264
gem5::X86ISA::len2
Bitfield< 27, 26 > len2
Definition: misc.hh:672
gem5::X86ISA::pae
Bitfield< 5 > pae
Definition: misc.hh:633
gem5::X86ISA::misc_reg::DsAttr
@ DsAttr
Definition: misc.hh:374
gem5::X86ISA::pb0
Bitfield< 2 > pb0
Definition: misc.hh:716
gem5::X86ISA::misc_reg::Cr0
@ Cr0
Definition: misc.hh:114
gem5::X86ISA::otherInfo
Bitfield< 56, 32 > otherInfo
Definition: misc.hh:762
gem5::X86ISA::stack
Bitfield< 17, 16 > stack
Definition: misc.hh:587
gem5::X86ISA::btf
Bitfield< 1 > btf
Definition: misc.hh:715
gem5::X86ISA::misc_reg::Mc7Status
@ Mc7Status
Definition: misc.hh:228
gem5::X86ISA::misc_reg::IdtrEffBase
@ IdtrEffBase
Definition: misc.hh:351
gem5::X86ISA::NumCRegs
const int NumCRegs
Definition: x86_traits.hh:56
gem5::X86ISA::misc_reg::EsLimit
@ EsLimit
Definition: misc.hh:355
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1051
gem5::X86ISA::misc_reg::Foseg
@ Foseg
Definition: misc.hh:395
gem5::X86ISA::misc_reg::TsgAttr
@ TsgAttr
Definition: misc.hh:379
gem5::X86ISA::misc_reg::GsBase
@ GsBase
Definition: misc.hh:326
gem5::X86ISA::g
Bitfield< 8 > g
Definition: pagetable.hh:143
gem5::X86ISA::count
count
Definition: misc.hh:703
gem5::X86ISA::EZFBit
@ EZFBit
Definition: misc.hh:63
gem5::X86ISA::TFBit
@ TFBit
Definition: misc.hh:75
gem5::X86ISA::misc_reg::Mc6Ctl
@ Mc6Ctl
Definition: misc.hh:216
gem5::X86ISA::misc_reg::cr
static RegIndex cr(int index)
Definition: misc.hh:419
gem5::X86ISA::misc_reg::Cr13
@ Cr13
Definition: misc.hh:127
gem5::X86ISA::misc_reg::NumRegs
@ NumRegs
Definition: misc.hh:406
gem5::X86ISA::misc_reg::mcAddr
static RegIndex mcAddr(int index)
Definition: misc.hh:461
gem5::X86ISA::VMBit
@ VMBit
Definition: misc.hh:79
gem5::X86ISA::misc_reg::Cr11
@ Cr11
Definition: misc.hh:125
gem5::X86ISA::rsmCycle
Bitfield< 4 > rsmCycle
Definition: misc.hh:849
gem5::X86ISA::misc_reg::Mxcsr
@ Mxcsr
Definition: misc.hh:388
gem5::BitfieldType
Definition: bitunion.hh:117
segment.hh
gem5::X86ISA::mp
Bitfield< 1 > mp
Definition: misc.hh:603
gem5::X86ISA::misc_reg::MtrrPhysBase6
@ MtrrPhysBase6
Definition: misc.hh:178
gem5::X86ISA::disA20M
Bitfield< 2 > disA20M
Definition: misc.hh:837
bitunion.hh
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::X86ISA::StackFaultBit
@ StackFaultBit
Definition: misc.hh:97
gem5::X86ISA::vme
Bitfield< 0 > vme
Definition: misc.hh:638
gem5::X86ISA::misc_reg::SegBaseBase
@ SegBaseBase
Definition: misc.hh:320
gem5::X86ISA::misc_reg::TopMem2
@ TopMem2
Definition: misc.hh:293
gem5::X86ISA::misc_reg::Fiseg
@ Fiseg
Definition: misc.hh:393
gem5::X86ISA::misc_reg::SysenterEip
@ SysenterEip
Definition: misc.hh:158
gem5::X86ISA::submode
Bitfield< 3, 1 > submode
Definition: misc.hh:579
gem5::X86ISA::nt
Bitfield< 14 > nt
Definition: misc.hh:564
gem5::X86ISA::SegDescriptorLimit::getter
uint32_t getter(const uint64_t &storage) const
Definition: misc.hh:890
gem5::X86ISA::physAddr
physAddr
Definition: misc.hh:831
gem5::X86ISA::osfxsr
Bitfield< 9 > osfxsr
Definition: misc.hh:629
gem5::X86ISA::mcaErrorCode
mcaErrorCode
Definition: misc.hh:760
gem5::X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
gem5::X86ISA::addrv
Bitfield< 58 > addrv
Definition: misc.hh:764
gem5::X86ISA::misc_reg::HsLimit
@ HsLimit
Definition: misc.hh:361
gem5::X86ISA::misc_reg::Mc6Misc
@ Mc6Misc
Definition: misc.hh:249
gem5::X86ISA::misc_reg::SysenterEsp
@ SysenterEsp
Definition: misc.hh:157
gem5::X86ISA::misc_reg::MtrrPhysBase0
@ MtrrPhysBase0
Definition: misc.hh:172
gem5::X86ISA::misc_reg::Fop
@ Fop
Definition: misc.hh:397
gem5::X86ISA::misc_reg::MtrrPhysMaskBase
@ MtrrPhysMaskBase
Definition: misc.hh:182
gem5::X86ISA::bd
Bitfield< 13 > bd
Definition: misc.hh:650
gem5::X86ISA::misc_reg::iorrMask
static RegIndex iorrMask(int index)
Definition: misc.hh:496
gem5::MipsISA::wr
Bitfield< 3 > wr
Definition: pra_constants.hh:244
gem5::X86ISA::SubBitUnion
SubBitUnion(type, 43, 40) Bitfield< 43 > codeOrData
gem5::X86ISA::misc_reg::TslBase
@ TslBase
Definition: misc.hh:328
gem5::X86ISA::misc_reg::IdtrAttr
@ IdtrAttr
Definition: misc.hh:383
gem5::X86ISA::miscv
Bitfield< 59 > miscv
Definition: misc.hh:765
gem5::X86ISA::misc_reg::FsLimit
@ FsLimit
Definition: misc.hh:359
gem5::X86ISA::ECFBit
@ ECFBit
Definition: misc.hh:61
gem5::X86ISA::misc_reg::Mc4Ctl
@ Mc4Ctl
Definition: misc.hh:214
gem5::X86ISA::misc_reg::Fsw
@ Fsw
Definition: misc.hh:390
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::misc_reg::MtrrFix4kF0000
@ MtrrFix4kF0000
Definition: misc.hh:202
gem5::X86ISA::misc_reg::MtrrPhysBase1
@ MtrrPhysBase1
Definition: misc.hh:173
gem5::X86ISA::gd
Bitfield< 13 > gd
Definition: misc.hh:666
gem5::X86ISA::misc_reg::Cr2
@ Cr2
Definition: misc.hh:116
gem5::X86ISA::ti
Bitfield< 2 > ti
Definition: misc.hh:861
gem5::X86ISA::misc_reg::Ds
@ Ds
Definition: misc.hh:308
gem5::X86ISA::misc_reg::SmmCtl
@ SmmCtl
Definition: misc.hh:297
gem5::X86ISA::pf
Bitfield< 2 > pf
Definition: misc.hh:550
gem5::X86ISA::b1
Bitfield< 1 > b1
Definition: misc.hh:647
gem5::X86ISA::misc_reg::MtrrPhysBase4
@ MtrrPhysBase4
Definition: misc.hh:176
gem5::X86ISA::ffxsr
Bitfield< 14 > ffxsr
Definition: misc.hh:786
gem5::X86ISA::bsp
Bitfield< 8 > bsp
Definition: misc.hh:1052
gem5::X86ISA::paePdtb
Bitfield< 31, 5 > paePdtb
Definition: misc.hh:617
gem5::X86ISA::misc_reg::Tsl
@ Tsl
Definition: misc.hh:312
gem5::X86ISA::misc_reg::DsLimit
@ DsLimit
Definition: misc.hh:358
gem5::X86ISA::misc_reg::Cr5
@ Cr5
Definition: misc.hh:119
gem5::X86ISA::misc_reg::Cr3
@ Cr3
Definition: misc.hh:117
gem5::X86ISA::usr
Bitfield< 16 > usr
Definition: misc.hh:802
gem5::X86ISA::misc_reg::Mc3Status
@ Mc3Status
Definition: misc.hh:224
gem5::X86ISA::misc_reg::Mc5Addr
@ Mc5Addr
Definition: misc.hh:237
gem5::X86ISA::misc_reg::SegAttrBase
@ SegAttrBase
Definition: misc.hh:370
gem5::X86ISA::esi
esi
Definition: misc.hh:859
gem5::X86ISA::rw2
Bitfield< 25, 24 > rw2
Definition: misc.hh:671
gem5::X86ISA::af
Bitfield< 4 > af
Definition: misc.hh:548
gem5::X86ISA::misc_reg::VmCr
@ VmCr
Definition: misc.hh:295
gem5::X86ISA::misc_reg::Cr4
@ Cr4
Definition: misc.hh:118
gem5::X86ISA::dpl
Bitfield< 46, 45 > dpl
Definition: misc.hh:926
gem5::X86ISA::w
Bitfield< 1 > w
Definition: pagetable.hh:150
gem5::X86ISA::misc_reg::Cs
@ Cs
Definition: misc.hh:306
gem5::X86ISA::misc_reg::Idtr
@ Idtr
Definition: misc.hh:317
gem5::X86ISA::si
Bitfield< 15, 3 > si
Definition: misc.hh:860
gem5::X86ISA::misc_reg::PerfEvtCtr0
@ PerfEvtCtr0
Definition: misc.hh:274
gem5::X86ISA::ac
Bitfield< 18 > ac
Definition: misc.hh:561
gem5::X86ISA::OFBit
@ OFBit
Definition: misc.hh:67
gem5::X86ISA::longPdtb
longPdtb
Definition: misc.hh:613
gem5::X86ISA::misc_reg::Ls
@ Ls
Definition: misc.hh:314
gem5::X86ISA::baseLow
Bitfield< 39, 16 > baseLow
Definition: misc.hh:915
gem5::X86ISA::expandDown
Bitfield< 14 > expandDown
Definition: misc.hh:996
gem5::X86ISA::exit
Bitfield< 3 > exit
Definition: misc.hh:848
gem5::X86ISA::RFLAGBit
RFLAGBit
Definition: misc.hh:73
gem5::X86ISA::NTBit
@ NTBit
Definition: misc.hh:77
gem5::X86ISA::enter
Bitfield< 1 > enter
Definition: misc.hh:846
gem5::X86ISA::misc_reg::SysenterCs
@ SysenterCs
Definition: misc.hh:156
gem5::X86ISA::intEn
Bitfield< 20 > intEn
Definition: misc.hh:806
gem5::X86ISA::physbase
Bitfield< 51, 12 > physbase
Definition: misc.hh:728
gem5::X86ISA::misc_reg::McAddrEnd
@ McAddrEnd
Definition: misc.hh:240
gem5::X86ISA::vif
Bitfield< 19 > vif
Definition: misc.hh:560
gem5::X86ISA::BitUnion32
BitUnion32(TriggerIntMessage) Bitfield< 7
gem5::X86ISA::misc_reg::Cr12
@ Cr12
Definition: misc.hh:126
gem5::X86ISA::misc_reg::IorrBaseEnd
@ IorrBaseEnd
Definition: misc.hh:285
gem5::X86ISA::legacy
legacy
Definition: misc.hh:609
gem5::X86ISA::misc_reg::IorrMask0
@ IorrMask0
Definition: misc.hh:288
gem5::X86ISA::misc_reg::Dr3
@ Dr3
Definition: misc.hh:136
gem5::X86ISA::lme
Bitfield< 8 > lme
Definition: misc.hh:782
gem5::X86ISA::eventMask
eventMask
Definition: misc.hh:800
gem5::X86ISA::tf
Bitfield< 8 > tf
Definition: misc.hh:569
gem5::QARMA::b0
Bitfield< 3, 0 > b0
Definition: qarma.hh:66
gem5::X86ISA::misc_reg::MtrrPhysMask5
@ MtrrPhysMask5
Definition: misc.hh:188
gem5::X86ISA::misc_reg::IdtrBase
@ IdtrBase
Definition: misc.hh:333
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
gem5::X86ISA::misc_reg::Cr7
@ Cr7
Definition: misc.hh:121
gem5::X86ISA::sysretCsAndSs
Bitfield< 63, 48 > sysretCsAndSs
Definition: misc.hh:792
gem5::X86ISA::misc_reg::FsBase
@ FsBase
Definition: misc.hh:325
gem5::X86ISA::misc_reg::iorrBase
static RegIndex iorrBase(int index)
Definition: misc.hh:489
gem5::X86ISA::misc_reg::TsgLimit
@ TsgLimit
Definition: misc.hh:363
gem5::X86ISA::misc_reg::Gs
@ Gs
Definition: misc.hh:310
gem5::X86ISA::rpl
Bitfield< 1, 0 > rpl
Definition: misc.hh:862
gem5::X86ISA::vm
Bitfield< 17 > vm
Definition: misc.hh:562
gem5::X86ISA::misc_reg::EsAttr
@ EsAttr
Definition: misc.hh:371
gem5::X86ISA::misc_reg::MtrrFix16k80000
@ MtrrFix16k80000
Definition: misc.hh:194
gem5::X86ISA::unusable
Bitfield< 2 > unusable
Definition: misc.hh:987
gem5::X86ISA::eipv
Bitfield< 1 > eipv
Definition: misc.hh:709
gem5::X86ISA::misc_reg::MtrrPhysBase2
@ MtrrPhysBase2
Definition: misc.hh:174
gem5::X86ISA::misc_reg::Mtrrcap
@ Mtrrcap
Definition: misc.hh:154
gem5::X86ISA::misc_reg::MtrrPhysMaskEnd
@ MtrrPhysMaskEnd
Definition: misc.hh:191
gem5::X86ISA::misc_reg::Mc4Addr
@ Mc4Addr
Definition: misc.hh:236
gem5::X86ISA::avl
Bitfield< 11, 9 > avl
Definition: pagetable.hh:142
gem5::X86ISA::granularity
Bitfield< 6 > granularity
Definition: misc.hh:991
gem5::X86ISA::misc_reg::Fooff
@ Fooff
Definition: misc.hh:396
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::X86ISA::misc_reg::X87Top
@ X87Top
Definition: misc.hh:386
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::misc_reg::PerfEvtCtrBase
@ PerfEvtCtrBase
Definition: misc.hh:273
gem5::X86ISA::over
Bitfield< 62 > over
Definition: misc.hh:768
gem5::X86ISA::misc_reg::DrBase
@ DrBase
Definition: misc.hh:132
gem5::X86ISA::misc_reg::FsEffBase
@ FsEffBase
Definition: misc.hh:343
gem5::X86ISA::selector
Bitfield< 31, 16 > selector
Definition: misc.hh:1003
gem5::X86ISA::inv
Bitfield< 23 > inv
Definition: misc.hh:808
gem5::X86ISA::am
Bitfield< 18 > am
Definition: misc.hh:597
gem5::X86ISA::misc_reg::McgCap
@ McgCap
Definition: misc.hh:160
gem5::X86ISA::targetEip
targetEip
Definition: misc.hh:790
gem5::X86ISA::rd
Bitfield< 4 > rd
Definition: misc.hh:821
gem5::X86ISA::misc_reg::McCtlBase
@ McCtlBase
Definition: misc.hh:209
gem5::X86ISA::misc_reg::MtrrFix4kC8000
@ MtrrFix4kC8000
Definition: misc.hh:197
gem5::X86ISA::ezf
Bitfield< 5 > ezf
Definition: misc.hh:547
gem5::X86ISA::misc_reg::mcCtl
static RegIndex mcCtl(int index)
Definition: misc.hh:447
gem5::X86ISA::misc_reg::Hs
@ Hs
Definition: misc.hh:311
gem5::X86ISA::misc_reg::Mc1Status
@ Mc1Status
Definition: misc.hh:222
gem5::X86ISA::misc_reg::SsLimit
@ SsLimit
Definition: misc.hh:357
gem5::X86ISA::misc_reg::MtrrPhysMask6
@ MtrrPhysMask6
Definition: misc.hh:189
gem5::X86ISA::misc_reg::LastExceptionFromIp
@ LastExceptionFromIp
Definition: misc.hh:168
gem5::X86ISA::AFBit
@ AFBit
Definition: misc.hh:62
gem5::X86ISA::pce
Bitfield< 8 > pce
Definition: misc.hh:630
gem5::X86ISA::misc_reg::Mc3Misc
@ Mc3Misc
Definition: misc.hh:246
gem5::X86ISA::l1
Bitfield< 2 > l1
Definition: misc.hh:658
gem5::X86ISA::et
Bitfield< 4 > et
Definition: misc.hh:600
logging.hh
gem5::X86ISA::misc_reg::EsEffBase
@ EsEffBase
Definition: misc.hh:339
gem5::X86ISA::d
Bitfield< 6 > d
Definition: pagetable.hh:145
gem5::X86ISA::misc_reg::VmHsavePa
@ VmHsavePa
Definition: misc.hh:298
gem5::X86ISA::pe
Bitfield< 0 > pe
Definition: misc.hh:604
gem5::X86ISA::cd
Bitfield< 30 > cd
Definition: misc.hh:595
gem5::X86ISA::PFBit
@ PFBit
Definition: misc.hh:60
gem5::X86ISA::misc_reg::SsBase
@ SsBase
Definition: misc.hh:323
gem5::X86ISA::misc_reg::MtrrFix4kE0000
@ MtrrFix4kE0000
Definition: misc.hh:200
gem5::X86ISA::misc_reg::PerfEvtSel3
@ PerfEvtSel3
Definition: misc.hh:270
gem5::X86ISA::misc_reg::MtrrPhysMask4
@ MtrrPhysMask4
Definition: misc.hh:187
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::X86ISA::misc_reg::SsAttr
@ SsAttr
Definition: misc.hh:373
gem5::X86ISA::misc_reg::Rflags
@ Rflags
Definition: misc.hh:143
gem5::X86ISA::misc_reg::MtrrPhysBase5
@ MtrrPhysBase5
Definition: misc.hh:177
gem5::X86ISA::misc_reg::Dr4
@ Dr4
Definition: misc.hh:137
gem5::X86ISA::IFBit
@ IFBit
Definition: misc.hh:76
gem5::X86ISA::misc_reg::IorrMaskEnd
@ IorrMaskEnd
Definition: misc.hh:290
gem5::X86ISA::misc_reg::Syscfg
@ Syscfg
Definition: misc.hh:280
gem5::X86ISA::misc_reg::GsEffBase
@ GsEffBase
Definition: misc.hh:344
gem5::X86ISA::misc_reg::Cr10
@ Cr10
Definition: misc.hh:124
gem5::X86ISA::misc_reg::Mc4Status
@ Mc4Status
Definition: misc.hh:225
gem5::X86ISA::misc_reg::EsBase
@ EsBase
Definition: misc.hh:321
gem5::X86ISA::misc_reg::McMiscBase
@ McMiscBase
Definition: misc.hh:242
gem5::X86ISA::fix
Bitfield< 8 > fix
Definition: misc.hh:680
gem5::X86ISA::misc_reg::TslLimit
@ TslLimit
Definition: misc.hh:362
gem5::X86ISA::misc_reg::IorrMask1
@ IorrMask1
Definition: misc.hh:289
gem5::X86ISA::pse
Bitfield< 4 > pse
Definition: misc.hh:634
gem5::X86ISA::nw
Bitfield< 29 > nw
Definition: misc.hh:596
gem5::X86ISA::misc_reg::Es
@ Es
Definition: misc.hh:305
gem5::X86ISA::syscallCsAndSs
Bitfield< 47, 32 > syscallCsAndSs
Definition: misc.hh:791
gem5::X86ISA::physmask
Bitfield< 51, 12 > physmask
Definition: misc.hh:733
gem5::X86ISA::misc_reg::Cr8
@ Cr8
Definition: misc.hh:122
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::X86ISA::misc_reg::Mc4Misc
@ Mc4Misc
Definition: misc.hh:247
gem5::X86ISA::misc_reg::mtrrPhysMask
static RegIndex mtrrPhysMask(int index)
Definition: misc.hh:440
gem5::X86ISA::misc_reg::LastBranchFromIp
@ LastBranchFromIp
Definition: misc.hh:166
gem5::X86ISA::misc_reg::LsAttr
@ LsAttr
Definition: misc.hh:380
gem5::X86ISA::misc_reg::IdtrLimit
@ IdtrLimit
Definition: misc.hh:367
gem5::X86ISA::misc_reg::Mc2Ctl
@ Mc2Ctl
Definition: misc.hh:212
gem5::X86ISA::segment_idx::NumIdxs
@ NumIdxs
Definition: segment.hh:67
gem5::X86ISA::limitLow
Bitfield< 15, 0 > limitLow
Definition: misc.hh:923
gem5::X86ISA::svme
Bitfield< 12 > svme
Definition: misc.hh:785
gem5::X86ISA::counterMask
Bitfield< 31, 24 > counterMask
Definition: misc.hh:809
gem5::X86ISA::misc_reg::TrEffBase
@ TrEffBase
Definition: misc.hh:350
gem5::X86ISA::pdtb
Bitfield< 31, 12 > pdtb
Definition: misc.hh:615
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::misc_reg::TrLimit
@ TrLimit
Definition: misc.hh:366
gem5::X86ISA::misc_reg::Efer
@ Efer
Definition: misc.hh:254
gem5::X86ISA::pwt
Bitfield< 3 > pwt
Definition: pagetable.hh:148
gem5::X86ISA::misc_reg::perfEvtSel
static RegIndex perfEvtSel(int index)
Definition: misc.hh:475
gem5::X86ISA::modelSpecificCode
Bitfield< 31, 16 > modelSpecificCode
Definition: misc.hh:761
gem5::X86ISA::sf
Bitfield< 7 > sf
Definition: misc.hh:545
gem5::X86ISA::misc_reg::IorrBase0
@ IorrBase0
Definition: misc.hh:283
gem5::X86ISA::CC1Bit
@ CC1Bit
Definition: misc.hh:100
gem5::X86ISA::offsetLow
Bitfield< 15, 0 > offsetLow
Definition: misc.hh:1002
gem5::X86ISA::mfdm
Bitfield< 19 > mfdm
Definition: misc.hh:814
gem5::X86ISA::g1
Bitfield< 3 > g1
Definition: misc.hh:659
gem5::X86ISA::l2
Bitfield< 4 > l2
Definition: misc.hh:660
gem5::X86ISA::misc_reg::MtrrPhysMask7
@ MtrrPhysMask7
Definition: misc.hh:190
gem5::X86ISA::misc_reg::CsAttr
@ CsAttr
Definition: misc.hh:372
gem5::X86ISA::s
Bitfield< 44 > s
Definition: misc.hh:927
gem5::X86ISA::misc_reg::Mc0Ctl
@ Mc0Ctl
Definition: misc.hh:210
gem5::X86ISA::X87StatusBit
X87StatusBit
Definition: misc.hh:86
gem5::X86ISA::misc_reg::MsEffBase
@ MsEffBase
Definition: misc.hh:349
gem5::X86ISA::misc_reg::segLimit
static RegIndex segLimit(int index)
Definition: misc.hh:524
gem5::X86ISA::misc_reg::HsBase
@ HsBase
Definition: misc.hh:327
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::misc_reg::Mc7Addr
@ Mc7Addr
Definition: misc.hh:239
gem5::X86ISA::targetCS
targetCS
Definition: misc.hh:688
gem5::X86ISA::misc_reg::Pat
@ Pat
Definition: misc.hh:205
gem5::X86ISA::misc_reg::PerfEvtSelBase
@ PerfEvtSelBase
Definition: misc.hh:266
gem5::X86ISA::g0
Bitfield< 1 > g0
Definition: misc.hh:657
gem5::X86ISA::misc_reg::Fs
@ Fs
Definition: misc.hh:309
gem5::X86ISA::ecf
Bitfield< 3 > ecf
Definition: misc.hh:549
gem5::X86ISA::misc_reg::MtrrPhysMask3
@ MtrrPhysMask3
Definition: misc.hh:186
gem5::X86ISA::misc_reg::TrBase
@ TrBase
Definition: misc.hh:332
gem5::X86ISA::cf
Bitfield< 0 > cf
Definition: misc.hh:551
gem5::X86ISA::misc_reg::MsBase
@ MsBase
Definition: misc.hh:331
gem5::X86ISA::unitMask
Bitfield< 15, 8 > unitMask
Definition: misc.hh:801
gem5::X86ISA::prot
Bitfield< 7 > prot
Definition: misc.hh:582
gem5::X86ISA::misc_reg::MtrrFix4kF8000
@ MtrrFix4kF8000
Definition: misc.hh:203
gem5::X86ISA::misc_reg::MtrrPhysMask2
@ MtrrPhysMask2
Definition: misc.hh:185
gem5::X86ISA::a
Bitfield< 5 > a
Definition: pagetable.hh:146
gem5::X86ISA::vip
Bitfield< 20 > vip
Definition: misc.hh:559
gem5::X86ISA::misc_reg::HsEffBase
@ HsEffBase
Definition: misc.hh:345
gem5::X86ISA::EndSubBitUnion
EndSubBitUnion(type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
gem5::X86ISA::CfofMask
constexpr uint32_t CfofMask
Definition: misc.hh:70
gem5::X86ISA::limitHigh
Bitfield< 51, 48 > limitHigh
Definition: misc.hh:922
gem5::X86ISA::misc_reg::Mc6Addr
@ Mc6Addr
Definition: misc.hh:238
gem5::X86ISA::PEBit
@ PEBit
Definition: misc.hh:94
gem5::X86ISA::misc_reg::Cr14
@ Cr14
Definition: misc.hh:128
gem5::X86ISA::misc_reg::PerfEvtSelEnd
@ PerfEvtSelEnd
Definition: misc.hh:271
gem5::X86ISA::misc_reg::Tsg
@ Tsg
Definition: misc.hh:313

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