gem5  v22.1.0.0
misc.hh
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37 
38 #ifndef __ARCH_X86_MISCREGS_HH__
39 #define __ARCH_X86_MISCREGS_HH__
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "arch/x86/x86_traits.hh"
43 #include "base/bitunion.hh"
44 #include "base/logging.hh"
45 #include "cpu/reg_class.hh"
46 #include "debug/MiscRegs.hh"
47 
48 //These get defined in some system headers (at least termbits.h). That confuses
49 //things here significantly.
50 #undef CR0
51 #undef CR2
52 #undef CR3
53 
54 namespace gem5
55 {
56 namespace X86ISA
57 {
58 
60 {
61  CFBit = 1 << 0,
62  PFBit = 1 << 2,
63  ECFBit = 1 << 3,
64  AFBit = 1 << 4,
65  EZFBit = 1 << 5,
66  ZFBit = 1 << 6,
67  SFBit = 1 << 7,
68  DFBit = 1 << 10,
69  OFBit = 1 << 11
70 };
71 
72 constexpr uint32_t CfofMask = CFBit | OFBit;
73 constexpr uint32_t CcFlagMask = PFBit | AFBit | ZFBit | SFBit;
74 
76 {
77  TFBit = 1 << 8,
78  IFBit = 1 << 9,
79  NTBit = 1 << 14,
80  RFBit = 1 << 16,
81  VMBit = 1 << 17,
82  ACBit = 1 << 18,
83  VIFBit = 1 << 19,
84  VIPBit = 1 << 20,
85  IDBit = 1 << 21
86 };
87 
89 {
90  // Exception Flags
91  IEBit = 1 << 0,
92  DEBit = 1 << 1,
93  ZEBit = 1 << 2,
94  OEBit = 1 << 3,
95  UEBit = 1 << 4,
96  PEBit = 1 << 5,
97 
98  // !Exception Flags
99  StackFaultBit = 1 << 6,
100  ErrSummaryBit = 1 << 7,
101  CC0Bit = 1 << 8,
102  CC1Bit = 1 << 9,
103  CC2Bit = 1 << 10,
104  CC3Bit = 1 << 14,
105  BusyBit = 1 << 15,
106 };
107 
108 namespace misc_reg
109 {
110 
111 enum : RegIndex
112 {
113  // Control registers
114  // Most of these are invalid. See isValid() below.
132 
133  // Debug registers
143 
144  // Flags register
146 
147  //Register to keep handy values like the CPU mode in.
149 
150  /*
151  * Model Specific Registers
152  */
153  // Time stamp counter
155 
157 
161 
165 
167 
172 
183 
194 
206 
208 
210 
221 
232 
243 
254 
255  // Extended feature enable register
257 
261 
263 
265 
267 
274 
281 
283 
288 
293 
296 
301 
302  /*
303  * Segment registers
304  */
305  // Segment selectors
308  Cs,
309  Ss,
310  Ds,
311  Fs,
312  Gs,
313  Hs,
316  Ls,
317  Ms,
318  Tr,
320 
321  // Hidden segment base field
336 
337  // The effective segment base, ie what is actually added to an
338  // address. In 64 bit mode this can be different from the above,
339  // namely 0.
354 
355  // Hidden segment limit field
370 
371  // Hidden segment limit attributes
386 
387  // Floating point control registers
389 
400 
401  //XXX Add "Model-Specific Registers"
402 
404 
405  // "Fake" MSRs for internally implemented devices
407 
408  NumRegs
409 };
410 
411 static inline bool
413 {
414  return (index >= Cr0 && index < NumRegs &&
415  index != Cr1 &&
416  !(index > Cr4 && index < Cr8) &&
417  !(index > Cr8 && index <= Cr15));
418 }
419 
420 static inline RegIndex
421 cr(int index)
422 {
423  assert(index >= 0 && index < NumCRegs);
424  return CrBase + index;
425 }
426 
427 static inline RegIndex
428 dr(int index)
429 {
430  assert(index >= 0 && index < NumDRegs);
431  return DrBase + index;
432 }
433 
434 static inline RegIndex
436 {
437  assert(index >= 0 && index < (MtrrPhysBaseEnd - MtrrPhysBaseBase));
438  return MtrrPhysBaseBase + index;
439 }
440 
441 static inline RegIndex
443 {
444  assert(index >= 0 && index < (MtrrPhysMaskEnd - MtrrPhysMaskBase));
445  return MtrrPhysMaskBase + index;
446 }
447 
448 static inline RegIndex
450 {
451  assert(index >= 0 && index < (McCtlEnd - McCtlBase));
452  return McCtlBase + index;
453 }
454 
455 static inline RegIndex
457 {
458  assert(index >= 0 && index < (McStatusEnd - McStatusBase));
459  return McStatusBase + index;
460 }
461 
462 static inline RegIndex
464 {
465  assert(index >= 0 && index < (McAddrEnd - McAddrBase));
466  return McAddrBase + index;
467 }
468 
469 static inline RegIndex
471 {
472  assert(index >= 0 && index < (McMiscEnd - McMiscBase));
473  return McMiscBase + index;
474 }
475 
476 static inline RegIndex
478 {
479  assert(index >= 0 && index < (PerfEvtSelEnd - PerfEvtSelBase));
480  return PerfEvtSelBase + index;
481 }
482 
483 static inline RegIndex
485 {
486  assert(index >= 0 && index < (PerfEvtCtrEnd - PerfEvtCtrBase));
487  return PerfEvtCtrBase + index;
488 }
489 
490 static inline RegIndex
492 {
493  assert(index >= 0 && index < (IorrBaseEnd - IorrBaseBase));
494  return IorrBaseBase + index;
495 }
496 
497 static inline RegIndex
499 {
500  assert(index >= 0 && index < (IorrMaskEnd - IorrMaskBase));
501  return IorrMaskBase + index;
502 }
503 
504 static inline RegIndex
506 {
507  assert(index >= 0 && index < segment_idx::NumIdxs);
508  return SegSelBase + index;
509 }
510 
511 static inline RegIndex
513 {
514  assert(index >= 0 && index < segment_idx::NumIdxs);
515  return SegBaseBase + index;
516 }
517 
518 static inline RegIndex
520 {
521  assert(index >= 0 && index < segment_idx::NumIdxs);
522  return SegEffBaseBase + index;
523 }
524 
525 static inline RegIndex
527 {
528  assert(index >= 0 && index < segment_idx::NumIdxs);
529  return SegLimitBase + index;
530 }
531 
532 static inline RegIndex
534 {
535  assert(index >= 0 && index < segment_idx::NumIdxs);
536  return SegAttrBase + index;
537 }
538 
539 } // namespace misc_reg
540 
542  misc_reg::NumRegs, debug::MiscRegs);
543 
548 BitUnion64(CCFlagBits)
549  Bitfield<11> of;
550  Bitfield<7> sf;
551  Bitfield<6> zf;
552  Bitfield<5> ezf;
553  Bitfield<4> af;
554  Bitfield<3> ecf;
555  Bitfield<2> pf;
556  Bitfield<0> cf;
557 EndBitUnion(CCFlagBits)
558 
559 
562 BitUnion64(RFLAGS)
563  Bitfield<21> id; // ID Flag
564  Bitfield<20> vip; // Virtual Interrupt Pending
565  Bitfield<19> vif; // Virtual Interrupt Flag
566  Bitfield<18> ac; // Alignment Check
567  Bitfield<17> vm; // Virtual-8086 Mode
568  Bitfield<16> rf; // Resume Flag
569  Bitfield<14> nt; // Nested Task
570  Bitfield<13, 12> iopl; // I/O Privilege Level
571  Bitfield<11> of; // Overflow Flag
572  Bitfield<10> df; // Direction Flag
573  Bitfield<9> intf; // Interrupt Flag
574  Bitfield<8> tf; // Trap Flag
575  Bitfield<7> sf; // Sign Flag
576  Bitfield<6> zf; // Zero Flag
577  Bitfield<4> af; // Auxiliary Flag
578  Bitfield<2> pf; // Parity Flag
579  Bitfield<0> cf; // Carry Flag
580 EndBitUnion(RFLAGS)
581 
582 BitUnion64(HandyM5Reg)
583  Bitfield<0> mode;
584  Bitfield<3, 1> submode;
585  Bitfield<5, 4> cpl;
586  Bitfield<6> paging;
587  Bitfield<7> prot;
588  Bitfield<9, 8> defOp;
589  Bitfield<11, 10> altOp;
590  Bitfield<13, 12> defAddr;
591  Bitfield<15, 14> altAddr;
592  Bitfield<17, 16> stack;
593 EndBitUnion(HandyM5Reg)
594 
595 
598 BitUnion64(CR0)
599  Bitfield<31> pg; // Paging
600  Bitfield<30> cd; // Cache Disable
601  Bitfield<29> nw; // Not Writethrough
602  Bitfield<18> am; // Alignment Mask
603  Bitfield<16> wp; // Write Protect
604  Bitfield<5> ne; // Numeric Error
605  Bitfield<4> et; // Extension Type
606  Bitfield<3> ts; // Task Switched
607  Bitfield<2> em; // Emulation
608  Bitfield<1> mp; // Monitor Coprocessor
609  Bitfield<0> pe; // Protection Enabled
611 
612 // Page Fault Virtual Address
613 BitUnion64(CR2)
614  Bitfield<31, 0> legacy;
616 
617 BitUnion64(CR3)
618  Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
619  // Base Address
620  Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
621  // Base Address
622  Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
623  // Base Address
624  Bitfield<11, 0> pcid; // Process-Context Identifier
625  Bitfield<4> pcd; // Page-Level Cache Disable
626  Bitfield<3> pwt; // Page-Level Writethrough
628 
629 BitUnion64(CR4)
630  Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
631  Bitfield<17> pcide; // PCID Enable
632  Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
633  // WRGSBASE instructions
634  Bitfield<10> osxmmexcpt; // Operating System Unmasked
635  // Exception Support
636  Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
637  Bitfield<8> pce; // Performance-Monitoring Counter Enable
638  Bitfield<7> pge; // Page-Global Enable
639  Bitfield<6> mce; // Machine Check Enable
640  Bitfield<5> pae; // Physical-Address Extension
641  Bitfield<4> pse; // Page Size Extensions
642  Bitfield<3> de; // Debugging Extensions
643  Bitfield<2> tsd; // Time Stamp Disable
644  Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
645  Bitfield<0> vme; // Virtual-8086 Mode Extensions
647 
648 BitUnion64(CR8)
649  Bitfield<3, 0> tpr; // Task Priority Register
651 
652 BitUnion64(DR6)
653  Bitfield<0> b0;
654  Bitfield<1> b1;
655  Bitfield<2> b2;
656  Bitfield<3> b3;
657  Bitfield<13> bd;
658  Bitfield<14> bs;
659  Bitfield<15> bt;
661 
662 BitUnion64(DR7)
663  Bitfield<0> l0;
664  Bitfield<1> g0;
665  Bitfield<2> l1;
666  Bitfield<3> g1;
667  Bitfield<4> l2;
668  Bitfield<5> g2;
669  Bitfield<6> l3;
670  Bitfield<7> g3;
671  Bitfield<8> le;
672  Bitfield<9> ge;
673  Bitfield<13> gd;
674  Bitfield<17, 16> rw0;
675  Bitfield<19, 18> len0;
676  Bitfield<21, 20> rw1;
677  Bitfield<23, 22> len1;
678  Bitfield<25, 24> rw2;
679  Bitfield<27, 26> len2;
680  Bitfield<29, 28> rw3;
681  Bitfield<31, 30> len3;
683 
684 // MTRR capabilities
685 BitUnion64(MTRRcap)
686  Bitfield<7, 0> vcnt; // Variable-Range Register Count
687  Bitfield<8> fix; // Fixed-Range Registers
688  Bitfield<10> wc; // Write-Combining
689 EndBitUnion(MTRRcap)
690 
694 BitUnion64(SysenterCS)
695  Bitfield<15, 0> targetCS;
696 EndBitUnion(SysenterCS)
697 
698 BitUnion64(SysenterESP)
699  Bitfield<31, 0> targetESP;
700 EndBitUnion(SysenterESP)
701 
702 BitUnion64(SysenterEIP)
703  Bitfield<31, 0> targetEIP;
704 EndBitUnion(SysenterEIP)
705 
710  Bitfield<7, 0> count; // Number of error reporting register banks
711  Bitfield<8> MCGCP; // MCG_CTL register present.
713 
715  Bitfield<0> ripv; // Restart-IP valid
716  Bitfield<1> eipv; // Error-IP valid
717  Bitfield<2> mcip; // Machine check in-progress
719 
721  Bitfield<0> lbr; // Last-branch record
722  Bitfield<1> btf; // Branch single step
723  Bitfield<2> pb0; // Performance monitoring pin control 0
724  Bitfield<3> pb1; // Performance monitoring pin control 1
725  Bitfield<4> pb2; // Performance monitoring pin control 2
726  Bitfield<5> pb3; // Performance monitoring pin control 3
727  /*uint64_t pb(int index)
728  {
729  return bits(__data, index + 2);
730  }*/
732 
733 BitUnion64(MtrrPhysBase)
734  Bitfield<7, 0> type; // Default memory type
735  Bitfield<51, 12> physbase; // Range physical base address
736 EndBitUnion(MtrrPhysBase)
737 
738 BitUnion64(MtrrPhysMask)
739  Bitfield<11> valid; // MTRR pair enable
740  Bitfield<51, 12> physmask; // Range physical mask
741 EndBitUnion(MtrrPhysMask)
742 
743 BitUnion64(MtrrFixed)
744  /*uint64_t type(int index)
745  {
746  return bits(__data, index * 8 + 7, index * 8);
747  }*/
748 EndBitUnion(MtrrFixed)
749 
751  /*uint64_t pa(int index)
752  {
753  return bits(__data, index * 8 + 2, index * 8);
754  }*/
756 
757 BitUnion64(MtrrDefType)
758  Bitfield<7, 0> type; // Default type
759  Bitfield<10> fe; // Fixed range enable
760  Bitfield<11> e; // MTRR enable
761 EndBitUnion(MtrrDefType)
762 
766 BitUnion64(McStatus)
767  Bitfield<15,0> mcaErrorCode;
768  Bitfield<31,16> modelSpecificCode;
769  Bitfield<56,32> otherInfo;
770  Bitfield<57> pcc; // Processor-context corrupt
771  Bitfield<58> addrv; // Error-address register valid
772  Bitfield<59> miscv; // Miscellaneous-error register valid
773  Bitfield<60> en; // Error condition enabled
774  Bitfield<61> uc; // Uncorrected error
775  Bitfield<62> over; // Status register overflow
776  Bitfield<63> val; // Valid
777 EndBitUnion(McStatus)
778 
779 BitUnion64(McCtl)
780  /*uint64_t en(int index)
781  {
782  return bits(__data, index);
783  }*/
784 EndBitUnion(McCtl)
785 
786 // Extended feature enable register
788  Bitfield<0> sce; // System call extensions
789  Bitfield<8> lme; // Long mode enable
790  Bitfield<10> lma; // Long mode active
791  Bitfield<11> nxe; // No-execute enable
792  Bitfield<12> svme; // Secure virtual machine enable
793  Bitfield<14> ffxsr; // Fast fxsave/fxrstor
795 
797  Bitfield<31,0> targetEip;
798  Bitfield<47,32> syscallCsAndSs;
799  Bitfield<63,48> sysretCsAndSs;
801 
803  Bitfield<31,0> mask;
805 
806 BitUnion64(PerfEvtSel)
807  Bitfield<7,0> eventMask;
808  Bitfield<15,8> unitMask;
809  Bitfield<16> usr; // User mode
810  Bitfield<17> os; // Operating-system mode
811  Bitfield<18> e; // Edge detect
812  Bitfield<19> pc; // Pin control
813  Bitfield<20> intEn; // Interrupt enable
814  Bitfield<22> en; // Counter enable
815  Bitfield<23> inv; // Invert mask
816  Bitfield<31,24> counterMask;
817 EndBitUnion(PerfEvtSel)
818 
820  Bitfield<18> mfde; // MtrrFixDramEn
821  Bitfield<19> mfdm; // MtrrFixDramModEn
822  Bitfield<20> mvdm; // MtrrVarDramEn
823  Bitfield<21> tom2; // MtrrTom2En
825 
826 BitUnion64(IorrBase)
827  Bitfield<3> wr; // WrMem Enable
828  Bitfield<4> rd; // RdMem Enable
829  Bitfield<51,12> physbase; // Range physical base address
830 EndBitUnion(IorrBase)
831 
832 BitUnion64(IorrMask)
833  Bitfield<11> v; // I/O register pair enable (valid)
834  Bitfield<51,12> physmask; // Range physical mask
835 EndBitUnion(IorrMask)
836 
837 BitUnion64(Tom)
838  Bitfield<51,23> physAddr; // Top of memory physical address
840 
841 BitUnion64(VmCrMsr)
842  Bitfield<0> dpd;
843  Bitfield<1> rInit;
844  Bitfield<2> disA20M;
845 EndBitUnion(VmCrMsr)
846 
847 BitUnion64(IgnneMsr)
848  Bitfield<0> ignne;
849 EndBitUnion(IgnneMsr)
850 
851 BitUnion64(SmmCtlMsr)
852  Bitfield<0> dismiss;
853  Bitfield<1> enter;
854  Bitfield<2> smiCycle;
855  Bitfield<3> exit;
856  Bitfield<4> rsmCycle;
857 EndBitUnion(SmmCtlMsr)
858 
862 BitUnion64(SegSelector)
863  // The following bitfield is not defined in the ISA, but it's useful
864  // when checking selectors in larger data types to make sure they
865  // aren't too large.
866  Bitfield<63, 3> esi; // Extended selector
867  Bitfield<15, 3> si; // Selector Index
868  Bitfield<2> ti; // Table Indicator
869  Bitfield<1, 0> rpl; // Requestor Privilege Level
870 EndBitUnion(SegSelector)
871 
876 class SegDescriptorBase
877 {
878  public:
879  uint32_t
880  getter(const uint64_t &storage) const
881  {
882  return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16);
883  }
884 
885  void
886  setter(uint64_t &storage, uint32_t base)
887  {
888  replaceBits(storage, 63, 56, bits(base, 31, 24));
889  replaceBits(storage, 39, 16, bits(base, 23, 0));
890  }
891 };
892 
894 {
895  public:
896  uint32_t
897  getter(const uint64_t &storage) const
898  {
899  uint32_t limit = (bits(storage, 51, 48) << 16) |
900  bits(storage, 15, 0);
901  if (bits(storage, 55))
902  limit = (limit << 12) | mask(12);
903  return limit;
904  }
905 
906  void
907  setter(uint64_t &storage, uint32_t limit)
908  {
909  bool g = (bits(limit, 31, 24) != 0);
910  panic_if(g && bits(limit, 11, 0) != mask(12),
911  "Inlimitid segment limit %#x", limit);
912  if (g)
913  limit = limit >> 12;
914  replaceBits(storage, 51, 48, bits(limit, 23, 16));
915  replaceBits(storage, 15, 0, bits(limit, 15, 0));
916  replaceBits(storage, 55, g ? 1 : 0);
917  }
918 };
919 
920 BitUnion64(SegDescriptor)
921  Bitfield<63, 56> baseHigh;
922  Bitfield<39, 16> baseLow;
923  BitfieldType<SegDescriptorBase> base;
924  Bitfield<55> g; // Granularity
925  Bitfield<54> d; // Default Operand Size
926  Bitfield<54> b; // Default Operand Size
927  Bitfield<53> l; // Long Attribute Bit
928  Bitfield<52> avl; // Available To Software
929  Bitfield<51, 48> limitHigh;
930  Bitfield<15, 0> limitLow;
932  Bitfield<47> p; // Present
933  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
934  Bitfield<44> s; // System
935  SubBitUnion(type, 43, 40)
936  // Specifies whether this descriptor is for code or data.
937  Bitfield<43> codeOrData;
938 
939  // These bit fields are for code segments
940  Bitfield<42> c; // Conforming
941  Bitfield<41> r; // Readable
942 
943  // These bit fields are for data segments
944  Bitfield<42> e; // Expand-Down
945  Bitfield<41> w; // Writable
946 
947  // This is used for both code and data segments.
948  Bitfield<40> a; // Accessed
950 EndBitUnion(SegDescriptor)
951 
956 BitUnion64(TSSlow)
957  Bitfield<63, 56> baseHigh;
958  Bitfield<39, 16> baseLow;
959  BitfieldType<SegDescriptorBase> base;
960  Bitfield<55> g; // Granularity
961  Bitfield<52> avl; // Available To Software
962  Bitfield<51, 48> limitHigh;
963  Bitfield<15, 0> limitLow;
965  Bitfield<47> p; // Present
966  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
967  SubBitUnion(type, 43, 40)
968  // Specifies whether this descriptor is for code or data.
969  Bitfield<43> codeOrData;
970 
971  // These bit fields are for code segments
972  Bitfield<42> c; // Conforming
973  Bitfield<41> r; // Readable
974 
975  // These bit fields are for data segments
976  Bitfield<42> e; // Expand-Down
977  Bitfield<41> w; // Writable
978 
979  // This is used for both code and data segments.
980  Bitfield<40> a; // Accessed
982 EndBitUnion(TSSlow)
983 
988 BitUnion64(TSShigh)
989  Bitfield<31, 0> base;
990 EndBitUnion(TSShigh)
991 
992 BitUnion64(SegAttr)
993  Bitfield<1, 0> dpl;
994  Bitfield<2> unusable;
995  Bitfield<3> defaultSize;
996  Bitfield<4> longMode;
997  Bitfield<5> avl;
998  Bitfield<6> granularity;
999  Bitfield<7> present;
1000  Bitfield<11, 8> type;
1001  Bitfield<12> writable;
1002  Bitfield<13> readable;
1003  Bitfield<14> expandDown;
1004  Bitfield<15> system;
1005 EndBitUnion(SegAttr)
1006 
1007 BitUnion64(GateDescriptor)
1008  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1009  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1010  Bitfield<31, 16> selector; // Target Code-Segment Selector
1011  Bitfield<47> p; // Present
1012  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1013  Bitfield<43, 40> type;
1014  Bitfield<36, 32> count; // Parameter Count
1015 EndBitUnion(GateDescriptor)
1016 
1020 BitUnion64(GateDescriptorLow)
1021  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1022  Bitfield<47> p; // Present
1023  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1024  Bitfield<43, 40> type;
1025  Bitfield<35, 32> IST; // IST pointer to TSS, new stack for exceptions
1026  Bitfield<31, 16> selector; // Target Code-Segment Selector
1027  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1028 EndBitUnion(GateDescriptorLow)
1029 
1030 BitUnion64(GateDescriptorHigh)
1031  Bitfield<31, 0> offset; // Target Code-Segment Offset
1032 EndBitUnion(GateDescriptorHigh)
1033 
1037 BitUnion64(GDTR)
1038 EndBitUnion(GDTR)
1039 
1040 BitUnion64(IDTR)
1041 EndBitUnion(IDTR)
1042 
1043 BitUnion64(LDTR)
1044 EndBitUnion(LDTR)
1045 
1049 BitUnion64(TR)
1050 EndBitUnion(TR)
1051 
1052 
1056 BitUnion64(LocalApicBase)
1057  Bitfield<51, 12> base;
1058  Bitfield<11> enable;
1059  Bitfield<8> bsp;
1060 EndBitUnion(LocalApicBase)
1061 
1062 } // namespace X86ISA
1063 } // namespace gem5
1064 
1065 #endif // __ARCH_X86_INTREGS_HH__
void setter(uint64_t &storage, uint32_t limit)
Definition: misc.hh:907
uint32_t getter(const uint64_t &storage) const
Definition: misc.hh:897
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:204
Bitfield< 3 > wr
Bitfield< 3, 0 > b0
Definition: qarma.hh:66
Bitfield< 11 > id
Definition: misc.hh:126
static bool isValid(int index)
Definition: misc.hh:412
static RegIndex mcStatus(int index)
Definition: misc.hh:456
static RegIndex cr(int index)
Definition: misc.hh:421
static RegIndex mtrrPhysBase(int index)
Definition: misc.hh:435
static RegIndex iorrMask(int index)
Definition: misc.hh:498
static RegIndex mcMisc(int index)
Definition: misc.hh:470
static RegIndex perfEvtCtr(int index)
Definition: misc.hh:484
static RegIndex segSel(int index)
Definition: misc.hh:505
static RegIndex segAttr(int index)
Definition: misc.hh:533
static RegIndex perfEvtSel(int index)
Definition: misc.hh:477
static RegIndex segBase(int index)
Definition: misc.hh:512
static RegIndex segLimit(int index)
Definition: misc.hh:526
static RegIndex mcCtl(int index)
Definition: misc.hh:449
static RegIndex iorrBase(int index)
Definition: misc.hh:491
static RegIndex mtrrPhysMask(int index)
Definition: misc.hh:442
static RegIndex dr(int index)
Definition: misc.hh:428
static RegIndex segEffBase(int index)
Definition: misc.hh:519
static RegIndex mcAddr(int index)
Definition: misc.hh:463
Bitfield< 19 > pc
Definition: misc.hh:812
Bitfield< 1 > w
Definition: pagetable.hh:150
Bitfield< 8 > g
Definition: pagetable.hh:143
Bitfield< 21, 20 > rw1
Definition: misc.hh:676
Bitfield< 46, 45 > dpl
Definition: misc.hh:933
Bitfield< 35, 32 > IST
Definition: misc.hh:1025
Bitfield< 10 > osxmmexcpt
Definition: misc.hh:634
Bitfield< 15, 14 > altAddr
Definition: misc.hh:591
Bitfield< 5 > pae
Definition: misc.hh:640
Bitfield< 0 > vme
Definition: misc.hh:645
Bitfield< 3 > ecf
Definition: misc.hh:554
Bitfield< 2 > b2
Definition: misc.hh:655
Bitfield< 29, 28 > rw3
Definition: misc.hh:680
Bitfield< 8 > lme
Definition: misc.hh:789
Bitfield< 23, 22 > len1
Definition: misc.hh:677
Bitfield< 17, 16 > rw0
Definition: misc.hh:674
Bitfield< 15 > system
Definition: misc.hh:1004
Bitfield< 18 > am
Definition: misc.hh:602
Bitfield< 7 > g3
Definition: misc.hh:670
Bitfield< 11, 10 > altOp
Definition: misc.hh:589
Bitfield< 1 > rInit
Definition: misc.hh:843
Bitfield< 60 > en
Definition: misc.hh:773
Bitfield< 11 > enable
Definition: misc.hh:1058
Bitfield< 0 > pe
Definition: misc.hh:609
Bitfield< 3 > pb1
Definition: misc.hh:724
Bitfield< 10 > lma
Definition: misc.hh:790
Bitfield< 3, 1 > submode
Definition: misc.hh:584
Bitfield< 4 > longMode
Definition: misc.hh:996
Bitfield< 17 > vm
Definition: misc.hh:567
Bitfield< 31, 16 > modelSpecificCode
Definition: misc.hh:768
Bitfield< 9, 8 > defOp
Definition: misc.hh:588
Bitfield< 13 > gd
Definition: misc.hh:673
Bitfield< 51, 48 > limitHigh
Definition: misc.hh:929
Bitfield< 17, 16 > stack
Definition: misc.hh:592
Bitfield< 31, 24 > counterMask
Definition: misc.hh:816
Bitfield< 6 > mce
Definition: misc.hh:639
Bitfield< 4 > pb2
Definition: misc.hh:725
Bitfield< 8 > bsp
Definition: misc.hh:1059
Bitfield< 11 > of
Definition: misc.hh:571
Bitfield< 12 > svme
Definition: misc.hh:792
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
Bitfield< 4 > pse
Definition: misc.hh:641
Bitfield< 17 > os
Definition: misc.hh:810
const int NumCRegs
Definition: x86_traits.hh:56
Bitfield< 1 > enter
Definition: misc.hh:853
Bitfield< 14 > expandDown
Definition: misc.hh:1003
Bitfield< 63, 48 > sysretCsAndSs
Definition: misc.hh:799
Bitfield< 19, 18 > len0
Definition: misc.hh:675
Bitfield< 1 > mp
Definition: misc.hh:608
Bitfield< 58 > addrv
Definition: misc.hh:771
Bitfield< 39, 16 > baseLow
Definition: misc.hh:922
Bitfield< 63 > val
Definition: misc.hh:776
Bitfield< 3 > b3
Definition: misc.hh:656
Bitfield< 56, 32 > otherInfo
Definition: misc.hh:769
Bitfield< 7 > sf
Definition: misc.hh:550
Bitfield< 2 > unusable
Definition: misc.hh:994
Bitfield< 19 > mfdm
Definition: misc.hh:821
Bitfield< 54 > b
Definition: misc.hh:926
Bitfield< 59 > miscv
Definition: misc.hh:772
Bitfield< 1 > btf
Definition: misc.hh:722
EndSubBitUnion(type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, misc_reg::NumRegs, debug::MiscRegs)
Bitfield< 5, 4 > cpl
Definition: misc.hh:585
Bitfield< 2 > l1
Definition: misc.hh:665
Bitfield< 6 > d
Definition: pagetable.hh:145
Bitfield< 2 > pb0
Definition: misc.hh:723
Bitfield< 27, 26 > len2
Definition: misc.hh:679
Bitfield< 2 > ti
Definition: misc.hh:868
Bitfield< 10 > wc
Definition: misc.hh:688
Bitfield< 1 > g0
Definition: misc.hh:664
Bitfield< 3 > exit
Definition: misc.hh:855
BitfieldType< SegDescriptorLimit > limit
Definition: misc.hh:931
Bitfield< 61 > uc
Definition: misc.hh:774
Bitfield< 7 > present
Definition: misc.hh:999
Bitfield< 31, 16 > selector
Definition: misc.hh:1010
Bitfield< 31, 30 > len3
Definition: misc.hh:681
X87StatusBit
Definition: misc.hh:89
@ StackFaultBit
Definition: misc.hh:99
@ ErrSummaryBit
Definition: misc.hh:100
Bitfield< 9 > osfxsr
Definition: misc.hh:636
SubBitUnion(type, 43, 40) Bitfield< 43 > codeOrData
Bitfield< 42 > c
Definition: misc.hh:940
constexpr uint32_t CcFlagMask
Definition: misc.hh:73
Bitfield< 57 > pcc
Definition: misc.hh:770
Bitfield< 62 > over
Definition: misc.hh:775
Bitfield< 1 > eipv
Definition: misc.hh:716
Bitfield< 7 > pge
Definition: misc.hh:638
Bitfield< 18 > ac
Definition: misc.hh:566
Bitfield< 23 > inv
Definition: misc.hh:815
Bitfield< 3 > defaultSize
Definition: misc.hh:995
Bitfield< 15, 0 > limitLow
Definition: misc.hh:930
Bitfield< 3 > ts
Definition: misc.hh:606
Bitfield< 31, 5 > paePdtb
Definition: misc.hh:622
Bitfield< 13 > bd
Definition: misc.hh:657
BitUnion64(VAddr) Bitfield< 20
Bitfield< 19 > vif
Definition: misc.hh:565
Bitfield< 10 > fe
Definition: misc.hh:759
Bitfield< 2 > em
Definition: misc.hh:607
Bitfield< 1 > pvi
Definition: misc.hh:644
Bitfield< 13, 12 > defAddr
Definition: misc.hh:590
Bitfield< 13, 12 > iopl
Definition: misc.hh:570
Bitfield< 15, 3 > si
Definition: misc.hh:867
Bitfield< 20 > intEn
Definition: misc.hh:813
Bitfield< 8 > fix
Definition: misc.hh:687
Bitfield< 21 > tom2
Definition: misc.hh:823
Bitfield< 9 > ge
Definition: misc.hh:672
Bitfield< 0 > cf
Definition: misc.hh:556
Bitfield< 3 > g1
Definition: misc.hh:666
Bitfield< 5 > ezf
Definition: misc.hh:552
Bitfield< 2 > smiCycle
Definition: misc.hh:854
Bitfield< 20 > mvdm
Definition: misc.hh:822
Bitfield< 4 > l2
Definition: misc.hh:667
Bitfield< 2 > tsd
Definition: misc.hh:643
Bitfield< 14 > ffxsr
Definition: misc.hh:793
Bitfield< 8 > pce
Definition: misc.hh:637
Bitfield< 11 > nxe
Definition: misc.hh:791
Bitfield< 4 > pcd
Definition: pagetable.hh:147
Bitfield< 1, 0 > rpl
Definition: misc.hh:869
Bitfield< 14 > nt
Definition: misc.hh:569
Bitfield< 8 > MCGCP
Definition: misc.hh:711
Bitfield< 4 > rsmCycle
Definition: misc.hh:856
Bitfield< 3 > mode
Definition: types.hh:192
Bitfield< 0 > p
Definition: pagetable.hh:151
Bitfield< 13 > readable
Definition: misc.hh:1002
Bitfield< 31, 12 > pdtb
Definition: misc.hh:620
Bitfield< 51, 12 > physmask
Definition: misc.hh:740
Bitfield< 6 > paging
Definition: misc.hh:586
Bitfield< 5 > ne
Definition: misc.hh:604
Bitfield< 25, 24 > rw2
Definition: misc.hh:678
Bitfield< 17 > pcide
Definition: misc.hh:631
Bitfield< 4 > rd
Definition: misc.hh:828
Bitfield< 5, 3 > index
Definition: types.hh:98
Bitfield< 8 > tf
Definition: misc.hh:574
Bitfield< 15 > bt
Definition: misc.hh:659
Bitfield< 41 > r
Definition: misc.hh:941
Bitfield< 29 > nw
Definition: misc.hh:601
Bitfield< 8 > le
Definition: misc.hh:671
Bitfield< 7 > prot
Definition: misc.hh:587
Bitfield< 16 > usr
Definition: misc.hh:809
constexpr uint32_t CfofMask
Definition: misc.hh:72
Bitfield< 1 > b1
Definition: misc.hh:654
Bitfield< 9 > intf
Definition: misc.hh:573
Bitfield< 51, 12 > physbase
Definition: misc.hh:735
Bitfield< 11 > e
Definition: misc.hh:760
Bitfield< 11, 0 > pcid
Definition: misc.hh:624
Bitfield< 5 > pb3
Definition: misc.hh:726
Bitfield< 2 > mcip
Definition: misc.hh:717
const int NumDRegs
Definition: x86_traits.hh:57
Bitfield< 6 > granularity
Definition: misc.hh:998
Bitfield< 2 > pf
Definition: misc.hh:555
Bitfield< 16 > wp
Definition: misc.hh:603
Bitfield< 4 > af
Definition: misc.hh:553
Bitfield< 6, 3 > v
Definition: types.hh:125
Bitfield< 6 > zf
Definition: misc.hh:551
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
Bitfield< 15, 0 > offsetLow
Definition: misc.hh:1009
@ VIFBit
Definition: misc.hh:83
@ VIPBit
Definition: misc.hh:84
Bitfield< 44 > s
Definition: misc.hh:934
Bitfield< 4 > et
Definition: misc.hh:605
Bitfield< 16 > rf
Definition: misc.hh:568
Bitfield< 20 > vip
Definition: misc.hh:564
Bitfield< 2 > disA20M
Definition: misc.hh:844
Bitfield< 53 > l
Definition: misc.hh:927
Bitfield< 6 > l3
Definition: misc.hh:669
Bitfield< 10 > df
Definition: misc.hh:572
BitUnion32(TriggerIntMessage) Bitfield< 7
@ ECFBit
Definition: misc.hh:63
@ EZFBit
Definition: misc.hh:65
Bitfield< 12 > writable
Definition: misc.hh:1001
Bitfield< 15, 8 > unitMask
Definition: misc.hh:808
Bitfield< 5 > g2
Definition: misc.hh:668
Bitfield< 30 > cd
Definition: misc.hh:600
Bitfield< 5 > a
Definition: pagetable.hh:146
Bitfield< 3 > de
Definition: misc.hh:642
Bitfield< 14 > bs
Definition: misc.hh:658
Bitfield< 47, 32 > syscallCsAndSs
Definition: misc.hh:798
Bitfield< 16 > fsgsbase
Definition: misc.hh:632
Bitfield< 3 > pwt
Definition: pagetable.hh:148
Bitfield< 11, 9 > avl
Definition: pagetable.hh:142
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
constexpr char MiscRegClassName[]
Definition: reg_class.hh:79
uint16_t RegIndex
Definition: types.hh:176
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:68

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