38 #ifndef __ARCH_X86_MISCREGS_HH__
39 #define __ARCH_X86_MISCREGS_HH__
46 #include "debug/MiscRegs.hh"
630 Bitfield<18> osxsave;
876 class SegDescriptorBase
880 getter(
const uint64_t &storage)
const
882 return (
bits(storage, 63, 56) << 24) |
bits(storage, 39, 16);
886 setter(uint64_t &storage, uint32_t
base)
899 uint32_t
limit = (
bits(storage, 51, 48) << 16) |
900 bits(storage, 15, 0);
901 if (
bits(storage, 55))
911 "Inlimitid segment limit %#x",
limit);
937 Bitfield<43> codeOrData;
966 Bitfield<46, 45>
dpl;
969 Bitfield<43> codeOrData;
989 Bitfield<31, 0>
base;
1000 Bitfield<11, 8>
type;
1012 Bitfield<46, 45>
dpl;
1013 Bitfield<43, 40>
type;
1014 Bitfield<36, 32>
count;
1023 Bitfield<46, 45>
dpl;
1024 Bitfield<43, 40>
type;
1057 Bitfield<51, 12>
base;
void setter(uint64_t &storage, uint32_t limit)
uint32_t getter(const uint64_t &storage) const
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
static bool isValid(int index)
static RegIndex mcStatus(int index)
static RegIndex cr(int index)
static RegIndex mtrrPhysBase(int index)
static RegIndex iorrMask(int index)
static RegIndex mcMisc(int index)
static RegIndex perfEvtCtr(int index)
static RegIndex segSel(int index)
static RegIndex segAttr(int index)
static RegIndex perfEvtSel(int index)
static RegIndex segBase(int index)
static RegIndex segLimit(int index)
static RegIndex mcCtl(int index)
static RegIndex iorrBase(int index)
static RegIndex mtrrPhysMask(int index)
static RegIndex dr(int index)
static RegIndex segEffBase(int index)
static RegIndex mcAddr(int index)
Bitfield< 10 > osxmmexcpt
Bitfield< 15, 14 > altAddr
Bitfield< 31, 16 > modelSpecificCode
Bitfield< 51, 48 > limitHigh
Bitfield< 31, 24 > counterMask
Bitfield< 14 > expandDown
Bitfield< 63, 48 > sysretCsAndSs
Bitfield< 39, 16 > baseLow
Bitfield< 56, 32 > otherInfo
EndSubBitUnion(type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, misc_reg::NumRegs, debug::MiscRegs)
BitfieldType< SegDescriptorLimit > limit
Bitfield< 31, 16 > selector
SubBitUnion(type, 43, 40) Bitfield< 43 > codeOrData
constexpr uint32_t CcFlagMask
Bitfield< 3 > defaultSize
Bitfield< 15, 0 > limitLow
Bitfield< 31, 5 > paePdtb
BitUnion64(VAddr) Bitfield< 20
Bitfield< 13, 12 > defAddr
Bitfield< 51, 12 > physmask
constexpr uint32_t CfofMask
Bitfield< 51, 12 > physbase
Bitfield< 6 > granularity
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
Bitfield< 15, 0 > offsetLow
BitUnion32(TriggerIntMessage) Bitfield< 7
Bitfield< 15, 8 > unitMask
Bitfield< 47, 32 > syscallCsAndSs
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
constexpr char MiscRegClassName[]
@ MiscRegClass
Control (misc) register.