gem5  v21.1.0.2
misc.hh
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37 
38 #ifndef __ARCH_X86_MISCREGS_HH__
39 #define __ARCH_X86_MISCREGS_HH__
40 
41 #include "arch/x86/regs/segment.hh"
42 #include "arch/x86/x86_traits.hh"
43 #include "base/bitunion.hh"
44 #include "base/logging.hh"
45 
46 //These get defined in some system headers (at least termbits.h). That confuses
47 //things here significantly.
48 #undef CR0
49 #undef CR2
50 #undef CR3
51 
52 namespace gem5
53 {
54 
55 namespace X86ISA
56 {
58  {
59  CFBit = 1 << 0,
60  PFBit = 1 << 2,
61  ECFBit = 1 << 3,
62  AFBit = 1 << 4,
63  EZFBit = 1 << 5,
64  ZFBit = 1 << 6,
65  SFBit = 1 << 7,
66  DFBit = 1 << 10,
67  OFBit = 1 << 11
68  };
69 
70  const uint32_t cfofMask = CFBit | OFBit;
71  const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit;
72 
73  enum RFLAGBit
74  {
75  TFBit = 1 << 8,
76  IFBit = 1 << 9,
77  NTBit = 1 << 14,
78  RFBit = 1 << 16,
79  VMBit = 1 << 17,
80  ACBit = 1 << 18,
81  VIFBit = 1 << 19,
82  VIPBit = 1 << 20,
83  IDBit = 1 << 21
84  };
85 
87  {
88  // Exception Flags
89  IEBit = 1 << 0,
90  DEBit = 1 << 1,
91  ZEBit = 1 << 2,
92  OEBit = 1 << 3,
93  UEBit = 1 << 4,
94  PEBit = 1 << 5,
95 
96  // !Exception Flags
97  StackFaultBit = 1 << 6,
98  ErrSummaryBit = 1 << 7,
99  CC0Bit = 1 << 8,
100  CC1Bit = 1 << 9,
101  CC2Bit = 1 << 10,
102  CC3Bit = 1 << 14,
103  BusyBit = 1 << 15,
104  };
105 
107  {
108  // Control registers
109  // Most of these are invalid. See isValidMiscReg() below.
127 
128  // Debug registers
138 
139  // Flags register
141 
142  //Register to keep handy values like the CPU mode in.
144 
145  /*
146  * Model Specific Registers
147  */
148  // Time stamp counter
150 
152 
156 
160 
162 
167 
178 
189 
201 
203 
205 
216 
227 
238 
249 
250  // Extended feature enable register
252 
256 
258 
260 
262 
269 
276 
278 
283 
288 
291 
296 
297  /*
298  * Segment registers
299  */
300  // Segment selectors
315 
316  // Hidden segment base field
331 
332  // The effective segment base, ie what is actually added to an
333  // address. In 64 bit mode this can be different from the above,
334  // namely 0.
349 
350  // Hidden segment limit field
365 
366  // Hidden segment limit attributes
381 
382  // Floating point control registers
385 
396 
397  //XXX Add "Model-Specific Registers"
398 
400 
401  // "Fake" MSRs for internally implemented devices
403 
405  };
406 
407  static inline bool
409  {
410  return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
411  index != MISCREG_CR1 &&
412  !(index > MISCREG_CR4 && index < MISCREG_CR8) &&
413  !(index > MISCREG_CR8 && index <= MISCREG_CR15));
414  }
415 
416  static inline MiscRegIndex
418  {
419  assert(index >= 0 && index < NumCRegs);
420  return (MiscRegIndex)(MISCREG_CR_BASE + index);
421  }
422 
423  static inline MiscRegIndex
425  {
426  assert(index >= 0 && index < NumDRegs);
427  return (MiscRegIndex)(MISCREG_DR_BASE + index);
428  }
429 
430  static inline MiscRegIndex
432  {
433  assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
436  }
437 
438  static inline MiscRegIndex
440  {
441  assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
444  }
445 
446  static inline MiscRegIndex
448  {
449  assert(index >= 0 && index < (MISCREG_MC_CTL_END -
452  }
453 
454  static inline MiscRegIndex
456  {
457  assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
460  }
461 
462  static inline MiscRegIndex
464  {
465  assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
468  }
469 
470  static inline MiscRegIndex
472  {
473  assert(index >= 0 && index < (MISCREG_MC_MISC_END -
476  }
477 
478  static inline MiscRegIndex
480  {
481  assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
484  }
485 
486  static inline MiscRegIndex
488  {
489  assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
492  }
493 
494  static inline MiscRegIndex
496  {
497  assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
500  }
501 
502  static inline MiscRegIndex
504  {
505  assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
508  }
509 
510  static inline MiscRegIndex
512  {
513  assert(index >= 0 && index < NUM_SEGMENTREGS);
515  }
516 
517  static inline MiscRegIndex
519  {
520  assert(index >= 0 && index < NUM_SEGMENTREGS);
522  }
523 
524  static inline MiscRegIndex
526  {
527  assert(index >= 0 && index < NUM_SEGMENTREGS);
529  }
530 
531  static inline MiscRegIndex
533  {
534  assert(index >= 0 && index < NUM_SEGMENTREGS);
536  }
537 
538  static inline MiscRegIndex
540  {
541  assert(index >= 0 && index < NUM_SEGMENTREGS);
543  }
544 
549  BitUnion64(CCFlagBits)
550  Bitfield<11> of;
551  Bitfield<7> sf;
552  Bitfield<6> zf;
553  Bitfield<5> ezf;
554  Bitfield<4> af;
555  Bitfield<3> ecf;
556  Bitfield<2> pf;
557  Bitfield<0> cf;
558  EndBitUnion(CCFlagBits)
559 
560 
563  BitUnion64(RFLAGS)
564  Bitfield<21> id; // ID Flag
565  Bitfield<20> vip; // Virtual Interrupt Pending
566  Bitfield<19> vif; // Virtual Interrupt Flag
567  Bitfield<18> ac; // Alignment Check
568  Bitfield<17> vm; // Virtual-8086 Mode
569  Bitfield<16> rf; // Resume Flag
570  Bitfield<14> nt; // Nested Task
571  Bitfield<13, 12> iopl; // I/O Privilege Level
572  Bitfield<11> of; // Overflow Flag
573  Bitfield<10> df; // Direction Flag
574  Bitfield<9> intf; // Interrupt Flag
575  Bitfield<8> tf; // Trap Flag
576  Bitfield<7> sf; // Sign Flag
577  Bitfield<6> zf; // Zero Flag
578  Bitfield<4> af; // Auxiliary Flag
579  Bitfield<2> pf; // Parity Flag
580  Bitfield<0> cf; // Carry Flag
581  EndBitUnion(RFLAGS)
582 
583  BitUnion64(HandyM5Reg)
584  Bitfield<0> mode;
585  Bitfield<3, 1> submode;
586  Bitfield<5, 4> cpl;
587  Bitfield<6> paging;
588  Bitfield<7> prot;
589  Bitfield<9, 8> defOp;
590  Bitfield<11, 10> altOp;
591  Bitfield<13, 12> defAddr;
592  Bitfield<15, 14> altAddr;
593  Bitfield<17, 16> stack;
594  EndBitUnion(HandyM5Reg)
595 
596 
599  BitUnion64(CR0)
600  Bitfield<31> pg; // Paging
601  Bitfield<30> cd; // Cache Disable
602  Bitfield<29> nw; // Not Writethrough
603  Bitfield<18> am; // Alignment Mask
604  Bitfield<16> wp; // Write Protect
605  Bitfield<5> ne; // Numeric Error
606  Bitfield<4> et; // Extension Type
607  Bitfield<3> ts; // Task Switched
608  Bitfield<2> em; // Emulation
609  Bitfield<1> mp; // Monitor Coprocessor
610  Bitfield<0> pe; // Protection Enabled
611  EndBitUnion(CR0)
612 
613  // Page Fault Virtual Address
614  BitUnion64(CR2)
615  Bitfield<31, 0> legacy;
616  EndBitUnion(CR2)
617 
618  BitUnion64(CR3)
619  Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
620  // Base Address
621  Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
622  // Base Address
623  Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
624  // Base Address
625  Bitfield<4> pcd; // Page-Level Cache Disable
626  Bitfield<3> pwt; // Page-Level Writethrough
627  EndBitUnion(CR3)
628 
629  BitUnion64(CR4)
630  Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
631  Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
632  // WRGSBASE instructions
633  Bitfield<10> osxmmexcpt; // Operating System Unmasked
634  // Exception Support
635  Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
636  Bitfield<8> pce; // Performance-Monitoring Counter Enable
637  Bitfield<7> pge; // Page-Global Enable
638  Bitfield<6> mce; // Machine Check Enable
639  Bitfield<5> pae; // Physical-Address Extension
640  Bitfield<4> pse; // Page Size Extensions
641  Bitfield<3> de; // Debugging Extensions
642  Bitfield<2> tsd; // Time Stamp Disable
643  Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
644  Bitfield<0> vme; // Virtual-8086 Mode Extensions
645  EndBitUnion(CR4)
646 
647  BitUnion64(CR8)
648  Bitfield<3, 0> tpr; // Task Priority Register
649  EndBitUnion(CR8)
650 
651  BitUnion64(DR6)
652  Bitfield<0> b0;
653  Bitfield<1> b1;
654  Bitfield<2> b2;
655  Bitfield<3> b3;
656  Bitfield<13> bd;
657  Bitfield<14> bs;
658  Bitfield<15> bt;
659  EndBitUnion(DR6)
660 
661  BitUnion64(DR7)
662  Bitfield<0> l0;
663  Bitfield<1> g0;
664  Bitfield<2> l1;
665  Bitfield<3> g1;
666  Bitfield<4> l2;
667  Bitfield<5> g2;
668  Bitfield<6> l3;
669  Bitfield<7> g3;
670  Bitfield<8> le;
671  Bitfield<9> ge;
672  Bitfield<13> gd;
673  Bitfield<17, 16> rw0;
674  Bitfield<19, 18> len0;
675  Bitfield<21, 20> rw1;
676  Bitfield<23, 22> len1;
677  Bitfield<25, 24> rw2;
678  Bitfield<27, 26> len2;
679  Bitfield<29, 28> rw3;
680  Bitfield<31, 30> len3;
681  EndBitUnion(DR7)
682 
683  // MTRR capabilities
684  BitUnion64(MTRRcap)
685  Bitfield<7, 0> vcnt; // Variable-Range Register Count
686  Bitfield<8> fix; // Fixed-Range Registers
687  Bitfield<10> wc; // Write-Combining
688  EndBitUnion(MTRRcap)
689 
693  BitUnion64(SysenterCS)
694  Bitfield<15, 0> targetCS;
695  EndBitUnion(SysenterCS)
696 
697  BitUnion64(SysenterESP)
698  Bitfield<31, 0> targetESP;
699  EndBitUnion(SysenterESP)
700 
701  BitUnion64(SysenterEIP)
702  Bitfield<31, 0> targetEIP;
703  EndBitUnion(SysenterEIP)
704 
708  BitUnion64(McgCap)
709  Bitfield<7, 0> count; // Number of error reporting register banks
710  Bitfield<8> MCGCP; // MCG_CTL register present.
711  EndBitUnion(McgCap)
712 
713  BitUnion64(McgStatus)
714  Bitfield<0> ripv; // Restart-IP valid
715  Bitfield<1> eipv; // Error-IP valid
716  Bitfield<2> mcip; // Machine check in-progress
717  EndBitUnion(McgStatus)
718 
719  BitUnion64(DebugCtlMsr)
720  Bitfield<0> lbr; // Last-branch record
721  Bitfield<1> btf; // Branch single step
722  Bitfield<2> pb0; // Performance monitoring pin control 0
723  Bitfield<3> pb1; // Performance monitoring pin control 1
724  Bitfield<4> pb2; // Performance monitoring pin control 2
725  Bitfield<5> pb3; // Performance monitoring pin control 3
726  /*uint64_t pb(int index)
727  {
728  return bits(__data, index + 2);
729  }*/
730  EndBitUnion(DebugCtlMsr)
731 
732  BitUnion64(MtrrPhysBase)
733  Bitfield<7, 0> type; // Default memory type
734  Bitfield<51, 12> physbase; // Range physical base address
735  EndBitUnion(MtrrPhysBase)
736 
737  BitUnion64(MtrrPhysMask)
738  Bitfield<11> valid; // MTRR pair enable
739  Bitfield<51, 12> physmask; // Range physical mask
740  EndBitUnion(MtrrPhysMask)
741 
742  BitUnion64(MtrrFixed)
743  /*uint64_t type(int index)
744  {
745  return bits(__data, index * 8 + 7, index * 8);
746  }*/
747  EndBitUnion(MtrrFixed)
748 
749  BitUnion64(Pat)
750  /*uint64_t pa(int index)
751  {
752  return bits(__data, index * 8 + 2, index * 8);
753  }*/
754  EndBitUnion(Pat)
755 
756  BitUnion64(MtrrDefType)
757  Bitfield<7, 0> type; // Default type
758  Bitfield<10> fe; // Fixed range enable
759  Bitfield<11> e; // MTRR enable
760  EndBitUnion(MtrrDefType)
761 
765  BitUnion64(McStatus)
766  Bitfield<15,0> mcaErrorCode;
767  Bitfield<31,16> modelSpecificCode;
768  Bitfield<56,32> otherInfo;
769  Bitfield<57> pcc; // Processor-context corrupt
770  Bitfield<58> addrv; // Error-address register valid
771  Bitfield<59> miscv; // Miscellaneous-error register valid
772  Bitfield<60> en; // Error condition enabled
773  Bitfield<61> uc; // Uncorrected error
774  Bitfield<62> over; // Status register overflow
775  Bitfield<63> val; // Valid
776  EndBitUnion(McStatus)
777 
778  BitUnion64(McCtl)
779  /*uint64_t en(int index)
780  {
781  return bits(__data, index);
782  }*/
783  EndBitUnion(McCtl)
784 
785  // Extended feature enable register
786  BitUnion64(Efer)
787  Bitfield<0> sce; // System call extensions
788  Bitfield<8> lme; // Long mode enable
789  Bitfield<10> lma; // Long mode active
790  Bitfield<11> nxe; // No-execute enable
791  Bitfield<12> svme; // Secure virtual machine enable
792  Bitfield<14> ffxsr; // Fast fxsave/fxrstor
793  EndBitUnion(Efer)
794 
795  BitUnion64(Star)
796  Bitfield<31,0> targetEip;
797  Bitfield<47,32> syscallCsAndSs;
798  Bitfield<63,48> sysretCsAndSs;
799  EndBitUnion(Star)
800 
801  BitUnion64(SfMask)
802  Bitfield<31,0> mask;
803  EndBitUnion(SfMask)
804 
805  BitUnion64(PerfEvtSel)
806  Bitfield<7,0> eventMask;
807  Bitfield<15,8> unitMask;
808  Bitfield<16> usr; // User mode
809  Bitfield<17> os; // Operating-system mode
810  Bitfield<18> e; // Edge detect
811  Bitfield<19> pc; // Pin control
812  Bitfield<20> intEn; // Interrupt enable
813  Bitfield<22> en; // Counter enable
814  Bitfield<23> inv; // Invert mask
815  Bitfield<31,24> counterMask;
816  EndBitUnion(PerfEvtSel)
817 
818  BitUnion32(Syscfg)
819  Bitfield<18> mfde; // MtrrFixDramEn
820  Bitfield<19> mfdm; // MtrrFixDramModEn
821  Bitfield<20> mvdm; // MtrrVarDramEn
822  Bitfield<21> tom2; // MtrrTom2En
823  EndBitUnion(Syscfg)
824 
825  BitUnion64(IorrBase)
826  Bitfield<3> wr; // WrMem Enable
827  Bitfield<4> rd; // RdMem Enable
828  Bitfield<51,12> physbase; // Range physical base address
829  EndBitUnion(IorrBase)
830 
831  BitUnion64(IorrMask)
832  Bitfield<11> v; // I/O register pair enable (valid)
833  Bitfield<51,12> physmask; // Range physical mask
834  EndBitUnion(IorrMask)
835 
836  BitUnion64(Tom)
837  Bitfield<51,23> physAddr; // Top of memory physical address
838  EndBitUnion(Tom)
839 
840  BitUnion64(VmCrMsr)
841  Bitfield<0> dpd;
842  Bitfield<1> rInit;
843  Bitfield<2> disA20M;
844  EndBitUnion(VmCrMsr)
845 
846  BitUnion64(IgnneMsr)
847  Bitfield<0> ignne;
848  EndBitUnion(IgnneMsr)
849 
850  BitUnion64(SmmCtlMsr)
851  Bitfield<0> dismiss;
852  Bitfield<1> enter;
853  Bitfield<2> smiCycle;
854  Bitfield<3> exit;
855  Bitfield<4> rsmCycle;
856  EndBitUnion(SmmCtlMsr)
857 
861  BitUnion64(SegSelector)
862  // The following bitfield is not defined in the ISA, but it's useful
863  // when checking selectors in larger data types to make sure they
864  // aren't too large.
865  Bitfield<63, 3> esi; // Extended selector
866  Bitfield<15, 3> si; // Selector Index
867  Bitfield<2> ti; // Table Indicator
868  Bitfield<1, 0> rpl; // Requestor Privilege Level
869  EndBitUnion(SegSelector)
870 
875  class SegDescriptorBase
876  {
877  public:
878  uint32_t
879  getter(const uint64_t &storage) const
880  {
881  return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16);
882  }
883 
884  void
885  setter(uint64_t &storage, uint32_t base)
886  {
887  replaceBits(storage, 63, 56, bits(base, 31, 24));
888  replaceBits(storage, 39, 16, bits(base, 23, 0));
889  }
890  };
891 
893  {
894  public:
895  uint32_t
896  getter(const uint64_t &storage) const
897  {
898  uint32_t limit = (bits(storage, 51, 48) << 16) |
899  bits(storage, 15, 0);
900  if (bits(storage, 55))
901  limit = (limit << 12) | mask(12);
902  return limit;
903  }
904 
905  void
906  setter(uint64_t &storage, uint32_t limit)
907  {
908  bool g = (bits(limit, 31, 24) != 0);
909  panic_if(g && bits(limit, 11, 0) != mask(12),
910  "Inlimitid segment limit %#x", limit);
911  if (g)
912  limit = limit >> 12;
913  replaceBits(storage, 51, 48, bits(limit, 23, 16));
914  replaceBits(storage, 15, 0, bits(limit, 15, 0));
915  replaceBits(storage, 55, g ? 1 : 0);
916  }
917  };
918 
919  BitUnion64(SegDescriptor)
920  Bitfield<63, 56> baseHigh;
921  Bitfield<39, 16> baseLow;
922  BitfieldType<SegDescriptorBase> base;
923  Bitfield<55> g; // Granularity
924  Bitfield<54> d; // Default Operand Size
925  Bitfield<54> b; // Default Operand Size
926  Bitfield<53> l; // Long Attribute Bit
927  Bitfield<52> avl; // Available To Software
928  Bitfield<51, 48> limitHigh;
929  Bitfield<15, 0> limitLow;
931  Bitfield<47> p; // Present
932  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
933  Bitfield<44> s; // System
934  SubBitUnion(type, 43, 40)
935  // Specifies whether this descriptor is for code or data.
936  Bitfield<43> codeOrData;
937 
938  // These bit fields are for code segments
939  Bitfield<42> c; // Conforming
940  Bitfield<41> r; // Readable
941 
942  // These bit fields are for data segments
943  Bitfield<42> e; // Expand-Down
944  Bitfield<41> w; // Writable
945 
946  // This is used for both code and data segments.
947  Bitfield<40> a; // Accessed
949  EndBitUnion(SegDescriptor)
950 
955  BitUnion64(TSSlow)
956  Bitfield<63, 56> baseHigh;
957  Bitfield<39, 16> baseLow;
958  BitfieldType<SegDescriptorBase> base;
959  Bitfield<55> g; // Granularity
960  Bitfield<52> avl; // Available To Software
961  Bitfield<51, 48> limitHigh;
962  Bitfield<15, 0> limitLow;
964  Bitfield<47> p; // Present
965  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
966  SubBitUnion(type, 43, 40)
967  // Specifies whether this descriptor is for code or data.
968  Bitfield<43> codeOrData;
969 
970  // These bit fields are for code segments
971  Bitfield<42> c; // Conforming
972  Bitfield<41> r; // Readable
973 
974  // These bit fields are for data segments
975  Bitfield<42> e; // Expand-Down
976  Bitfield<41> w; // Writable
977 
978  // This is used for both code and data segments.
979  Bitfield<40> a; // Accessed
981  EndBitUnion(TSSlow)
982 
987  BitUnion64(TSShigh)
988  Bitfield<31, 0> base;
989  EndBitUnion(TSShigh)
990 
991  BitUnion64(SegAttr)
992  Bitfield<1, 0> dpl;
993  Bitfield<2> unusable;
994  Bitfield<3> defaultSize;
995  Bitfield<4> longMode;
996  Bitfield<5> avl;
997  Bitfield<6> granularity;
998  Bitfield<7> present;
999  Bitfield<11, 8> type;
1000  Bitfield<12> writable;
1001  Bitfield<13> readable;
1002  Bitfield<14> expandDown;
1003  Bitfield<15> system;
1004  EndBitUnion(SegAttr)
1005 
1006  BitUnion64(GateDescriptor)
1007  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1008  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1009  Bitfield<31, 16> selector; // Target Code-Segment Selector
1010  Bitfield<47> p; // Present
1011  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1012  Bitfield<43, 40> type;
1013  Bitfield<36, 32> count; // Parameter Count
1014  EndBitUnion(GateDescriptor)
1015 
1019  BitUnion64(GateDescriptorLow)
1020  Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1021  Bitfield<47> p; // Present
1022  Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1023  Bitfield<43, 40> type;
1024  Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling
1025  Bitfield<31, 16> selector; // Target Code-Segment Selector
1026  Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1027  EndBitUnion(GateDescriptorLow)
1028 
1029  BitUnion64(GateDescriptorHigh)
1030  Bitfield<31, 0> offset; // Target Code-Segment Offset
1031  EndBitUnion(GateDescriptorHigh)
1032 
1036  BitUnion64(GDTR)
1037  EndBitUnion(GDTR)
1038 
1039  BitUnion64(IDTR)
1040  EndBitUnion(IDTR)
1041 
1042  BitUnion64(LDTR)
1043  EndBitUnion(LDTR)
1044 
1048  BitUnion64(TR)
1049  EndBitUnion(TR)
1050 
1051 
1055  BitUnion64(LocalApicBase)
1056  Bitfield<51, 12> base;
1057  Bitfield<11> enable;
1058  Bitfield<8> bsp;
1059  EndBitUnion(LocalApicBase)
1060 
1061 } // namespace X86ISA
1062 } // namespace gem5
1063 
1064 #endif // __ARCH_X86_INTREGS_HH__
gem5::X86ISA::intf
Bitfield< 9 > intf
Definition: misc.hh:574
gem5::X86ISA::tom2
Bitfield< 21 > tom2
Definition: misc.hh:822
gem5::X86ISA::MISCREG_PERF_EVT_CTR1
@ MISCREG_PERF_EVT_CTR1
Definition: misc.hh:272
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_4
@ MISCREG_MTRR_PHYS_MASK_4
Definition: misc.hh:184
gem5::X86ISA::MISCREG_ES
@ MISCREG_ES
Definition: misc.hh:302
gem5::X86ISA::IST
Bitfield< 35, 32 > IST
Definition: misc.hh:1024
gem5::X86ISA::MISCREG_PERF_EVT_CTR_BASE
@ MISCREG_PERF_EVT_CTR_BASE
Definition: misc.hh:270
gem5::X86ISA::mask
mask
Definition: misc.hh:802
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_2
@ MISCREG_MTRR_PHYS_BASE_2
Definition: misc.hh:171
gem5::X86ISA::iopl
Bitfield< 13, 12 > iopl
Definition: misc.hh:571
gem5::X86ISA::pc
Bitfield< 19 > pc
Definition: misc.hh:811
gem5::X86ISA::MISCREG_LAST_EXCEPTION_TO_IP
@ MISCREG_LAST_EXCEPTION_TO_IP
Definition: misc.hh:166
gem5::X86ISA::DFBit
@ DFBit
Definition: misc.hh:66
gem5::X86ISA::targetEIP
targetEIP
Definition: misc.hh:702
gem5::X86ISA::MISCREG_FS_BASE
@ MISCREG_FS_BASE
Definition: misc.hh:322
gem5::X86ISA::fe
Bitfield< 10 > fe
Definition: misc.hh:758
gem5::X86ISA::MISCREG_MC2_ADDR
@ MISCREG_MC2_ADDR
Definition: misc.hh:231
x86_traits.hh
gem5::X86ISA::SFBit
@ SFBit
Definition: misc.hh:65
gem5::X86ISA::MISCREG_M5_REG
@ MISCREG_M5_REG
Definition: misc.hh:143
gem5::X86ISA::longMode
Bitfield< 4 > longMode
Definition: misc.hh:995
gem5::X86ISA::bt
Bitfield< 15 > bt
Definition: misc.hh:658
gem5::X86ISA::MISCREG_SEG_SEL
static MiscRegIndex MISCREG_SEG_SEL(int index)
Definition: misc.hh:511
gem5::X86ISA::MISCREG_DS
@ MISCREG_DS
Definition: misc.hh:305
gem5::X86ISA::pcc
Bitfield< 57 > pcc
Definition: misc.hh:769
gem5::X86ISA::MISCREG_TR_EFF_BASE
@ MISCREG_TR_EFF_BASE
Definition: misc.hh:347
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_7
@ MISCREG_MTRR_PHYS_MASK_7
Definition: misc.hh:187
gem5::X86ISA::MISCREG_SS_LIMIT
@ MISCREG_SS_LIMIT
Definition: misc.hh:354
gem5::X86ISA::MISCREG_TR
@ MISCREG_TR
Definition: misc.hh:313
gem5::X86ISA::pvi
Bitfield< 1 > pvi
Definition: misc.hh:643
gem5::X86ISA::MISCREG_DR1
@ MISCREG_DR1
Definition: misc.hh:131
gem5::X86ISA::MISCREG_MC3_MISC
@ MISCREG_MC3_MISC
Definition: misc.hh:243
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_7
@ MISCREG_MTRR_PHYS_BASE_7
Definition: misc.hh:176
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_1
@ MISCREG_MTRR_PHYS_BASE_1
Definition: misc.hh:170
gem5::X86ISA::MISCREG_IORR_MASK_BASE
@ MISCREG_IORR_MASK_BASE
Definition: misc.hh:284
gem5::X86ISA::MISCREG_MTRR_FIX_4K_F8000
@ MISCREG_MTRR_FIX_4K_F8000
Definition: misc.hh:200
gem5::X86ISA::IDBit
@ IDBit
Definition: misc.hh:83
gem5::X86ISA::MISCREG_DEBUG_CTL_MSR
@ MISCREG_DEBUG_CTL_MSR
Definition: misc.hh:161
gem5::X86ISA::paging
Bitfield< 6 > paging
Definition: misc.hh:587
gem5::X86ISA::l3
Bitfield< 6 > l3
Definition: misc.hh:668
gem5::X86ISA::MISCREG_MC6_CTL
@ MISCREG_MC6_CTL
Definition: misc.hh:213
gem5::X86ISA::ZEBit
@ ZEBit
Definition: misc.hh:91
gem5::X86ISA::e
Bitfield< 11 > e
Definition: misc.hh:759
gem5::X86ISA::zf
Bitfield< 6 > zf
Definition: misc.hh:552
gem5::X86ISA::isValidMiscReg
static bool isValidMiscReg(int index)
Definition: misc.hh:408
gem5::X86ISA::MISCREG_MS_EFF_BASE
@ MISCREG_MS_EFF_BASE
Definition: misc.hh:346
gem5::X86ISA::MISCREG_TSL
@ MISCREG_TSL
Definition: misc.hh:309
gem5::X86ISA::rw3
Bitfield< 29, 28 > rw3
Definition: misc.hh:679
gem5::X86ISA::mvdm
Bitfield< 20 > mvdm
Definition: misc.hh:821
gem5::X86ISA::MISCREG_MS
@ MISCREG_MS
Definition: misc.hh:312
gem5::X86ISA::MISCREG_CR8
@ MISCREG_CR8
Definition: misc.hh:119
gem5::X86ISA::MISCREG_MC5_MISC
@ MISCREG_MC5_MISC
Definition: misc.hh:245
gem5::X86ISA::IEBit
@ IEBit
Definition: misc.hh:89
gem5::X86ISA::MISCREG_MC_ADDR
static MiscRegIndex MISCREG_MC_ADDR(int index)
Definition: misc.hh:463
gem5::X86ISA::MISCREG_CR7
@ MISCREG_CR7
Definition: misc.hh:118
gem5::X86ISA::mce
Bitfield< 6 > mce
Definition: misc.hh:638
gem5::X86ISA::MISCREG_PERF_EVT_SEL0
@ MISCREG_PERF_EVT_SEL0
Definition: misc.hh:264
gem5::X86ISA::defOp
Bitfield< 9, 8 > defOp
Definition: misc.hh:589
gem5::X86ISA::MISCREG_MC5_ADDR
@ MISCREG_MC5_ADDR
Definition: misc.hh:234
gem5::X86ISA::MISCREG_DR_BASE
@ MISCREG_DR_BASE
Definition: misc.hh:129
gem5::X86ISA::MISCREG_DR3
@ MISCREG_DR3
Definition: misc.hh:133
gem5::X86ISA::MISCREG_MTRR_FIX_4K_E8000
@ MISCREG_MTRR_FIX_4K_E8000
Definition: misc.hh:198
gem5::X86ISA::CC2Bit
@ CC2Bit
Definition: misc.hh:101
gem5::X86ISA::MISCREG_APIC_BASE
@ MISCREG_APIC_BASE
Definition: misc.hh:399
gem5::X86ISA::MISCREG_MC0_MISC
@ MISCREG_MC0_MISC
Definition: misc.hh:240
gem5::X86ISA::df
Bitfield< 10 > df
Definition: misc.hh:573
gem5::X86ISA::MCGCP
Bitfield< 8 > MCGCP
Definition: misc.hh:710
gem5::X86ISA::MISCREG_TSG_LIMIT
@ MISCREG_TSG_LIMIT
Definition: misc.hh:360
gem5::X86ISA::ErrSummaryBit
@ ErrSummaryBit
Definition: misc.hh:98
gem5::X86ISA::len3
Bitfield< 31, 30 > len3
Definition: misc.hh:680
gem5::X86ISA::MISCREG_CR6
@ MISCREG_CR6
Definition: misc.hh:117
gem5::X86ISA::MISCREG_CR1
@ MISCREG_CR1
Definition: misc.hh:112
gem5::X86ISA::wc
Bitfield< 10 > wc
Definition: misc.hh:687
gem5::X86ISA::MISCREG_VM_HSAVE_PA
@ MISCREG_VM_HSAVE_PA
Definition: misc.hh:295
gem5::X86ISA::MISCREG_MTRR_FIX_4K_E0000
@ MISCREG_MTRR_FIX_4K_E0000
Definition: misc.hh:197
gem5::X86ISA::MISCREG_SEG_LIMIT
static MiscRegIndex MISCREG_SEG_LIMIT(int index)
Definition: misc.hh:532
gem5::X86ISA::len1
Bitfield< 23, 22 > len1
Definition: misc.hh:676
gem5::X86ISA::MISCREG_DS_EFF_BASE
@ MISCREG_DS_EFF_BASE
Definition: misc.hh:339
gem5::X86ISA::MISCREG_MCG_STATUS
@ MISCREG_MCG_STATUS
Definition: misc.hh:158
gem5::X86ISA::ZFBit
@ ZFBit
Definition: misc.hh:64
gem5::X86ISA::pb3
Bitfield< 5 > pb3
Definition: misc.hh:725
gem5::X86ISA::MISCREG_SEG_ATTR
static MiscRegIndex MISCREG_SEG_ATTR(int index)
Definition: misc.hh:539
gem5::X86ISA::CC0Bit
@ CC0Bit
Definition: misc.hh:99
gem5::X86ISA::MISCREG_MC_MISC_BASE
@ MISCREG_MC_MISC_BASE
Definition: misc.hh:239
gem5::X86ISA::g2
Bitfield< 5 > g2
Definition: misc.hh:667
gem5::replaceBits
constexpr void replaceBits(T &val, unsigned first, unsigned last, B bit_val)
A convenience function to replace bits first to last of val with bit_val in place.
Definition: bitfield.hh:197
gem5::X86ISA::MISCREG_MTRR_FIX_4K_C0000
@ MISCREG_MTRR_FIX_4K_C0000
Definition: misc.hh:193
gem5::X86ISA::MISCREG_CR_BASE
@ MISCREG_CR_BASE
Definition: misc.hh:110
gem5::X86ISA::MISCREG_MTRRCAP
@ MISCREG_MTRRCAP
Definition: misc.hh:151
gem5::X86ISA::v
Bitfield< 6, 3 > v
Definition: types.hh:125
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_3
@ MISCREG_MTRR_PHYS_MASK_3
Definition: misc.hh:183
gem5::SparcISA::id
Bitfield< 11 > id
Definition: misc.hh:124
gem5::X86ISA::b
Bitfield< 54 > b
Definition: misc.hh:925
gem5::X86ISA::mcip
Bitfield< 2 > mcip
Definition: misc.hh:716
gem5::X86ISA::NumDRegs
const int NumDRegs
Definition: x86_traits.hh:57
gem5::X86ISA::offset
offset
Definition: misc.hh:1030
gem5::X86ISA::MISCREG_SS_BASE
@ MISCREG_SS_BASE
Definition: misc.hh:320
gem5::X86ISA::pge
Bitfield< 7 > pge
Definition: misc.hh:637
gem5::X86ISA::baseHigh
baseHigh
Definition: misc.hh:920
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::X86ISA::MISCREG_FIOFF
@ MISCREG_FIOFF
Definition: misc.hh:392
gem5::X86ISA::MISCREG_MC0_CTL
@ MISCREG_MC0_CTL
Definition: misc.hh:207
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_BASE
@ MISCREG_MTRR_PHYS_MASK_BASE
Definition: misc.hh:179
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_END
@ MISCREG_MTRR_PHYS_MASK_END
Definition: misc.hh:188
gem5::X86ISA::MISCREG_IORR_MASK
static MiscRegIndex MISCREG_IORR_MASK(int index)
Definition: misc.hh:503
gem5::X86ISA::MISCREG_FISEG
@ MISCREG_FISEG
Definition: misc.hh:391
gem5::X86ISA::MISCREG_MC_STATUS_BASE
@ MISCREG_MC_STATUS_BASE
Definition: misc.hh:217
gem5::X86ISA::g3
Bitfield< 7 > g3
Definition: misc.hh:669
gem5::X86ISA::MISCREG_SYSENTER_ESP
@ MISCREG_SYSENTER_ESP
Definition: misc.hh:154
gem5::X86ISA::osxmmexcpt
Bitfield< 10 > osxmmexcpt
Definition: misc.hh:633
gem5::X86ISA::MISCREG_FOOFF
@ MISCREG_FOOFF
Definition: misc.hh:394
gem5::X86ISA::MISCREG_CR5
@ MISCREG_CR5
Definition: misc.hh:116
gem5::X86ISA::SegDescriptorLimit
Definition: misc.hh:892
gem5::X86ISA::ACBit
@ ACBit
Definition: misc.hh:80
gem5::X86ISA::le
Bitfield< 8 > le
Definition: misc.hh:670
gem5::X86ISA::smiCycle
Bitfield< 2 > smiCycle
Definition: misc.hh:853
gem5::X86ISA::MISCREG_IORR_MASK_END
@ MISCREG_IORR_MASK_END
Definition: misc.hh:287
gem5::X86ISA::defaultSize
Bitfield< 3 > defaultSize
Definition: misc.hh:994
gem5::X86ISA::of
Bitfield< 11 > of
Definition: misc.hh:572
gem5::X86ISA::pb1
Bitfield< 3 > pb1
Definition: misc.hh:723
gem5::X86ISA::MISCREG_IORR_BASE0
@ MISCREG_IORR_BASE0
Definition: misc.hh:280
gem5::X86ISA::b2
Bitfield< 2 > b2
Definition: misc.hh:654
gem5::X86ISA::MISCREG_GS_LIMIT
@ MISCREG_GS_LIMIT
Definition: misc.hh:357
gem5::X86ISA::MISCREG_MC_CTL
static MiscRegIndex MISCREG_MC_CTL(int index)
Definition: misc.hh:447
gem5::X86ISA::system
Bitfield< 15 > system
Definition: misc.hh:1003
gem5::X86ISA::MISCREG_MTRR_FIX_4K_D8000
@ MISCREG_MTRR_FIX_4K_D8000
Definition: misc.hh:196
gem5::X86ISA::l
Bitfield< 53 > l
Definition: misc.hh:926
gem5::X86ISA::MISCREG_PERF_EVT_CTR2
@ MISCREG_PERF_EVT_CTR2
Definition: misc.hh:273
gem5::X86ISA::MISCREG_MC1_ADDR
@ MISCREG_MC1_ADDR
Definition: misc.hh:230
gem5::X86ISA::MISCREG_MC6_ADDR
@ MISCREG_MC6_ADDR
Definition: misc.hh:235
gem5::X86ISA::MISCREG_LS_EFF_BASE
@ MISCREG_LS_EFF_BASE
Definition: misc.hh:345
gem5::X86ISA::MISCREG_ES_LIMIT
@ MISCREG_ES_LIMIT
Definition: misc.hh:352
gem5::X86ISA::rw0
Bitfield< 17, 16 > rw0
Definition: misc.hh:673
gem5::X86ISA::MISCREG_X87_TOP
@ MISCREG_X87_TOP
Definition: misc.hh:383
gem5::X86ISA::MISCREG_MC_CTL_BASE
@ MISCREG_MC_CTL_BASE
Definition: misc.hh:206
gem5::X86ISA::MISCREG_ES_BASE
@ MISCREG_ES_BASE
Definition: misc.hh:318
gem5::X86ISA::vcnt
vcnt
Definition: misc.hh:685
gem5::X86ISA::pb2
Bitfield< 4 > pb2
Definition: misc.hh:724
gem5::X86ISA::MISCREG_MC7_ADDR
@ MISCREG_MC7_ADDR
Definition: misc.hh:236
gem5::X86ISA::tpr
tpr
Definition: misc.hh:648
gem5::X86ISA::limit
BitfieldType< SegDescriptorLimit > limit
Definition: misc.hh:930
gem5::X86ISA::UEBit
@ UEBit
Definition: misc.hh:93
gem5::X86ISA::len0
Bitfield< 19, 18 > len0
Definition: misc.hh:674
gem5::X86ISA::rInit
Bitfield< 1 > rInit
Definition: misc.hh:842
gem5::X86ISA::MISCREG_MC2_CTL
@ MISCREG_MC2_CTL
Definition: misc.hh:209
gem5::X86ISA::MISCREG_TR_BASE
@ MISCREG_TR_BASE
Definition: misc.hh:329
gem5::X86ISA::rf
Bitfield< 16 > rf
Definition: misc.hh:569
gem5::X86ISA::MISCREG_MCG_CAP
@ MISCREG_MCG_CAP
Definition: misc.hh:157
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::X86ISA::NUM_MISCREGS
@ NUM_MISCREGS
Definition: misc.hh:404
gem5::X86ISA::MISCREG_STAR
@ MISCREG_STAR
Definition: misc.hh:253
gem5::X86ISA::MISCREG_DR2
@ MISCREG_DR2
Definition: misc.hh:132
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK
static MiscRegIndex MISCREG_MTRR_PHYS_MASK(int index)
Definition: misc.hh:439
gem5::X86ISA::SegDescriptorLimit::setter
void setter(uint64_t &storage, uint32_t limit)
Definition: misc.hh:906
gem5::X86ISA::MISCREG_MC0_ADDR
@ MISCREG_MC0_ADDR
Definition: misc.hh:229
gem5::X86ISA::ne
Bitfield< 5 > ne
Definition: misc.hh:605
gem5::X86ISA::defAddr
Bitfield< 13, 12 > defAddr
Definition: misc.hh:591
gem5::X86ISA::MISCREG_MTRR_FIX_4K_F0000
@ MISCREG_MTRR_FIX_4K_F0000
Definition: misc.hh:199
gem5::X86ISA::VIPBit
@ VIPBit
Definition: misc.hh:82
gem5::X86ISA::bs
Bitfield< 14 > bs
Definition: misc.hh:657
gem5::X86ISA::MISCREG_IDTR_BASE
@ MISCREG_IDTR_BASE
Definition: misc.hh:330
gem5::X86ISA::MISCREG_DEF_TYPE
@ MISCREG_DEF_TYPE
Definition: misc.hh:204
gem5::X86ISA::MISCREG_HS_EFF_BASE
@ MISCREG_HS_EFF_BASE
Definition: misc.hh:342
gem5::X86ISA::ts
Bitfield< 3 > ts
Definition: misc.hh:607
gem5::X86ISA::MISCREG_PERF_EVT_SEL
static MiscRegIndex MISCREG_PERF_EVT_SEL(int index)
Definition: misc.hh:479
gem5::X86ISA::MISCREG_GS
@ MISCREG_GS
Definition: misc.hh:307
gem5::X86ISA::MISCREG_TSG_EFF_BASE
@ MISCREG_TSG_EFF_BASE
Definition: misc.hh:344
gem5::X86ISA::altAddr
Bitfield< 15, 14 > altAddr
Definition: misc.hh:592
gem5::X86ISA::lma
Bitfield< 10 > lma
Definition: misc.hh:789
gem5::X86ISA::MISCREG_PERF_EVT_CTR
static MiscRegIndex MISCREG_PERF_EVT_CTR(int index)
Definition: misc.hh:487
gem5::X86ISA::wp
Bitfield< 16 > wp
Definition: misc.hh:604
gem5::X86ISA::MISCREG_ES_ATTR
@ MISCREG_ES_ATTR
Definition: misc.hh:368
gem5::X86ISA::writable
Bitfield< 12 > writable
Definition: misc.hh:1000
gem5::X86ISA::MISCREG_CR3
@ MISCREG_CR3
Definition: misc.hh:114
gem5::X86ISA::BusyBit
@ BusyBit
Definition: misc.hh:103
gem5::X86ISA::tsd
Bitfield< 2 > tsd
Definition: misc.hh:642
gem5::X86ISA::fsgsbase
Bitfield< 16 > fsgsbase
Definition: misc.hh:631
gem5::X86ISA::VIFBit
@ VIFBit
Definition: misc.hh:81
gem5::X86ISA::b3
Bitfield< 3 > b3
Definition: misc.hh:655
gem5::X86ISA::MISCREG_DS_BASE
@ MISCREG_DS_BASE
Definition: misc.hh:321
gem5::X86ISA::uc
Bitfield< 61 > uc
Definition: misc.hh:773
gem5::X86ISA::MISCREG_IORR_MASK1
@ MISCREG_IORR_MASK1
Definition: misc.hh:286
gem5::X86ISA::CondFlagBit
CondFlagBit
Definition: misc.hh:57
gem5::X86ISA::MISCREG_SEG_BASE_BASE
@ MISCREG_SEG_BASE_BASE
Definition: misc.hh:317
gem5::X86ISA::en
Bitfield< 60 > en
Definition: misc.hh:772
gem5::X86ISA::DEBit
@ DEBit
Definition: misc.hh:90
gem5::X86ISA::OEBit
@ OEBit
Definition: misc.hh:92
gem5::X86ISA::MISCREG_MC4_ADDR
@ MISCREG_MC4_ADDR
Definition: misc.hh:233
gem5::X86ISA::readable
Bitfield< 13 > readable
Definition: misc.hh:1001
gem5::X86ISA::MISCREG_SF_MASK
@ MISCREG_SF_MASK
Definition: misc.hh:257
gem5::X86ISA::ge
Bitfield< 9 > ge
Definition: misc.hh:671
gem5::X86ISA::MISCREG_GS_ATTR
@ MISCREG_GS_ATTR
Definition: misc.hh:373
gem5::X86ISA::nxe
Bitfield< 11 > nxe
Definition: misc.hh:790
gem5::X86ISA::RFBit
@ RFBit
Definition: misc.hh:78
gem5::X86ISA::MISCREG_HS_BASE
@ MISCREG_HS_BASE
Definition: misc.hh:324
gem5::X86ISA::altOp
Bitfield< 11, 10 > altOp
Definition: misc.hh:590
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_5
@ MISCREG_MTRR_PHYS_BASE_5
Definition: misc.hh:174
gem5::X86ISA::de
Bitfield< 3 > de
Definition: misc.hh:641
gem5::X86ISA::MISCREG_CR2
@ MISCREG_CR2
Definition: misc.hh:113
gem5::X86ISA::MISCREG_CS_BASE
@ MISCREG_CS_BASE
Definition: misc.hh:319
gem5::X86ISA::MISCREG_MC4_STATUS
@ MISCREG_MC4_STATUS
Definition: misc.hh:222
gem5::X86ISA::MISCREG_PERF_EVT_CTR0
@ MISCREG_PERF_EVT_CTR0
Definition: misc.hh:271
gem5::X86ISA::CC3Bit
@ CC3Bit
Definition: misc.hh:102
gem5::X86ISA::em
Bitfield< 2 > em
Definition: misc.hh:608
gem5::X86ISA::MISCREG_LSTAR
@ MISCREG_LSTAR
Definition: misc.hh:254
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:998
gem5::X86ISA::pcd
Bitfield< 4 > pcd
Definition: pagetable.hh:147
gem5::X86ISA::targetESP
targetESP
Definition: misc.hh:698
gem5::X86ISA::r
Bitfield< 41 > r
Definition: misc.hh:940
gem5::X86ISA::c
Bitfield< 42 > c
Definition: misc.hh:939
gem5::X86ISA::rw1
Bitfield< 21, 20 > rw1
Definition: misc.hh:675
gem5::X86ISA::CFBit
@ CFBit
Definition: misc.hh:59
gem5::X86ISA::MISCREG_IDTR_LIMIT
@ MISCREG_IDTR_LIMIT
Definition: misc.hh:364
gem5::X86ISA::MISCREG_HS_LIMIT
@ MISCREG_HS_LIMIT
Definition: misc.hh:358
gem5::X86ISA::MISCREG_MC6_STATUS
@ MISCREG_MC6_STATUS
Definition: misc.hh:224
gem5::X86ISA::MISCREG_DR7
@ MISCREG_DR7
Definition: misc.hh:137
gem5::X86ISA::MISCREG_FOP
@ MISCREG_FOP
Definition: misc.hh:395
gem5::X86ISA::offsetHigh
offsetHigh
Definition: misc.hh:1007
gem5::X86ISA::MISCREG_ES_EFF_BASE
@ MISCREG_ES_EFF_BASE
Definition: misc.hh:336
gem5::X86ISA::MISCREG_FOSEG
@ MISCREG_FOSEG
Definition: misc.hh:393
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_0
@ MISCREG_MTRR_PHYS_MASK_0
Definition: misc.hh:180
gem5::X86ISA::MISCREG_MC2_STATUS
@ MISCREG_MC2_STATUS
Definition: misc.hh:220
gem5::X86ISA::len2
Bitfield< 27, 26 > len2
Definition: misc.hh:678
gem5::X86ISA::pae
Bitfield< 5 > pae
Definition: misc.hh:639
gem5::X86ISA::MISCREG_PERF_EVT_SEL_END
@ MISCREG_PERF_EVT_SEL_END
Definition: misc.hh:268
gem5::X86ISA::pb0
Bitfield< 2 > pb0
Definition: misc.hh:722
gem5::X86ISA::otherInfo
Bitfield< 56, 32 > otherInfo
Definition: misc.hh:768
gem5::X86ISA::stack
Bitfield< 17, 16 > stack
Definition: misc.hh:593
gem5::X86ISA::MISCREG_MS_LIMIT
@ MISCREG_MS_LIMIT
Definition: misc.hh:362
gem5::X86ISA::btf
Bitfield< 1 > btf
Definition: misc.hh:721
gem5::X86ISA::MISCREG_CR13
@ MISCREG_CR13
Definition: misc.hh:124
gem5::X86ISA::MISCREG_CR11
@ MISCREG_CR11
Definition: misc.hh:122
gem5::X86ISA::MISCREG_MC_ADDR_BASE
@ MISCREG_MC_ADDR_BASE
Definition: misc.hh:228
gem5::X86ISA::NumCRegs
const int NumCRegs
Definition: x86_traits.hh:56
gem5::X86ISA::enable
Bitfield< 11 > enable
Definition: misc.hh:1057
gem5::X86ISA::MISCREG_MTRR_FIX_4K_D0000
@ MISCREG_MTRR_FIX_4K_D0000
Definition: misc.hh:195
gem5::X86ISA::NUM_SEGMENTREGS
@ NUM_SEGMENTREGS
Definition: segment.hh:65
gem5::X86ISA::MISCREG_DR4
@ MISCREG_DR4
Definition: misc.hh:134
gem5::X86ISA::MISCREG_LS_BASE
@ MISCREG_LS_BASE
Definition: misc.hh:327
gem5::X86ISA::MISCREG_TOP_MEM
@ MISCREG_TOP_MEM
Definition: misc.hh:289
gem5::X86ISA::g
Bitfield< 8 > g
Definition: pagetable.hh:143
gem5::X86ISA::MISCREG_FS_EFF_BASE
@ MISCREG_FS_EFF_BASE
Definition: misc.hh:340
gem5::X86ISA::MISCREG_SS_EFF_BASE
@ MISCREG_SS_EFF_BASE
Definition: misc.hh:338
gem5::X86ISA::count
count
Definition: misc.hh:709
gem5::X86ISA::EZFBit
@ EZFBit
Definition: misc.hh:63
gem5::X86ISA::MISCREG_LAST_BRANCH_FROM_IP
@ MISCREG_LAST_BRANCH_FROM_IP
Definition: misc.hh:163
gem5::X86ISA::TFBit
@ TFBit
Definition: misc.hh:75
gem5::X86ISA::MISCREG_PERF_EVT_SEL_BASE
@ MISCREG_PERF_EVT_SEL_BASE
Definition: misc.hh:263
gem5::X86ISA::MISCREG_MC7_STATUS
@ MISCREG_MC7_STATUS
Definition: misc.hh:225
gem5::X86ISA::MISCREG_TOP_MEM2
@ MISCREG_TOP_MEM2
Definition: misc.hh:290
gem5::X86ISA::VMBit
@ VMBit
Definition: misc.hh:79
gem5::X86ISA::MISCREG_PAT
@ MISCREG_PAT
Definition: misc.hh:202
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_END
@ MISCREG_MTRR_PHYS_BASE_END
Definition: misc.hh:177
gem5::X86ISA::rsmCycle
Bitfield< 4 > rsmCycle
Definition: misc.hh:855
gem5::X86ISA::MISCREG_MC7_MISC
@ MISCREG_MC7_MISC
Definition: misc.hh:247
gem5::BitfieldType
Definition: bitunion.hh:118
segment.hh
gem5::X86ISA::mp
Bitfield< 1 > mp
Definition: misc.hh:609
gem5::X86ISA::disA20M
Bitfield< 2 > disA20M
Definition: misc.hh:843
bitunion.hh
gem5::X86ISA::type
type
Definition: misc.hh:733
gem5::X86ISA::StackFaultBit
@ StackFaultBit
Definition: misc.hh:97
gem5::X86ISA::vme
Bitfield< 0 > vme
Definition: misc.hh:644
gem5::X86ISA::MISCREG_IORR_BASE_END
@ MISCREG_IORR_BASE_END
Definition: misc.hh:282
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_6
@ MISCREG_MTRR_PHYS_BASE_6
Definition: misc.hh:175
gem5::X86ISA::MISCREG_TSC
@ MISCREG_TSC
Definition: misc.hh:149
gem5::X86ISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:106
gem5::X86ISA::MISCREG_IORR_MASK0
@ MISCREG_IORR_MASK0
Definition: misc.hh:285
gem5::X86ISA::MISCREG_SMM_CTL
@ MISCREG_SMM_CTL
Definition: misc.hh:294
gem5::X86ISA::submode
Bitfield< 3, 1 > submode
Definition: misc.hh:585
gem5::X86ISA::nt
Bitfield< 14 > nt
Definition: misc.hh:570
gem5::X86ISA::SegDescriptorLimit::getter
uint32_t getter(const uint64_t &storage) const
Definition: misc.hh:896
gem5::X86ISA::physAddr
physAddr
Definition: misc.hh:837
gem5::X86ISA::MISCREG_FTAG
@ MISCREG_FTAG
Definition: misc.hh:390
gem5::X86ISA::osfxsr
Bitfield< 9 > osfxsr
Definition: misc.hh:635
gem5::X86ISA::MISCREG_CR
static MiscRegIndex MISCREG_CR(int index)
Definition: misc.hh:417
gem5::X86ISA::MISCREG_KERNEL_GS_BASE
@ MISCREG_KERNEL_GS_BASE
Definition: misc.hh:259
gem5::X86ISA::MISCREG_LS_LIMIT
@ MISCREG_LS_LIMIT
Definition: misc.hh:361
gem5::X86ISA::mcaErrorCode
mcaErrorCode
Definition: misc.hh:766
gem5::X86ISA::MISCREG_DR0
@ MISCREG_DR0
Definition: misc.hh:130
gem5::X86ISA::BitUnion64
BitUnion64(VAddr) Bitfield< 20
gem5::X86ISA::MISCREG_PERF_EVT_SEL1
@ MISCREG_PERF_EVT_SEL1
Definition: misc.hh:265
gem5::X86ISA::MISCREG_CR4
@ MISCREG_CR4
Definition: misc.hh:115
gem5::X86ISA::MISCREG_LS_ATTR
@ MISCREG_LS_ATTR
Definition: misc.hh:377
gem5::X86ISA::addrv
Bitfield< 58 > addrv
Definition: misc.hh:770
gem5::X86ISA::MISCREG_MC2_MISC
@ MISCREG_MC2_MISC
Definition: misc.hh:242
gem5::X86ISA::MISCREG_PERF_EVT_SEL2
@ MISCREG_PERF_EVT_SEL2
Definition: misc.hh:266
gem5::X86ISA::MISCREG_PCI_CONFIG_ADDRESS
@ MISCREG_PCI_CONFIG_ADDRESS
Definition: misc.hh:402
gem5::X86ISA::bd
Bitfield< 13 > bd
Definition: misc.hh:656
gem5::MipsISA::wr
Bitfield< 3 > wr
Definition: pra_constants.hh:244
gem5::X86ISA::SubBitUnion
SubBitUnion(type, 43, 40) Bitfield< 43 > codeOrData
gem5::X86ISA::MISCREG_CS_ATTR
@ MISCREG_CS_ATTR
Definition: misc.hh:369
gem5::X86ISA::MISCREG_IDTR_ATTR
@ MISCREG_IDTR_ATTR
Definition: misc.hh:380
gem5::X86ISA::miscv
Bitfield< 59 > miscv
Definition: misc.hh:771
gem5::X86ISA::MISCREG_EFER
@ MISCREG_EFER
Definition: misc.hh:251
gem5::X86ISA::MISCREG_SEG_LIMIT_BASE
@ MISCREG_SEG_LIMIT_BASE
Definition: misc.hh:351
gem5::X86ISA::MISCREG_MC_STATUS
static MiscRegIndex MISCREG_MC_STATUS(int index)
Definition: misc.hh:455
gem5::X86ISA::ECFBit
@ ECFBit
Definition: misc.hh:61
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::X86ISA::MISCREG_LAST_BRANCH_TO_IP
@ MISCREG_LAST_BRANCH_TO_IP
Definition: misc.hh:164
gem5::X86ISA::MISCREG_SEG_BASE
static MiscRegIndex MISCREG_SEG_BASE(int index)
Definition: misc.hh:518
gem5::X86ISA::MISCREG_CS_LIMIT
@ MISCREG_CS_LIMIT
Definition: misc.hh:353
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_2
@ MISCREG_MTRR_PHYS_MASK_2
Definition: misc.hh:182
gem5::X86ISA::MISCREG_RFLAGS
@ MISCREG_RFLAGS
Definition: misc.hh:140
gem5::X86ISA::MISCREG_MTRR_FIX_4K_C8000
@ MISCREG_MTRR_FIX_4K_C8000
Definition: misc.hh:194
gem5::X86ISA::gd
Bitfield< 13 > gd
Definition: misc.hh:672
gem5::X86ISA::MISCREG_FS
@ MISCREG_FS
Definition: misc.hh:306
gem5::X86ISA::ti
Bitfield< 2 > ti
Definition: misc.hh:867
gem5::X86ISA::MISCREG_TSL_ATTR
@ MISCREG_TSL_ATTR
Definition: misc.hh:375
gem5::X86ISA::MISCREG_MC3_ADDR
@ MISCREG_MC3_ADDR
Definition: misc.hh:232
gem5::X86ISA::pf
Bitfield< 2 > pf
Definition: misc.hh:556
gem5::X86ISA::MISCREG_CR10
@ MISCREG_CR10
Definition: misc.hh:121
gem5::X86ISA::b1
Bitfield< 1 > b1
Definition: misc.hh:653
gem5::X86ISA::MISCREG_IDTR
@ MISCREG_IDTR
Definition: misc.hh:314
gem5::X86ISA::MISCREG_CR15
@ MISCREG_CR15
Definition: misc.hh:126
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_3
@ MISCREG_MTRR_PHYS_BASE_3
Definition: misc.hh:172
gem5::X86ISA::ffxsr
Bitfield< 14 > ffxsr
Definition: misc.hh:792
gem5::X86ISA::bsp
Bitfield< 8 > bsp
Definition: misc.hh:1058
gem5::X86ISA::paePdtb
Bitfield< 31, 5 > paePdtb
Definition: misc.hh:623
gem5::X86ISA::MISCREG_MC4_MISC
@ MISCREG_MC4_MISC
Definition: misc.hh:244
gem5::X86ISA::MISCREG_TSL_BASE
@ MISCREG_TSL_BASE
Definition: misc.hh:325
gem5::X86ISA::usr
Bitfield< 16 > usr
Definition: misc.hh:808
gem5::X86ISA::esi
esi
Definition: misc.hh:865
gem5::X86ISA::rw2
Bitfield< 25, 24 > rw2
Definition: misc.hh:677
gem5::X86ISA::af
Bitfield< 4 > af
Definition: misc.hh:554
gem5::X86ISA::MISCREG_DR6
@ MISCREG_DR6
Definition: misc.hh:136
gem5::X86ISA::dpl
Bitfield< 46, 45 > dpl
Definition: misc.hh:932
gem5::X86ISA::w
Bitfield< 1 > w
Definition: pagetable.hh:150
gem5::X86ISA::MISCREG_SS
@ MISCREG_SS
Definition: misc.hh:304
gem5::X86ISA::MISCREG_MXCSR
@ MISCREG_MXCSR
Definition: misc.hh:386
gem5::X86ISA::si
Bitfield< 15, 3 > si
Definition: misc.hh:866
gem5::X86ISA::MISCREG_SYSENTER_CS
@ MISCREG_SYSENTER_CS
Definition: misc.hh:153
gem5::X86ISA::MISCREG_MC1_STATUS
@ MISCREG_MC1_STATUS
Definition: misc.hh:219
gem5::X86ISA::MISCREG_SEG_ATTR_BASE
@ MISCREG_SEG_ATTR_BASE
Definition: misc.hh:367
gem5::X86ISA::ac
Bitfield< 18 > ac
Definition: misc.hh:567
gem5::X86ISA::MISCREG_MC4_CTL
@ MISCREG_MC4_CTL
Definition: misc.hh:211
gem5::ArmISA::MiscRegIndex
MiscRegIndex
Definition: misc.hh:59
gem5::X86ISA::OFBit
@ OFBit
Definition: misc.hh:67
gem5::X86ISA::MISCREG_SEG_EFF_BASE_BASE
@ MISCREG_SEG_EFF_BASE_BASE
Definition: misc.hh:335
gem5::X86ISA::longPdtb
longPdtb
Definition: misc.hh:619
gem5::X86ISA::baseLow
Bitfield< 39, 16 > baseLow
Definition: misc.hh:921
gem5::X86ISA::expandDown
Bitfield< 14 > expandDown
Definition: misc.hh:1002
gem5::X86ISA::exit
Bitfield< 3 > exit
Definition: misc.hh:854
gem5::X86ISA::RFLAGBit
RFLAGBit
Definition: misc.hh:73
gem5::X86ISA::MISCREG_TSG_ATTR
@ MISCREG_TSG_ATTR
Definition: misc.hh:376
gem5::X86ISA::NTBit
@ NTBit
Definition: misc.hh:77
gem5::X86ISA::enter
Bitfield< 1 > enter
Definition: misc.hh:852
gem5::X86ISA::MISCREG_CR14
@ MISCREG_CR14
Definition: misc.hh:125
gem5::X86ISA::intEn
Bitfield< 20 > intEn
Definition: misc.hh:812
gem5::X86ISA::MISCREG_MC6_MISC
@ MISCREG_MC6_MISC
Definition: misc.hh:246
gem5::X86ISA::MISCREG_FS_ATTR
@ MISCREG_FS_ATTR
Definition: misc.hh:372
gem5::X86ISA::physbase
Bitfield< 51, 12 > physbase
Definition: misc.hh:734
gem5::X86ISA::vif
Bitfield< 19 > vif
Definition: misc.hh:566
gem5::X86ISA::BitUnion32
BitUnion32(TriggerIntMessage) Bitfield< 7
gem5::X86ISA::MISCREG_FCW
@ MISCREG_FCW
Definition: misc.hh:387
gem5::X86ISA::MISCREG_TSG
@ MISCREG_TSG
Definition: misc.hh:310
gem5::X86ISA::MISCREG_CS
@ MISCREG_CS
Definition: misc.hh:303
gem5::X86ISA::MISCREG_MC5_CTL
@ MISCREG_MC5_CTL
Definition: misc.hh:212
gem5::X86ISA::MISCREG_CS_EFF_BASE
@ MISCREG_CS_EFF_BASE
Definition: misc.hh:337
gem5::X86ISA::legacy
legacy
Definition: misc.hh:615
gem5::X86ISA::MISCREG_CR9
@ MISCREG_CR9
Definition: misc.hh:120
gem5::X86ISA::MISCREG_MS_ATTR
@ MISCREG_MS_ATTR
Definition: misc.hh:378
gem5::X86ISA::MISCREG_TSG_BASE
@ MISCREG_TSG_BASE
Definition: misc.hh:326
gem5::X86ISA::lme
Bitfield< 8 > lme
Definition: misc.hh:788
gem5::X86ISA::eventMask
eventMask
Definition: misc.hh:806
gem5::X86ISA::tf
Bitfield< 8 > tf
Definition: misc.hh:575
gem5::X86ISA::MISCREG_TR_LIMIT
@ MISCREG_TR_LIMIT
Definition: misc.hh:363
gem5::X86ISA::MISCREG_MC3_STATUS
@ MISCREG_MC3_STATUS
Definition: misc.hh:221
gem5::QARMA::b0
Bitfield< 3, 0 > b0
Definition: qarma.hh:66
gem5::X86ISA::MISCREG_IORR_BASE
static MiscRegIndex MISCREG_IORR_BASE(int index)
Definition: misc.hh:495
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::X86ISA::sysretCsAndSs
Bitfield< 63, 48 > sysretCsAndSs
Definition: misc.hh:798
gem5::X86ISA::MISCREG_SS_ATTR
@ MISCREG_SS_ATTR
Definition: misc.hh:370
gem5::X86ISA::MISCREG_MTRR_FIX_16K_A0000
@ MISCREG_MTRR_FIX_16K_A0000
Definition: misc.hh:192
gem5::X86ISA::rpl
Bitfield< 1, 0 > rpl
Definition: misc.hh:868
gem5::X86ISA::vm
Bitfield< 17 > vm
Definition: misc.hh:568
gem5::X86ISA::MISCREG_CR12
@ MISCREG_CR12
Definition: misc.hh:123
gem5::X86ISA::MISCREG_MC1_MISC
@ MISCREG_MC1_MISC
Definition: misc.hh:241
gem5::X86ISA::unusable
Bitfield< 2 > unusable
Definition: misc.hh:993
gem5::X86ISA::eipv
Bitfield< 1 > eipv
Definition: misc.hh:715
gem5::X86ISA::MISCREG_HS_ATTR
@ MISCREG_HS_ATTR
Definition: misc.hh:374
gem5::X86ISA::MISCREG_MC_MISC
static MiscRegIndex MISCREG_MC_MISC(int index)
Definition: misc.hh:471
gem5::X86ISA::avl
Bitfield< 11, 9 > avl
Definition: pagetable.hh:142
gem5::X86ISA::granularity
Bitfield< 6 > granularity
Definition: misc.hh:997
gem5::X86ISA::MISCREG_MCG_CTL
@ MISCREG_MCG_CTL
Definition: misc.hh:159
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:809
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_0
@ MISCREG_MTRR_PHYS_BASE_0
Definition: misc.hh:169
gem5::X86ISA::over
Bitfield< 62 > over
Definition: misc.hh:774
gem5::X86ISA::MISCREG_GS_BASE
@ MISCREG_GS_BASE
Definition: misc.hh:323
gem5::X86ISA::MISCREG_SEG_EFF_BASE
static MiscRegIndex MISCREG_SEG_EFF_BASE(int index)
Definition: misc.hh:525
gem5::X86ISA::selector
Bitfield< 31, 16 > selector
Definition: misc.hh:1009
gem5::X86ISA::inv
Bitfield< 23 > inv
Definition: misc.hh:814
gem5::X86ISA::am
Bitfield< 18 > am
Definition: misc.hh:603
gem5::X86ISA::targetEip
targetEip
Definition: misc.hh:796
gem5::X86ISA::rd
Bitfield< 4 > rd
Definition: misc.hh:827
gem5::X86ISA::MISCREG_MC5_STATUS
@ MISCREG_MC5_STATUS
Definition: misc.hh:223
gem5::X86ISA::ezf
Bitfield< 5 > ezf
Definition: misc.hh:553
gem5::X86ISA::MISCREG_CR0
@ MISCREG_CR0
Definition: misc.hh:111
gem5::X86ISA::MISCREG_IORR_BASE_BASE
@ MISCREG_IORR_BASE_BASE
Definition: misc.hh:279
gem5::X86ISA::MISCREG_SYSCFG
@ MISCREG_SYSCFG
Definition: misc.hh:277
gem5::X86ISA::AFBit
@ AFBit
Definition: misc.hh:62
gem5::X86ISA::pce
Bitfield< 8 > pce
Definition: misc.hh:636
gem5::X86ISA::MISCREG_FSW
@ MISCREG_FSW
Definition: misc.hh:388
gem5::X86ISA::l1
Bitfield< 2 > l1
Definition: misc.hh:664
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_BASE
@ MISCREG_MTRR_PHYS_BASE_BASE
Definition: misc.hh:168
gem5::X86ISA::et
Bitfield< 4 > et
Definition: misc.hh:606
logging.hh
gem5::X86ISA::d
Bitfield< 6 > d
Definition: pagetable.hh:145
gem5::X86ISA::MISCREG_VM_CR
@ MISCREG_VM_CR
Definition: misc.hh:292
gem5::X86ISA::MISCREG_MC0_STATUS
@ MISCREG_MC0_STATUS
Definition: misc.hh:218
gem5::X86ISA::pe
Bitfield< 0 > pe
Definition: misc.hh:610
gem5::X86ISA::cd
Bitfield< 30 > cd
Definition: misc.hh:601
gem5::X86ISA::MISCREG_LAST_EXCEPTION_FROM_IP
@ MISCREG_LAST_EXCEPTION_FROM_IP
Definition: misc.hh:165
gem5::X86ISA::PFBit
@ PFBit
Definition: misc.hh:60
gem5::X86ISA::MISCREG_IGNNE
@ MISCREG_IGNNE
Definition: misc.hh:293
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::X86ISA::MISCREG_MC_STATUS_END
@ MISCREG_MC_STATUS_END
Definition: misc.hh:226
gem5::X86ISA::MISCREG_GS_EFF_BASE
@ MISCREG_GS_EFF_BASE
Definition: misc.hh:341
gem5::X86ISA::MISCREG_TR_ATTR
@ MISCREG_TR_ATTR
Definition: misc.hh:379
gem5::X86ISA::IFBit
@ IFBit
Definition: misc.hh:76
gem5::X86ISA::MISCREG_DS_LIMIT
@ MISCREG_DS_LIMIT
Definition: misc.hh:355
gem5::X86ISA::MISCREG_SEG_SEL_BASE
@ MISCREG_SEG_SEL_BASE
Definition: misc.hh:301
gem5::X86ISA::MISCREG_MC_MISC_END
@ MISCREG_MC_MISC_END
Definition: misc.hh:248
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_5
@ MISCREG_MTRR_PHYS_MASK_5
Definition: misc.hh:185
gem5::X86ISA::MISCREG_PERF_EVT_SEL3
@ MISCREG_PERF_EVT_SEL3
Definition: misc.hh:267
gem5::X86ISA::MISCREG_MC_ADDR_END
@ MISCREG_MC_ADDR_END
Definition: misc.hh:237
gem5::X86ISA::fix
Bitfield< 8 > fix
Definition: misc.hh:686
gem5::X86ISA::MISCREG_FTW
@ MISCREG_FTW
Definition: misc.hh:389
gem5::X86ISA::MISCREG_SYSENTER_EIP
@ MISCREG_SYSENTER_EIP
Definition: misc.hh:155
gem5::X86ISA::cfofMask
const uint32_t cfofMask
Definition: misc.hh:70
gem5::X86ISA::pse
Bitfield< 4 > pse
Definition: misc.hh:640
gem5::X86ISA::nw
Bitfield< 29 > nw
Definition: misc.hh:602
gem5::X86ISA::MISCREG_IDTR_EFF_BASE
@ MISCREG_IDTR_EFF_BASE
Definition: misc.hh:348
gem5::X86ISA::syscallCsAndSs
Bitfield< 47, 32 > syscallCsAndSs
Definition: misc.hh:797
gem5::X86ISA::MISCREG_DR
static MiscRegIndex MISCREG_DR(int index)
Definition: misc.hh:424
gem5::X86ISA::physmask
Bitfield< 51, 12 > physmask
Definition: misc.hh:739
gem5::X86ISA::MISCREG_PERF_EVT_CTR_END
@ MISCREG_PERF_EVT_CTR_END
Definition: misc.hh:275
gem5::X86ISA::MISCREG_FS_LIMIT
@ MISCREG_FS_LIMIT
Definition: misc.hh:356
gem5::X86ISA::MISCREG_LS
@ MISCREG_LS
Definition: misc.hh:311
gem5::X86ISA::MISCREG_HS
@ MISCREG_HS
Definition: misc.hh:308
gem5::X86ISA::MISCREG_TSL_EFF_BASE
@ MISCREG_TSL_EFF_BASE
Definition: misc.hh:343
gem5::X86ISA::limitLow
Bitfield< 15, 0 > limitLow
Definition: misc.hh:929
gem5::X86ISA::svme
Bitfield< 12 > svme
Definition: misc.hh:791
gem5::X86ISA::MISCREG_IORR_BASE1
@ MISCREG_IORR_BASE1
Definition: misc.hh:281
gem5::X86ISA::counterMask
Bitfield< 31, 24 > counterMask
Definition: misc.hh:815
gem5::X86ISA::pdtb
Bitfield< 31, 12 > pdtb
Definition: misc.hh:621
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::X86ISA::pwt
Bitfield< 3 > pwt
Definition: pagetable.hh:148
gem5::X86ISA::MISCREG_MC7_CTL
@ MISCREG_MC7_CTL
Definition: misc.hh:214
gem5::X86ISA::MISCREG_TSC_AUX
@ MISCREG_TSC_AUX
Definition: misc.hh:261
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_1
@ MISCREG_MTRR_PHYS_MASK_1
Definition: misc.hh:181
gem5::X86ISA::modelSpecificCode
Bitfield< 31, 16 > modelSpecificCode
Definition: misc.hh:767
gem5::X86ISA::MISCREG_MC3_CTL
@ MISCREG_MC3_CTL
Definition: misc.hh:210
gem5::X86ISA::sf
Bitfield< 7 > sf
Definition: misc.hh:551
gem5::X86ISA::CC1Bit
@ CC1Bit
Definition: misc.hh:100
gem5::X86ISA::offsetLow
Bitfield< 15, 0 > offsetLow
Definition: misc.hh:1008
gem5::X86ISA::mfdm
Bitfield< 19 > mfdm
Definition: misc.hh:820
gem5::X86ISA::g1
Bitfield< 3 > g1
Definition: misc.hh:665
gem5::X86ISA::l2
Bitfield< 4 > l2
Definition: misc.hh:666
gem5::X86ISA::MISCREG_TSL_LIMIT
@ MISCREG_TSL_LIMIT
Definition: misc.hh:359
gem5::X86ISA::s
Bitfield< 44 > s
Definition: misc.hh:933
gem5::X86ISA::MISCREG_DS_ATTR
@ MISCREG_DS_ATTR
Definition: misc.hh:371
gem5::X86ISA::X87StatusBit
X87StatusBit
Definition: misc.hh:86
gem5::X86ISA::MISCREG_MC1_CTL
@ MISCREG_MC1_CTL
Definition: misc.hh:208
gem5::X86ISA::MISCREG_MTRR_FIX_16K_80000
@ MISCREG_MTRR_FIX_16K_80000
Definition: misc.hh:191
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::MISCREG_MC_CTL_END
@ MISCREG_MC_CTL_END
Definition: misc.hh:215
gem5::X86ISA::targetCS
targetCS
Definition: misc.hh:694
gem5::X86ISA::MISCREG_MTRR_FIX_64K_00000
@ MISCREG_MTRR_FIX_64K_00000
Definition: misc.hh:190
gem5::X86ISA::g0
Bitfield< 1 > g0
Definition: misc.hh:663
gem5::X86ISA::ecf
Bitfield< 3 > ecf
Definition: misc.hh:555
gem5::X86ISA::MISCREG_CSTAR
@ MISCREG_CSTAR
Definition: misc.hh:255
gem5::X86ISA::MISCREG_DR5
@ MISCREG_DR5
Definition: misc.hh:135
gem5::X86ISA::cf
Bitfield< 0 > cf
Definition: misc.hh:557
gem5::X86ISA::unitMask
Bitfield< 15, 8 > unitMask
Definition: misc.hh:807
gem5::X86ISA::prot
Bitfield< 7 > prot
Definition: misc.hh:588
gem5::X86ISA::a
Bitfield< 5 > a
Definition: pagetable.hh:146
gem5::X86ISA::vip
Bitfield< 20 > vip
Definition: misc.hh:565
gem5::X86ISA::cpl
Bitfield< 5, 4 > cpl
Definition: misc.hh:586
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE
static MiscRegIndex MISCREG_MTRR_PHYS_BASE(int index)
Definition: misc.hh:431
gem5::X86ISA::EndSubBitUnion
EndSubBitUnion(type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
TSS Descriptor (long mode - 128 bits) the lower 64 bits.
gem5::X86ISA::limitHigh
Bitfield< 51, 48 > limitHigh
Definition: misc.hh:928
gem5::X86ISA::MISCREG_MTRR_PHYS_MASK_6
@ MISCREG_MTRR_PHYS_MASK_6
Definition: misc.hh:186
gem5::X86ISA::PEBit
@ PEBit
Definition: misc.hh:94
gem5::ArmISA::mode
Bitfield< 4, 0 > mode
Definition: misc_types.hh:73
gem5::X86ISA::MISCREG_MS_BASE
@ MISCREG_MS_BASE
Definition: misc.hh:328
gem5::X86ISA::ccFlagMask
const uint32_t ccFlagMask
Definition: misc.hh:71
gem5::X86ISA::MISCREG_PERF_EVT_CTR3
@ MISCREG_PERF_EVT_CTR3
Definition: misc.hh:274
gem5::X86ISA::MISCREG_MTRR_PHYS_BASE_4
@ MISCREG_MTRR_PHYS_BASE_4
Definition: misc.hh:173

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