gem5  v22.0.0.2
Enumerations | Functions
gem5::X86ISA::misc_reg Namespace Reference

Enumerations

enum  : RegIndex {
  CrBase, Cr0 = CrBase, Cr1, Cr2,
  Cr3, Cr4, Cr5, Cr6,
  Cr7, Cr8, Cr9, Cr10,
  Cr11, Cr12, Cr13, Cr14,
  Cr15, DrBase = CrBase + NumCRegs, Dr0 = DrBase, Dr1,
  Dr2, Dr3, Dr4, Dr5,
  Dr6, Dr7, Rflags = DrBase + NumDRegs, M5Reg,
  Tsc, Mtrrcap, SysenterCs, SysenterEsp,
  SysenterEip, McgCap, McgStatus, McgCtl,
  DebugCtlMsr, LastBranchFromIp, LastBranchToIp, LastExceptionFromIp,
  LastExceptionToIp, MtrrPhysBaseBase, MtrrPhysBase0 = MtrrPhysBaseBase, MtrrPhysBase1,
  MtrrPhysBase2, MtrrPhysBase3, MtrrPhysBase4, MtrrPhysBase5,
  MtrrPhysBase6, MtrrPhysBase7, MtrrPhysBaseEnd, MtrrPhysMaskBase = MtrrPhysBaseEnd,
  MtrrPhysMask0 = MtrrPhysMaskBase, MtrrPhysMask1, MtrrPhysMask2, MtrrPhysMask3,
  MtrrPhysMask4, MtrrPhysMask5, MtrrPhysMask6, MtrrPhysMask7,
  MtrrPhysMaskEnd, MtrrFix64k00000 = MtrrPhysMaskEnd, MtrrFix16k80000, MtrrFix16kA0000,
  MtrrFix4kC0000, MtrrFix4kC8000, MtrrFix4kD0000, MtrrFix4kD8000,
  MtrrFix4kE0000, MtrrFix4kE8000, MtrrFix4kF0000, MtrrFix4kF8000,
  Pat, DefType, McCtlBase, Mc0Ctl = McCtlBase,
  Mc1Ctl, Mc2Ctl, Mc3Ctl, Mc4Ctl,
  Mc5Ctl, Mc6Ctl, Mc7Ctl, McCtlEnd,
  McStatusBase = McCtlEnd, Mc0Status = McStatusBase, Mc1Status, Mc2Status,
  Mc3Status, Mc4Status, Mc5Status, Mc6Status,
  Mc7Status, McStatusEnd, McAddrBase = McStatusEnd, Mc0Addr = McAddrBase,
  Mc1Addr, Mc2Addr, Mc3Addr, Mc4Addr,
  Mc5Addr, Mc6Addr, Mc7Addr, McAddrEnd,
  McMiscBase = McAddrEnd, Mc0Misc = McMiscBase, Mc1Misc, Mc2Misc,
  Mc3Misc, Mc4Misc, Mc5Misc, Mc6Misc,
  Mc7Misc, McMiscEnd, Efer = McMiscEnd, Star,
  Lstar, Cstar, SfMask, KernelGsBase,
  TscAux, PerfEvtSelBase, PerfEvtSel0 = PerfEvtSelBase, PerfEvtSel1,
  PerfEvtSel2, PerfEvtSel3, PerfEvtSelEnd, PerfEvtCtrBase = PerfEvtSelEnd,
  PerfEvtCtr0 = PerfEvtCtrBase, PerfEvtCtr1, PerfEvtCtr2, PerfEvtCtr3,
  PerfEvtCtrEnd, Syscfg = PerfEvtCtrEnd, IorrBaseBase, IorrBase0 = IorrBaseBase,
  IorrBase1, IorrBaseEnd, IorrMaskBase = IorrBaseEnd, IorrMask0 = IorrMaskBase,
  IorrMask1, IorrMaskEnd, TopMem = IorrMaskEnd, TopMem2,
  VmCr, Ignne, SmmCtl, VmHsavePa,
  SegSelBase, Es = SegSelBase, Cs, Ss,
  Ds, Fs, Gs, Hs,
  Tsl, Tsg, Ls, Ms,
  Tr, Idtr, SegBaseBase = SegSelBase + segment_idx::NumIdxs, EsBase = SegBaseBase,
  CsBase, SsBase, DsBase, FsBase,
  GsBase, HsBase, TslBase, TsgBase,
  LsBase, MsBase, TrBase, IdtrBase,
  SegEffBaseBase = SegBaseBase + segment_idx::NumIdxs, EsEffBase = SegEffBaseBase, CsEffBase, SsEffBase,
  DsEffBase, FsEffBase, GsEffBase, HsEffBase,
  TslEffBase, TsgEffBase, LsEffBase, MsEffBase,
  TrEffBase, IdtrEffBase, SegLimitBase = SegEffBaseBase + segment_idx::NumIdxs, EsLimit = SegLimitBase,
  CsLimit, SsLimit, DsLimit, FsLimit,
  GsLimit, HsLimit, TslLimit, TsgLimit,
  LsLimit, MsLimit, TrLimit, IdtrLimit,
  SegAttrBase = SegLimitBase + segment_idx::NumIdxs, EsAttr = SegAttrBase, CsAttr, SsAttr,
  DsAttr, FsAttr, GsAttr, HsAttr,
  TslAttr, TsgAttr, LsAttr, MsAttr,
  TrAttr, IdtrAttr, X87Top = SegAttrBase + segment_idx::NumIdxs, Mxcsr,
  Fcw, Fsw, Ftw, Ftag,
  Fiseg, Fioff, Foseg, Fooff,
  Fop, ApicBase, PciConfigAddress, NumRegs
}
 

Functions

static bool isValid (int index)
 
static RegIndex cr (int index)
 
static RegIndex dr (int index)
 
static RegIndex mtrrPhysBase (int index)
 
static RegIndex mtrrPhysMask (int index)
 
static RegIndex mcCtl (int index)
 
static RegIndex mcStatus (int index)
 
static RegIndex mcAddr (int index)
 
static RegIndex mcMisc (int index)
 
static RegIndex perfEvtSel (int index)
 
static RegIndex perfEvtCtr (int index)
 
static RegIndex iorrBase (int index)
 
static RegIndex iorrMask (int index)
 
static RegIndex segSel (int index)
 
static RegIndex segBase (int index)
 
static RegIndex segEffBase (int index)
 
static RegIndex segLimit (int index)
 
static RegIndex segAttr (int index)
 

Enumeration Type Documentation

◆ anonymous enum

anonymous enum : RegIndex
Enumerator
CrBase 
Cr0 
Cr1 
Cr2 
Cr3 
Cr4 
Cr5 
Cr6 
Cr7 
Cr8 
Cr9 
Cr10 
Cr11 
Cr12 
Cr13 
Cr14 
Cr15 
DrBase 
Dr0 
Dr1 
Dr2 
Dr3 
Dr4 
Dr5 
Dr6 
Dr7 
Rflags 
M5Reg 
Tsc 
Mtrrcap 
SysenterCs 
SysenterEsp 
SysenterEip 
McgCap 
McgStatus 
McgCtl 
DebugCtlMsr 
LastBranchFromIp 
LastBranchToIp 
LastExceptionFromIp 
LastExceptionToIp 
MtrrPhysBaseBase 
MtrrPhysBase0 
MtrrPhysBase1 
MtrrPhysBase2 
MtrrPhysBase3 
MtrrPhysBase4 
MtrrPhysBase5 
MtrrPhysBase6 
MtrrPhysBase7 
MtrrPhysBaseEnd 
MtrrPhysMaskBase 
MtrrPhysMask0 
MtrrPhysMask1 
MtrrPhysMask2 
MtrrPhysMask3 
MtrrPhysMask4 
MtrrPhysMask5 
MtrrPhysMask6 
MtrrPhysMask7 
MtrrPhysMaskEnd 
MtrrFix64k00000 
MtrrFix16k80000 
MtrrFix16kA0000 
MtrrFix4kC0000 
MtrrFix4kC8000 
MtrrFix4kD0000 
MtrrFix4kD8000 
MtrrFix4kE0000 
MtrrFix4kE8000 
MtrrFix4kF0000 
MtrrFix4kF8000 
Pat 
DefType 
McCtlBase 
Mc0Ctl 
Mc1Ctl 
Mc2Ctl 
Mc3Ctl 
Mc4Ctl 
Mc5Ctl 
Mc6Ctl 
Mc7Ctl 
McCtlEnd 
McStatusBase 
Mc0Status 
Mc1Status 
Mc2Status 
Mc3Status 
Mc4Status 
Mc5Status 
Mc6Status 
Mc7Status 
McStatusEnd 
McAddrBase 
Mc0Addr 
Mc1Addr 
Mc2Addr 
Mc3Addr 
Mc4Addr 
Mc5Addr 
Mc6Addr 
Mc7Addr 
McAddrEnd 
McMiscBase 
Mc0Misc 
Mc1Misc 
Mc2Misc 
Mc3Misc 
Mc4Misc 
Mc5Misc 
Mc6Misc 
Mc7Misc 
McMiscEnd 
Efer 
Star 
Lstar 
Cstar 
SfMask 
KernelGsBase 
TscAux 
PerfEvtSelBase 
PerfEvtSel0 
PerfEvtSel1 
PerfEvtSel2 
PerfEvtSel3 
PerfEvtSelEnd 
PerfEvtCtrBase 
PerfEvtCtr0 
PerfEvtCtr1 
PerfEvtCtr2 
PerfEvtCtr3 
PerfEvtCtrEnd 
Syscfg 
IorrBaseBase 
IorrBase0 
IorrBase1 
IorrBaseEnd 
IorrMaskBase 
IorrMask0 
IorrMask1 
IorrMaskEnd 
TopMem 
TopMem2 
VmCr 
Ignne 
SmmCtl 
VmHsavePa 
SegSelBase 
Es 
Cs 
Ss 
Ds 
Fs 
Gs 
Hs 
Tsl 
Tsg 
Ls 
Ms 
Tr 
Idtr 
SegBaseBase 
EsBase 
CsBase 
SsBase 
DsBase 
FsBase 
GsBase 
HsBase 
TslBase 
TsgBase 
LsBase 
MsBase 
TrBase 
IdtrBase 
SegEffBaseBase 
EsEffBase 
CsEffBase 
SsEffBase 
DsEffBase 
FsEffBase 
GsEffBase 
HsEffBase 
TslEffBase 
TsgEffBase 
LsEffBase 
MsEffBase 
TrEffBase 
IdtrEffBase 
SegLimitBase 
EsLimit 
CsLimit 
SsLimit 
DsLimit 
FsLimit 
GsLimit 
HsLimit 
TslLimit 
TsgLimit 
LsLimit 
MsLimit 
TrLimit 
IdtrLimit 
SegAttrBase 
EsAttr 
CsAttr 
SsAttr 
DsAttr 
FsAttr 
GsAttr 
HsAttr 
TslAttr 
TsgAttr 
LsAttr 
MsAttr 
TrAttr 
IdtrAttr 
X87Top 
Mxcsr 
Fcw 
Fsw 
Ftw 
Ftag 
Fiseg 
Fioff 
Foseg 
Fooff 
Fop 
ApicBase 
PciConfigAddress 
NumRegs 

Definition at line 109 of file misc.hh.

Function Documentation

◆ cr()

static RegIndex gem5::X86ISA::misc_reg::cr ( int  index)
inlinestatic

◆ dr()

static RegIndex gem5::X86ISA::misc_reg::dr ( int  index)
inlinestatic

Definition at line 426 of file misc.hh.

References DrBase, gem5::X86ISA::index, and gem5::X86ISA::NumDRegs.

◆ iorrBase()

static RegIndex gem5::X86ISA::misc_reg::iorrBase ( int  index)
inlinestatic

Definition at line 489 of file misc.hh.

References gem5::X86ISA::index, IorrBaseBase, and IorrBaseEnd.

◆ iorrMask()

static RegIndex gem5::X86ISA::misc_reg::iorrMask ( int  index)
inlinestatic

Definition at line 496 of file misc.hh.

References gem5::X86ISA::index, IorrMaskBase, and IorrMaskEnd.

◆ isValid()

static bool gem5::X86ISA::misc_reg::isValid ( int  index)
inlinestatic

◆ mcAddr()

static RegIndex gem5::X86ISA::misc_reg::mcAddr ( int  index)
inlinestatic

Definition at line 461 of file misc.hh.

References gem5::X86ISA::index, McAddrBase, and McAddrEnd.

◆ mcCtl()

static RegIndex gem5::X86ISA::misc_reg::mcCtl ( int  index)
inlinestatic

Definition at line 447 of file misc.hh.

References gem5::X86ISA::index, McCtlBase, and McCtlEnd.

◆ mcMisc()

static RegIndex gem5::X86ISA::misc_reg::mcMisc ( int  index)
inlinestatic

Definition at line 468 of file misc.hh.

References gem5::X86ISA::index, McMiscBase, and McMiscEnd.

◆ mcStatus()

static RegIndex gem5::X86ISA::misc_reg::mcStatus ( int  index)
inlinestatic

Definition at line 454 of file misc.hh.

References gem5::X86ISA::index, McStatusBase, and McStatusEnd.

◆ mtrrPhysBase()

static RegIndex gem5::X86ISA::misc_reg::mtrrPhysBase ( int  index)
inlinestatic

Definition at line 433 of file misc.hh.

References gem5::X86ISA::index, MtrrPhysBaseBase, and MtrrPhysBaseEnd.

◆ mtrrPhysMask()

static RegIndex gem5::X86ISA::misc_reg::mtrrPhysMask ( int  index)
inlinestatic

Definition at line 440 of file misc.hh.

References gem5::X86ISA::index, MtrrPhysMaskBase, and MtrrPhysMaskEnd.

◆ perfEvtCtr()

static RegIndex gem5::X86ISA::misc_reg::perfEvtCtr ( int  index)
inlinestatic

Definition at line 482 of file misc.hh.

References gem5::X86ISA::index, PerfEvtCtrBase, and PerfEvtCtrEnd.

◆ perfEvtSel()

static RegIndex gem5::X86ISA::misc_reg::perfEvtSel ( int  index)
inlinestatic

Definition at line 475 of file misc.hh.

References gem5::X86ISA::index, PerfEvtSelBase, and PerfEvtSelEnd.

◆ segAttr()

static RegIndex gem5::X86ISA::misc_reg::segAttr ( int  index)
inlinestatic

◆ segBase()

static RegIndex gem5::X86ISA::misc_reg::segBase ( int  index)
inlinestatic

◆ segEffBase()

static RegIndex gem5::X86ISA::misc_reg::segEffBase ( int  index)
inlinestatic

◆ segLimit()

static RegIndex gem5::X86ISA::misc_reg::segLimit ( int  index)
inlinestatic

◆ segSel()

static RegIndex gem5::X86ISA::misc_reg::segSel ( int  index)
inlinestatic

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