gem5  v22.0.0.1
msr.hh
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28 
29 #ifndef __ARCH_X86_REG_MSR_HH__
30 #define __ARCH_X86_REG_MSR_HH__
31 
32 #include <unordered_map>
33 
34 #include "arch/x86/regs/misc.hh"
35 #include "base/types.hh"
36 
37 namespace gem5
38 {
39 
40 namespace X86ISA
41 {
42 
43 typedef std::unordered_map<Addr, RegIndex> MsrMap;
44 
52 extern const MsrMap msrMap;
53 
65 bool msrAddrToIndex(RegIndex &regNum, Addr addr);
66 
67 } // namespace X86ISA
68 } // namespace gem5
69 
70 #endif // __ARCH_X86_REG_MSR_HH__
gem5::X86ISA::msrMap
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::X86ISA::MsrMap
std::unordered_map< Addr, RegIndex > MsrMap
Definition: msr.hh:43
types.hh
gem5::X86ISA::msrAddrToIndex
bool msrAddrToIndex(RegIndex &reg_num, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition: msr.cc:150
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
misc.hh
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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