gem5
v22.0.0.1
arch
x86
regs
msr.hh
Go to the documentation of this file.
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/*
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* Copyright (c) 2011 Google
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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*/
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#ifndef __ARCH_X86_REG_MSR_HH__
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#define __ARCH_X86_REG_MSR_HH__
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#include <unordered_map>
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#include "
arch/x86/regs/misc.hh
"
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#include "
base/types.hh
"
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namespace
gem5
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{
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namespace
X86ISA
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{
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typedef
std::unordered_map<Addr, RegIndex>
MsrMap
;
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extern
const
MsrMap
msrMap
;
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bool
msrAddrToIndex
(
RegIndex
®Num,
Addr
addr
);
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}
// namespace X86ISA
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}
// namespace gem5
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#endif // __ARCH_X86_REG_MSR_HH__
gem5::X86ISA::msrMap
const MsrMap msrMap
Map between MSR addresses and their corresponding misc registers.
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition:
types.hh:147
gem5::X86ISA::MsrMap
std::unordered_map< Addr, RegIndex > MsrMap
Definition:
msr.hh:43
types.hh
gem5::X86ISA::msrAddrToIndex
bool msrAddrToIndex(RegIndex ®_num, Addr addr)
Find and return the misc reg corresponding to an MSR address.
Definition:
msr.cc:150
gem5::RegIndex
uint16_t RegIndex
Definition:
types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
misc.hh
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition:
types.hh:84
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