gem5 v24.0.0.0
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mult.hh
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1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#ifndef __ARCH_ARM_INSTS_MULT_HH__
39#define __ARCH_ARM_INSTS_MULT_HH__
40
42#include "base/trace.hh"
43
44namespace gem5
45{
46
47namespace ArmISA
48{
49
53class Mult3 : public PredOp
54{
55 protected:
57
58 Mult3(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
59 RegIndex _reg0, RegIndex _reg1, RegIndex _reg2) :
60 PredOp(mnem, _machInst, __opClass),
61 reg0(_reg0), reg1(_reg1), reg2(_reg2)
62 {}
63};
64
68class Mult4 : public Mult3
69{
70 protected:
72
73 Mult4(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
74 RegIndex _reg0, RegIndex _reg1,
75 RegIndex _reg2, RegIndex _reg3) :
76 Mult3(mnem, _machInst, __opClass, _reg0, _reg1, _reg2), reg3(_reg3)
77 {}
78};
79
80} // namespace ArmISA
81} // namespace gem5
82
83#endif //__ARCH_ARM_INSTS_MULT_HH__
Base class for multipy instructions using three registers.
Definition mult.hh:54
Mult3(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _reg0, RegIndex _reg1, RegIndex _reg2)
Definition mult.hh:58
RegIndex reg2
Definition mult.hh:56
RegIndex reg0
Definition mult.hh:56
RegIndex reg1
Definition mult.hh:56
Base class for multipy instructions using four registers.
Definition mult.hh:69
RegIndex reg3
Definition mult.hh:71
Mult4(const char *mnem, ExtMachInst _machInst, OpClass __opClass, RegIndex _reg0, RegIndex _reg1, RegIndex _reg2, RegIndex _reg3)
Definition mult.hh:73
Base class for predicated integer operations.
Definition pred_inst.hh:217
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
uint16_t RegIndex
Definition types.hh:176

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