gem5  v21.1.0.2
pred_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2007-2008 The Florida State University
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #ifndef __ARCH_ARM_INSTS_PREDINST_HH__
42 #define __ARCH_ARM_INSTS_PREDINST_HH__
43 
45 #include "base/compiler.hh"
46 #include "base/logging.hh"
47 #include "base/trace.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 static inline uint32_t
55 rotate_imm(uint32_t immValue, uint32_t rotateValue)
56 {
57  rotateValue &= 31;
58  return rotateValue == 0 ? immValue :
59  (immValue >> rotateValue) | (immValue << (32 - rotateValue));
60 }
61 
62 static inline uint32_t
63 modified_imm(uint8_t ctrlImm, uint8_t dataImm)
64 {
65  uint32_t bigData = dataImm;
66  uint32_t bigCtrl = ctrlImm;
67  if (bigCtrl < 4) {
68  switch (bigCtrl) {
69  case 0:
70  return bigData;
71  case 1:
72  return bigData | (bigData << 16);
73  case 2:
74  return (bigData << 8) | (bigData << 24);
75  case 3:
76  return (bigData << 0) | (bigData << 8) |
77  (bigData << 16) | (bigData << 24);
78  }
79  }
80  bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
81  bigData |= (1 << 7);
82  return bigData << (32 - bigCtrl);
83 }
84 
85 static inline uint64_t
86 simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
87  bool isAarch64 = false)
88 {
89  uint64_t bigData = data;
90  immValid = true;
91  switch (cmode) {
92  case 0x0:
93  case 0x1:
94  bigData = (bigData << 0) | (bigData << 32);
95  break;
96  case 0x2:
97  case 0x3:
98  bigData = (bigData << 8) | (bigData << 40);
99  break;
100  case 0x4:
101  case 0x5:
102  bigData = (bigData << 16) | (bigData << 48);
103  break;
104  case 0x6:
105  case 0x7:
106  bigData = (bigData << 24) | (bigData << 56);
107  break;
108  case 0x8:
109  case 0x9:
110  bigData = (bigData << 0) | (bigData << 16) |
111  (bigData << 32) | (bigData << 48);
112  break;
113  case 0xa:
114  case 0xb:
115  bigData = (bigData << 8) | (bigData << 24) |
116  (bigData << 40) | (bigData << 56);
117  break;
118  case 0xc:
119  bigData = (0xffULL << 0) | (bigData << 8) |
120  (0xffULL << 32) | (bigData << 40);
121  break;
122  case 0xd:
123  bigData = (0xffffULL << 0) | (bigData << 16) |
124  (0xffffULL << 32) | (bigData << 48);
125  break;
126  case 0xe:
127  if (op) {
128  bigData = 0;
129  for (int i = 7; i >= 0; i--) {
130  if (bits(data, i)) {
131  bigData |= (0xFFULL << (i * 8));
132  }
133  }
134  } else {
135  bigData = (bigData << 0) | (bigData << 8) |
136  (bigData << 16) | (bigData << 24) |
137  (bigData << 32) | (bigData << 40) |
138  (bigData << 48) | (bigData << 56);
139  }
140  break;
141  case 0xf:
142  {
143  uint64_t bVal = 0;
144  if (!op) {
145  bVal = bits(bigData, 6) ? (0x1F) : (0x20);
146  bigData = (bits(bigData, 5, 0) << 19) |
147  (bVal << 25) | (bits(bigData, 7) << 31);
148  bigData |= (bigData << 32);
149  break;
150  } else if (isAarch64) {
151  bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
152  bigData = (bits(bigData, 5, 0) << 48) |
153  (bVal << 54) | (bits(bigData, 7) << 63);
154  break;
155  }
156  }
158  default:
159  immValid = false;
160  break;
161  }
162  return bigData;
163 }
164 
166 enum class FpDataType { Fp16, Fp32, Fp64 };
167 
168 static inline uint64_t
170 {
171  uint64_t bigData = data;
172  uint64_t repData;
173  switch (dtype) {
174  case FpDataType::Fp16:
175  repData = bits(data, 6) ? 0x3 : 0;
176  bigData = (bits(bigData, 5, 0) << 6) |
177  (repData << 12) | (bits(~bigData, 6) << 14) |
178  (bits(bigData, 7) << 15);
179  break;
180  case FpDataType::Fp32:
181  repData = bits(data, 6) ? 0x1F : 0;
182  bigData = (bits(bigData, 5, 0) << 19) |
183  (repData << 25) | (bits(~bigData, 6) << 30) |
184  (bits(bigData, 7) << 31);
185  break;
186  case FpDataType::Fp64:
187  repData = bits(data, 6) ? 0xFF : 0;
188  bigData = (bits(bigData, 5, 0) << 48) |
189  (repData << 54) | (bits(~bigData, 6) << 62) |
190  (bits(bigData, 7) << 63);
191  break;
192  default:
193  panic("Unrecognized FP data type");
194  }
195  return bigData;
196 }
197 
198 static inline FpDataType
200 {
201  switch (encoding) {
202  case 1: return FpDataType::Fp16;
203  case 2: return FpDataType::Fp32;
204  case 3: return FpDataType::Fp64;
205  default:
206  panic(
207  "Invalid floating point data type in VFP/SIMD or SVE instruction");
208  }
209 }
210 
214 class PredOp : public ArmStaticInst
215 {
216  protected:
217 
219 
221  PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
222  ArmStaticInst(mnem, _machInst, __opClass)
223  {
224  if (machInst.aarch64)
225  condCode = COND_UC;
226  else if (machInst.itstateMask)
227  condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
228  else
229  condCode = (ConditionCode)(unsigned)machInst.condCode;
230  }
231 };
232 
236 class PredImmOp : public PredOp
237 {
238  protected:
239 
240  uint32_t imm;
241  uint32_t rotated_imm;
242  uint32_t rotated_carry;
243  uint32_t rotate;
244 
246  PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
247  PredOp(mnem, _machInst, __opClass),
249  rotate(machInst.rotate << 1)
250  {
252  if (rotate != 0)
254  }
255 
256  std::string generateDisassembly(
257  Addr pc, const loader::SymbolTable *symtab) const override;
258 };
259 
263 class PredIntOp : public PredOp
264 {
265  protected:
266 
267  uint32_t shift_size;
268  uint32_t shift;
269 
271  PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
272  PredOp(mnem, _machInst, __opClass),
274  {
275  }
276 
277  std::string generateDisassembly(
278  Addr pc, const loader::SymbolTable *symtab) const override;
279 };
280 
281 class DataImmOp : public PredOp
282 {
283  protected:
284  IntRegIndex dest, op1;
285  uint32_t imm;
286  // Whether the carry flag should be modified if that's an option for
287  // this instruction.
288  bool rotC;
289 
290  DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
291  IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
292  PredOp(mnem, _machInst, __opClass),
293  dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
294  {}
295 
296  std::string generateDisassembly(
297  Addr pc, const loader::SymbolTable *symtab) const override;
298 };
299 
300 class DataRegOp : public PredOp
301 {
302  protected:
303  IntRegIndex dest, op1, op2;
304  int32_t shiftAmt;
305  ArmShiftType shiftType;
306 
307  DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
308  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
309  int32_t _shiftAmt, ArmShiftType _shiftType) :
310  PredOp(mnem, _machInst, __opClass),
311  dest(_dest), op1(_op1), op2(_op2),
312  shiftAmt(_shiftAmt), shiftType(_shiftType)
313  {}
314 
315  std::string generateDisassembly(
316  Addr pc, const loader::SymbolTable *symtab) const override;
317 };
318 
319 class DataRegRegOp : public PredOp
320 {
321  protected:
322  IntRegIndex dest, op1, op2, shift;
323  ArmShiftType shiftType;
324 
325  DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
326  IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
327  IntRegIndex _shift, ArmShiftType _shiftType) :
328  PredOp(mnem, _machInst, __opClass),
329  dest(_dest), op1(_op1), op2(_op2), shift(_shift),
330  shiftType(_shiftType)
331  {}
332 
333  std::string generateDisassembly(
334  Addr pc, const loader::SymbolTable *symtab) const override;
335 };
336 
340 class PredMacroOp : public PredOp
341 {
342  protected:
343 
344  uint32_t numMicroops;
346 
348  PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
349  PredOp(mnem, _machInst, __opClass),
350  numMicroops(0), microOps(nullptr)
351  {
352  // We rely on the subclasses of this object to handle the
353  // initialization of the micro-operations, since they are
354  // all of variable length
355  flags[IsMacroop] = true;
356  }
357 
359  {
360  if (numMicroops)
361  delete [] microOps;
362  }
363 
365  fetchMicroop(MicroPC microPC) const override
366  {
367  assert(microPC < numMicroops);
368  return microOps[microPC];
369  }
370 
371  Fault
372  execute(ExecContext *, Trace::InstRecord *) const override
373  {
374  panic("Execute method called when it shouldn't!");
375  }
376 
377  std::string generateDisassembly(
378  Addr pc, const loader::SymbolTable *symtab) const override;
379 };
380 
384 class PredMicroop : public PredOp
385 {
387  PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
388  PredOp(mnem, _machInst, __opClass)
389  {
390  flags[IsMicroop] = true;
391  }
392 
393  void
394  advancePC(PCState &pcState) const override
395  {
396  if (flags[IsLastMicroop])
397  pcState.uEnd();
398  else
399  pcState.uAdvance();
400  }
401 };
402 
403 } // namespace ArmISA
404 } // namespace gem5
405 
406 #endif //__ARCH_ARM_INSTS_PREDINST_HH__
gem5::ArmISA::PredIntOp::PredIntOp
PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: pred_inst.hh:271
gem5::ArmISA::FpDataType::Fp16
@ Fp16
gem5::ArmISA::DataRegOp::DataRegOp
DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType)
Definition: pred_inst.hh:307
gem5::ArmISA::DataImmOp::op1
IntRegIndex op1
Definition: pred_inst.hh:284
gem5::ArmISA::DataImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:82
gem5::ArmISA::PredMicroop
Base class for predicated micro-operations.
Definition: pred_inst.hh:384
gem5::ArmISA::decode_fp_data_type
static FpDataType decode_fp_data_type(uint8_t encoding)
Definition: pred_inst.hh:199
gem5::ArmISA::FpDataType::Fp64
@ Fp64
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::ArmStaticInst
Definition: static_inst.hh:63
gem5::ArmISA::DataRegOp::shiftType
ArmShiftType shiftType
Definition: pred_inst.hh:305
gem5::ArmISA::PredOp::condCode
ConditionCode condCode
Definition: pred_inst.hh:218
gem5::ArmISA::simd_modified_imm
static uint64_t simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid, bool isAarch64=false)
Definition: pred_inst.hh:86
gem5::ArmISA::PredMacroOp::numMicroops
uint32_t numMicroops
Definition: pred_inst.hh:344
gem5::ArmISA::DataRegOp
Definition: pred_inst.hh:300
GEM5_FALLTHROUGH
#define GEM5_FALLTHROUGH
Definition: compiler.hh:61
gem5::ArmISA::modified_imm
static uint32_t modified_imm(uint8_t ctrlImm, uint8_t dataImm)
Definition: pred_inst.hh:63
gem5::ArmISA::DataRegOp::dest
IntRegIndex dest
Definition: pred_inst.hh:303
gem5::ArmISA::PredImmOp::imm
uint32_t imm
Definition: pred_inst.hh:240
gem5::loader::SymbolTable
Definition: symtab.hh:65
gem5::ArmISA::DataImmOp
Definition: pred_inst.hh:281
gem5::ArmISA::PredImmOp::rotated_imm
uint32_t rotated_imm
Definition: pred_inst.hh:241
gem5::ArmISA::PredImmOp::rotated_carry
uint32_t rotated_carry
Definition: pred_inst.hh:242
gem5::ArmISA::encoding
Bitfield< 27, 25 > encoding
Definition: types.hh:90
gem5::ArmISA::PredMacroOp::~PredMacroOp
~PredMacroOp()
Definition: pred_inst.hh:358
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::ArmISA::DataRegRegOp
Definition: pred_inst.hh:319
gem5::ArmISA::ArmStaticInst::machInst
ExtMachInst machInst
Definition: static_inst.hh:149
gem5::ArmISA::DataRegOp::op1
IntRegIndex op1
Definition: pred_inst.hh:303
gem5::ArmISA::PredImmOp::rotate
uint32_t rotate
Definition: pred_inst.hh:243
gem5::ArmISA::DataRegRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:102
gem5::RefCountingPtr< StaticInst >
gem5::ArmISA::DataRegOp::op2
IntRegIndex op2
Definition: pred_inst.hh:303
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::ArmISA::PredMacroOp::PredMacroOp
PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: pred_inst.hh:348
gem5::ArmISA::DataRegOp::shiftAmt
int32_t shiftAmt
Definition: pred_inst.hh:304
gem5::ArmISA::FpDataType
FpDataType
Floating point data types.
Definition: pred_inst.hh:166
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::ArmISA::vfp_modified_imm
static uint64_t vfp_modified_imm(uint8_t data, FpDataType dtype)
Definition: pred_inst.hh:169
gem5::ArmISA::DataRegOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:92
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
gem5::ArmISA::PredImmOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:67
gem5::ArmISA::DataRegRegOp::DataRegRegOp
DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, ArmShiftType _shiftType)
Definition: pred_inst.hh:325
gem5::ArmISA::PredMacroOp::microOps
StaticInstPtr * microOps
Definition: pred_inst.hh:345
gem5::ArmISA::PredIntOp::shift_size
uint32_t shift_size
Definition: pred_inst.hh:267
gem5::ArmISA::shiftSize
Bitfield< 11, 7 > shiftSize
Definition: types.hh:116
gem5::StaticInst::flags
std::bitset< Num_Flags > flags
Flag values for this instruction.
Definition: static_inst.hh:103
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
compiler.hh
gem5::ArmISA::DataImmOp::imm
uint32_t imm
Definition: pred_inst.hh:285
gem5::ArmISA::PredMicroop::advancePC
void advancePC(PCState &pcState) const override
Definition: pred_inst.hh:394
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::PredMacroOp
Base class for predicated macro-operations.
Definition: pred_inst.hh:340
gem5::ArmISA::DataRegRegOp::dest
IntRegIndex dest
Definition: pred_inst.hh:322
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::PredImmOp
Base class for predicated immediate operations.
Definition: pred_inst.hh:236
gem5::ArmISA::PredMicroop::PredMicroop
PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: pred_inst.hh:387
gem5::ArmISA::DataRegRegOp::shift
IntRegIndex shift
Definition: pred_inst.hh:322
gem5::ArmISA::ConditionCode
ConditionCode
Definition: cc.hh:67
static_inst.hh
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
gem5::ArmISA::DataImmOp::dest
IntRegIndex dest
Definition: pred_inst.hh:284
logging.hh
gem5::ArmISA::FpDataType::Fp32
@ Fp32
gem5::ArmISA::PredIntOp
Base class for predicated integer operations.
Definition: pred_inst.hh:263
gem5::ExecContext
The ExecContext is an abstract base class the provides the interface used by the ISA to manipulate th...
Definition: exec_context.hh:73
gem5::ArmISA::DataImmOp::rotC
bool rotC
Definition: pred_inst.hh:288
gem5::ArmISA::PredOp
Base class for predicated integer operations.
Definition: pred_inst.hh:214
gem5::ArmISA::PredMacroOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:112
trace.hh
gem5::ArmISA::PredIntOp::generateDisassembly
std::string generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override
Internal function to generate disassembly string.
Definition: pred_inst.cc:49
gem5::Trace::InstRecord
Definition: insttracer.hh:58
gem5::ArmISA::rotate_imm
static uint32_t rotate_imm(uint32_t immValue, uint32_t rotateValue)
Definition: pred_inst.hh:55
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::PredMacroOp::fetchMicroop
StaticInstPtr fetchMicroop(MicroPC microPC) const override
Return the microop that goes with a particular micropc.
Definition: pred_inst.hh:365
gem5::ArmISA::DataRegRegOp::op2
IntRegIndex op2
Definition: pred_inst.hh:322
gem5::ArmISA::DataRegRegOp::op1
IntRegIndex op1
Definition: pred_inst.hh:322
gem5::ArmISA::DataImmOp::DataImmOp
DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC)
Definition: pred_inst.hh:290
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::ArmISA::PredMacroOp::execute
Fault execute(ExecContext *, Trace::InstRecord *) const override
Definition: pred_inst.hh:372
gem5::ArmISA::PredIntOp::shift
uint32_t shift
Definition: pred_inst.hh:268
gem5::ArmISA::DataRegRegOp::shiftType
ArmShiftType shiftType
Definition: pred_inst.hh:323
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::ArmISA::PredImmOp::PredImmOp
PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: pred_inst.hh:246
gem5::ArmISA::PredOp::PredOp
PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
Constructor.
Definition: pred_inst.hh:221

Generated on Tue Sep 21 2021 12:24:35 for gem5 by doxygen 1.8.17