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gem5 v24.0.0.0
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Go to the source code of this file.
Classes | |
| struct | PMCAP |
| Defines the Power Management capability register and all its associated bitfields for a PCIe device. More... | |
| struct | MSICAP |
| Defines the MSI Capability register and its associated bitfields for the a PCI/PCIe device. More... | |
| union | MSIXCAP |
| union | MSIXTable |
| struct | MSIXPbaEntry |
| struct | PXCAP |
| Defines the PCI Express capability register and its associated bitfields for a PCIe device. More... | |
Macros | |
| #define | PCI_VENDOR_ID 0x00 |
| #define | PCI_DEVICE_ID 0x02 |
| #define | PCI_COMMAND 0x04 |
| #define | PCI_STATUS 0x06 |
| #define | PCI_REVISION_ID 0x08 |
| #define | PCI_CLASS_CODE 0x09 |
| #define | PCI_SUB_CLASS_CODE 0x0A |
| #define | PCI_BASE_CLASS_CODE 0x0B |
| #define | PCI_CACHE_LINE_SIZE 0x0C |
| #define | PCI_LATENCY_TIMER 0x0D |
| #define | PCI_HEADER_TYPE 0x0E |
| #define | PCI_BIST 0x0F |
| #define | PCI_CMD_BME 0x04 |
| #define | PCI_CMD_MSE 0x02 |
| #define | PCI_CMD_IOSE 0x01 |
| #define | PCI0_BASE_ADDR0 0x10 |
| #define | PCI0_BASE_ADDR1 0x14 |
| #define | PCI0_BASE_ADDR2 0x18 |
| #define | PCI0_BASE_ADDR3 0x1C |
| #define | PCI0_BASE_ADDR4 0x20 |
| #define | PCI0_BASE_ADDR5 0x24 |
| #define | PCI0_CIS 0x28 |
| #define | PCI0_SUB_VENDOR_ID 0x2C |
| #define | PCI0_SUB_SYSTEM_ID 0x2E |
| #define | PCI0_ROM_BASE_ADDR 0x30 |
| #define | PCI0_CAP_PTR 0x34 |
| #define | PCI0_RESERVED 0x35 |
| #define | PCI0_INTERRUPT_LINE 0x3C |
| #define | PCI0_INTERRUPT_PIN 0x3D |
| #define | PCI0_MINIMUM_GRANT 0x3E |
| #define | PCI0_MAXIMUM_LATENCY 0x3F |
| #define | PCI1_BASE_ADDR0 0x10 |
| #define | PCI1_BASE_ADDR1 0x14 |
| #define | PCI1_PRI_BUS_NUM 0x18 |
| #define | PCI1_SEC_BUS_NUM 0x19 |
| #define | PCI1_SUB_BUS_NUM 0x1A |
| #define | PCI1_SEC_LAT_TIMER 0x1B |
| #define | PCI1_IO_BASE 0x1C |
| #define | PCI1_IO_LIMIT 0x1D |
| #define | PCI1_SECONDARY_STATUS 0x1E |
| #define | PCI1_MEM_BASE 0x20 |
| #define | PCI1_MEM_LIMIT 0x22 |
| #define | PCI1_PRF_MEM_BASE 0x24 |
| #define | PCI1_PRF_MEM_LIMIT 0x26 |
| #define | PCI1_PRF_BASE_UPPER 0x28 |
| #define | PCI1_PRF_LIMIT_UPPER 0x2C |
| #define | PCI1_IO_BASE_UPPER 0x30 |
| #define | PCI1_IO_LIMIT_UPPER 0x32 |
| #define | PCI1_RESERVED 0x34 |
| #define | PCI1_ROM_BASE_ADDR 0x38 |
| #define | PCI1_INTR_LINE 0x3C |
| #define | PCI1_INTR_PIN 0x3D |
| #define | PCI1_BRIDGE_CTRL 0x3E |
| #define | PCI_DEVICE_SPECIFIC 0x40 |
| #define | PCI_CONFIG_SIZE 0xFF |
| #define | PCI_VENDOR_DEC 0x1011 |
| #define | PCI_VENDOR_NCR 0x101A |
| #define | PCI_VENDOR_QLOGIC 0x1077 |
| #define | PCI_VENDOR_SIMOS 0x1291 |
| #define | PCI_PRODUCT_DEC_PZA 0x0008 |
| #define | PCI_PRODUCT_NCR_810 0x0001 |
| #define | PCI_PRODUCT_QLOGIC_ISP1020 0x1020 |
| #define | PCI_PRODUCT_SIMOS_SIMOS 0x1291 |
| #define | PCI_PRODUCT_SIMOS_ETHER 0x1292 |
| #define | PMCAP_ID 0x00 |
| PCIe capability list offsets internal to the entry. | |
| #define | PMCAP_PC 0x02 |
| #define | PMCAP_PMCS 0x04 |
| #define | PMCAP_SIZE 0x06 |
| #define | MSICAP_ID 0x00 |
| #define | MSICAP_MC 0x02 |
| #define | MSICAP_MA 0x04 |
| #define | MSICAP_MUA 0x08 |
| #define | MSICAP_MD 0x0C |
| #define | MSICAP_MMASK 0x10 |
| #define | MSICAP_MPEND 0x14 |
| #define | MSICAP_SIZE 0x18 |
| #define | MSIXCAP_ID 0x00 |
| #define | MSIXCAP_MXC 0x02 |
| #define | MSIXCAP_MTAB 0x04 |
| #define | MSIXCAP_MPBA 0x08 |
| #define | MSIXCAP_SIZE 0x0C |
| #define | PXCAP_ID 0x00 |
| #define | PXCAP_PXCAP 0x02 |
| #define | PXCAP_PXDCAP 0x04 |
| #define | PXCAP_PXDC 0x08 |
| #define | PXCAP_PXDS 0x0A |
| #define | PXCAP_PXLCAP 0x0C |
| #define | PXCAP_PXLC 0x10 |
| #define | PXCAP_PXLS 0x12 |
| #define | PXCAP_PXDCAP2 0x24 |
| #define | PXCAP_PXDC2 0x28 |
| #define | PXCAP_SIZE 0x30 |
| #define | MSIXVECS_PER_PBA 64 |
Functions | |
| BitUnion16 (PciCommandRegister) Bitfield< 15 | |
| EndBitUnion (PciCommandRegister) union PCIConfig | |
Variables | |
| reserved | |
| Bitfield< 9 > | fastBackToBackEn |
| Bitfield< 8 > | serrEn |
| Bitfield< 7 > | steppingControl |
| Bitfield< 6 > | parityErrResp |
| Bitfield< 5 > | vgaPaletteSnoopEn |
| Bitfield< 4 > | memWriteInvEn |
| Bitfield< 3 > | specialCycles |
| Bitfield< 2 > | busMaster |
| Bitfield< 1 > | memorySpace |
| Bitfield< 0 > | ioSpace |
| #define MSIXVECS_PER_PBA 64 |
Definition at line 319 of file pcireg.h.
Referenced by gem5::PciDevice::PciDevice(), and gem5::PciDevice::serialize().
| #define PCI0_BASE_ADDR0 0x10 |
Definition at line 122 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_BASE_ADDR1 0x14 |
Definition at line 123 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_BASE_ADDR2 0x18 |
Definition at line 124 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_BASE_ADDR3 0x1C |
Definition at line 125 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_BASE_ADDR4 0x20 |
Definition at line 126 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_BASE_ADDR5 0x24 |
Definition at line 127 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_INTERRUPT_LINE 0x3C |
Definition at line 134 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_INTERRUPT_PIN 0x3D |
Definition at line 135 of file pcireg.h.
Referenced by gem5::AMDGPUDevice::readConfig(), and gem5::PciDevice::writeConfig().
| #define PCI0_MAXIMUM_LATENCY 0x3F |
Definition at line 137 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_MINIMUM_GRANT 0x3E |
Definition at line 136 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI0_ROM_BASE_ADDR 0x30 |
Definition at line 131 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI_CACHE_LINE_SIZE 0x0C |
Definition at line 111 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI_CLASS_CODE 0x09 |
Definition at line 108 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI_CMD_IOSE 0x01 |
Definition at line 119 of file pcireg.h.
Referenced by gem5::NSGigE::writeConfig().
| #define PCI_CMD_MSE 0x02 |
Definition at line 118 of file pcireg.h.
Referenced by gem5::sinic::Device::read(), and gem5::sinic::Device::write().
| #define PCI_COMMAND 0x04 |
Definition at line 105 of file pcireg.h.
Referenced by gem5::NSGigE::writeConfig(), and gem5::PciDevice::writeConfig().
| #define PCI_CONFIG_SIZE 0xFF |
Definition at line 165 of file pcireg.h.
Referenced by gem5::AMDGPUDevice::readConfig(), gem5::IdeController::readConfig(), gem5::PciDevice::readConfig(), gem5::AMDGPUDevice::writeConfig(), gem5::IdeController::writeConfig(), gem5::IGbE::writeConfig(), gem5::NSGigE::writeConfig(), and gem5::PciDevice::writeConfig().
| #define PCI_DEVICE_SPECIFIC 0x40 |
Definition at line 164 of file pcireg.h.
Referenced by gem5::AMDGPUDevice::readConfig(), gem5::IdeController::readConfig(), gem5::PciDevice::readConfig(), gem5::AMDGPUDevice::writeConfig(), gem5::IdeController::writeConfig(), gem5::IGbE::writeConfig(), gem5::NSGigE::writeConfig(), and gem5::PciDevice::writeConfig().
| #define PCI_LATENCY_TIMER 0x0D |
Definition at line 112 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI_REVISION_ID 0x08 |
Definition at line 107 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PCI_STATUS 0x06 |
Definition at line 106 of file pcireg.h.
Referenced by gem5::PciDevice::writeConfig().
| #define PMCAP_ID 0x00 |
| BitUnion16 | ( | PciCommandRegister | ) |
| EndBitUnion | ( | PciCommandRegister | ) |
| reserved |
Definition at line 54 of file pcireg.h.
Referenced by EndBitUnion(), gem5::EndBitUnion(), and gem5::qemu::FwCfg::Directory::update().