48 #include <sys/types.h>
81 uint8_t cacheLineSize;
87 uint16_t subsystemVendorID;
89 uint32_t expansionROM;
90 uint8_t capabilityPtr;
95 uint8_t interruptLine;
98 uint8_t maximumLatency;
103 #define PCI_VENDOR_ID 0x00
104 #define PCI_DEVICE_ID 0x02
105 #define PCI_COMMAND 0x04
106 #define PCI_STATUS 0x06
107 #define PCI_REVISION_ID 0x08
108 #define PCI_CLASS_CODE 0x09
109 #define PCI_SUB_CLASS_CODE 0x0A
110 #define PCI_BASE_CLASS_CODE 0x0B
111 #define PCI_CACHE_LINE_SIZE 0x0C
112 #define PCI_LATENCY_TIMER 0x0D
113 #define PCI_HEADER_TYPE 0x0E
114 #define PCI_BIST 0x0F
117 #define PCI_CMD_BME 0x04
118 #define PCI_CMD_MSE 0x02
119 #define PCI_CMD_IOSE 0x01
122 #define PCI0_BASE_ADDR0 0x10
123 #define PCI0_BASE_ADDR1 0x14
124 #define PCI0_BASE_ADDR2 0x18
125 #define PCI0_BASE_ADDR3 0x1C
126 #define PCI0_BASE_ADDR4 0x20
127 #define PCI0_BASE_ADDR5 0x24
128 #define PCI0_CIS 0x28
129 #define PCI0_SUB_VENDOR_ID 0x2C
130 #define PCI0_SUB_SYSTEM_ID 0x2E
131 #define PCI0_ROM_BASE_ADDR 0x30
132 #define PCI0_CAP_PTR 0x34
133 #define PCI0_RESERVED 0x35
134 #define PCI0_INTERRUPT_LINE 0x3C
135 #define PCI0_INTERRUPT_PIN 0x3D
136 #define PCI0_MINIMUM_GRANT 0x3E
137 #define PCI0_MAXIMUM_LATENCY 0x3F
140 #define PCI1_BASE_ADDR0 0x10
141 #define PCI1_BASE_ADDR1 0x14
142 #define PCI1_PRI_BUS_NUM 0x18
143 #define PCI1_SEC_BUS_NUM 0x19
144 #define PCI1_SUB_BUS_NUM 0x1A
145 #define PCI1_SEC_LAT_TIMER 0x1B
146 #define PCI1_IO_BASE 0x1C
147 #define PCI1_IO_LIMIT 0x1D
148 #define PCI1_SECONDARY_STATUS 0x1E
149 #define PCI1_MEM_BASE 0x20
150 #define PCI1_MEM_LIMIT 0x22
151 #define PCI1_PRF_MEM_BASE 0x24
152 #define PCI1_PRF_MEM_LIMIT 0x26
153 #define PCI1_PRF_BASE_UPPER 0x28
154 #define PCI1_PRF_LIMIT_UPPER 0x2C
155 #define PCI1_IO_BASE_UPPER 0x30
156 #define PCI1_IO_LIMIT_UPPER 0x32
157 #define PCI1_RESERVED 0x34
158 #define PCI1_ROM_BASE_ADDR 0x38
159 #define PCI1_INTR_LINE 0x3C
160 #define PCI1_INTR_PIN 0x3D
161 #define PCI1_BRIDGE_CTRL 0x3E
164 #define PCI_DEVICE_SPECIFIC 0x40
165 #define PCI_CONFIG_SIZE 0xFF
168 #define PCI_VENDOR_DEC 0x1011
169 #define PCI_VENDOR_NCR 0x101A
170 #define PCI_VENDOR_QLOGIC 0x1077
171 #define PCI_VENDOR_SIMOS 0x1291
174 #define PCI_PRODUCT_DEC_PZA 0x0008
175 #define PCI_PRODUCT_NCR_810 0x0001
176 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
177 #define PCI_PRODUCT_SIMOS_SIMOS 0x1291
178 #define PCI_PRODUCT_SIMOS_ETHER 0x1292
185 #define PMCAP_ID 0x00
186 #define PMCAP_PC 0x02
187 #define PMCAP_PMCS 0x04
188 #define PMCAP_SIZE 0x06
190 #define MSICAP_ID 0x00
191 #define MSICAP_MC 0x02
192 #define MSICAP_MA 0x04
193 #define MSICAP_MUA 0x08
194 #define MSICAP_MD 0x0C
195 #define MSICAP_MMASK 0x10
196 #define MSICAP_MPEND 0x14
197 #define MSICAP_SIZE 0x18
199 #define MSIXCAP_ID 0x00
200 #define MSIXCAP_MXC 0x02
201 #define MSIXCAP_MTAB 0x04
202 #define MSIXCAP_MPBA 0x08
203 #define MSIXCAP_SIZE 0x0C
205 #define PXCAP_ID 0x00
206 #define PXCAP_PXCAP 0x02
207 #define PXCAP_PXDCAP 0x04
208 #define PXCAP_PXDC 0x08
209 #define PXCAP_PXDS 0x0A
210 #define PXCAP_PXLCAP 0x0C
211 #define PXCAP_PXLC 0x10
212 #define PXCAP_PXLS 0x12
213 #define PXCAP_PXDCAP2 0x24
214 #define PXCAP_PXDC2 0x28
215 #define PXCAP_SIZE 0x30
319 #define MSIXVECS_PER_PBA 64
Bitfield< 47, 6 > baseAddr
Bitfield< 1 > memorySpace
Bitfield< 9 > fastBackToBackEn
EndBitUnion(PciCommandRegister) union PCIConfig
Bitfield< 7 > steppingControl
Bitfield< 4 > memWriteInvEn
Bitfield< 6 > parityErrResp
BitUnion16(PciCommandRegister) Bitfield< 15
Bitfield< 3 > specialCycles
Bitfield< 5 > vgaPaletteSnoopEn
Defines the PCI Express capability register and its associated bitfields for a PCIe device.
Defines the MSI Capability register and its associated bitfields for the a PCI/PCIe device.
struct MSIXTable::@321 fields
Defines the Power Management capability register and all its associated bitfields for a PCIe device.