gem5  v21.1.0.2
pcireg.h
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1 /*
2  * Copyright (c) 2013 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2001-2005 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 /* @file
42  * Device register definitions for a device's PCI config space
43  */
44 
45 #ifndef __PCIREG_H__
46 #define __PCIREG_H__
47 
48 #include <sys/types.h>
49 
50 #include "base/bitfield.hh"
51 #include "base/bitunion.hh"
52 
53 BitUnion16(PciCommandRegister)
54  Bitfield<15, 10> reserved;
55  Bitfield<9> fastBackToBackEn;
56  Bitfield<8> serrEn;
57  Bitfield<7> steppingControl;
58  Bitfield<6> parityErrResp;
59  Bitfield<5> vgaPaletteSnoopEn;
60  Bitfield<4> memWriteInvEn;
61  Bitfield<3> specialCycles;
62  Bitfield<2> busMaster;
63  Bitfield<1> memorySpace;
64  Bitfield<0> ioSpace;
65 EndBitUnion(PciCommandRegister)
66 
67 union PCIConfig
68 {
69  uint8_t data[64];
70 
71  struct
72  {
73  uint16_t vendor;
74  uint16_t device;
75  uint16_t command;
76  uint16_t status;
77  uint8_t revision;
78  uint8_t progIF;
79  uint8_t subClassCode;
80  uint8_t classCode;
81  uint8_t cacheLineSize;
82  uint8_t latencyTimer;
83  uint8_t headerType;
84  uint8_t bist;
85  uint32_t baseAddr[6];
86  uint32_t cardbusCIS;
87  uint16_t subsystemVendorID;
88  uint16_t subsystemID;
89  uint32_t expansionROM;
90  uint8_t capabilityPtr;
91  // Was 8 bytes in the legacy PCI spec, but to support PCIe
92  // this field is now 7 bytes with PCIe's addition of the
93  // capability list pointer.
94  uint8_t reserved[7];
95  uint8_t interruptLine;
96  uint8_t interruptPin;
97  uint8_t minimumGrant;
98  uint8_t maximumLatency;
99  };
100 };
101 
102 // Common PCI offsets
103 #define PCI_VENDOR_ID 0x00 // Vendor ID ro
104 #define PCI_DEVICE_ID 0x02 // Device ID ro
105 #define PCI_COMMAND 0x04 // Command rw
106 #define PCI_STATUS 0x06 // Status rw
107 #define PCI_REVISION_ID 0x08 // Revision ID ro
108 #define PCI_CLASS_CODE 0x09 // Class Code ro
109 #define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro
110 #define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro
111 #define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+
112 #define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+
113 #define PCI_HEADER_TYPE 0x0E // Header Type ro
114 #define PCI_BIST 0x0F // Built in self test rw
115 
116 // some pci command reg bitfields
117 #define PCI_CMD_BME 0x04 // Bus master function enable
118 #define PCI_CMD_MSE 0x02 // Memory Space Access enable
119 #define PCI_CMD_IOSE 0x01 // I/O space enable
120 
121 // Type 0 PCI offsets
122 #define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
123 #define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
124 #define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw
125 #define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw
126 #define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw
127 #define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw
128 #define PCI0_CIS 0x28 // CardBus CIS Pointer ro
129 #define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro
130 #define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro
131 #define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw
132 #define PCI0_CAP_PTR 0x34 // Capability list pointer ro
133 #define PCI0_RESERVED 0x35
134 #define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw
135 #define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro
136 #define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro
137 #define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro
138 
139 // Type 1 PCI offsets
140 #define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw
141 #define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw
142 #define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw
143 #define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw
144 #define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw
145 #define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+
146 #define PCI1_IO_BASE 0x1C // I/O Base rw
147 #define PCI1_IO_LIMIT 0x1D // I/O Limit rw
148 #define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw
149 #define PCI1_MEM_BASE 0x20 // Memory Base rw
150 #define PCI1_MEM_LIMIT 0x22 // Memory Limit rw
151 #define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw
152 #define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw
153 #define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw
154 #define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw
155 #define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw
156 #define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw
157 #define PCI1_RESERVED 0x34 // Reserved ro
158 #define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw
159 #define PCI1_INTR_LINE 0x3C // Interrupt Line rw
160 #define PCI1_INTR_PIN 0x3D // Interrupt Pin ro
161 #define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw
162 
163 // Device specific offsets
164 #define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
165 #define PCI_CONFIG_SIZE 0xFF
166 
167 // Some Vendor IDs
168 #define PCI_VENDOR_DEC 0x1011
169 #define PCI_VENDOR_NCR 0x101A
170 #define PCI_VENDOR_QLOGIC 0x1077
171 #define PCI_VENDOR_SIMOS 0x1291
172 
173 // Some Product IDs
174 #define PCI_PRODUCT_DEC_PZA 0x0008
175 #define PCI_PRODUCT_NCR_810 0x0001
176 #define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
177 #define PCI_PRODUCT_SIMOS_SIMOS 0x1291
178 #define PCI_PRODUCT_SIMOS_ETHER 0x1292
179 
185 #define PMCAP_ID 0x00
186 #define PMCAP_PC 0x02
187 #define PMCAP_PMCS 0x04
188 #define PMCAP_SIZE 0x06
189 
190 #define MSICAP_ID 0x00
191 #define MSICAP_MC 0x02
192 #define MSICAP_MA 0x04
193 #define MSICAP_MUA 0x08
194 #define MSICAP_MD 0x0C
195 #define MSICAP_MMASK 0x10
196 #define MSICAP_MPEND 0x14
197 #define MSICAP_SIZE 0x18
198 
199 #define MSIXCAP_ID 0x00
200 #define MSIXCAP_MXC 0x02
201 #define MSIXCAP_MTAB 0x04
202 #define MSIXCAP_MPBA 0x08
203 #define MSIXCAP_SIZE 0x0C
204 
205 #define PXCAP_ID 0x00
206 #define PXCAP_PXCAP 0x02
207 #define PXCAP_PXDCAP 0x04
208 #define PXCAP_PXDC 0x08
209 #define PXCAP_PXDS 0x0A
210 #define PXCAP_PXLCAP 0x0C
211 #define PXCAP_PXLC 0x10
212 #define PXCAP_PXLS 0x12
213 #define PXCAP_PXDCAP2 0x24
214 #define PXCAP_PXDC2 0x28
215 #define PXCAP_SIZE 0x30
216 
221 union PMCAP
222 {
223  uint8_t data[6];
224  struct
225  {
226  uint16_t pid; /* 0:7 cid
227  * 8:15 next
228  */
229  uint16_t pc; /* 0:2 vs
230  * 3 pmec
231  * 4 reserved
232  * 5 dsi
233  * 6:8 auxc
234  * 9 d1s
235  * 10 d2s
236  * 11:15 psup
237  */
238  uint16_t pmcs; /* 0:1 ps
239  * 2 reserved
240  * 3 nsfrst
241  * 4:7 reserved
242  * 8 pmee
243  * 9:12 dse
244  * 13:14 dsc
245  * 15 pmes
246  */
247  };
248 };
249 
256 union MSICAP
257 {
258  uint8_t data[24];
259  struct
260  {
261  uint16_t mid; /* 0:7 cid
262  * 8:15 next
263  */
264  uint16_t mc; /* 0 msie;
265  * 1:3 mmc;
266  * 4:6 mme;
267  * 7 c64;
268  * 8 pvm;
269  * 9:15 reserved;
270  */
271  uint32_t ma; /* 0:1 reserved
272  * 2:31 addr
273  */
274  uint32_t mua;
275  uint16_t md;
276  uint32_t mmask;
277  uint32_t mpend;
278  };
279 };
280 
285 union MSIXCAP
286 {
287  uint8_t data[12];
288  struct
289  {
290  uint16_t mxid; /* 0:7 cid
291  * 8:15 next
292  */
293  uint16_t mxc; /* 0:10 ts;
294  * 11:13 reserved;
295  * 14 fm;
296  * 15 mxe;
297  */
298  uint32_t mtab; /* 0:2 tbir;
299  * 3:31 to;
300  */
301  uint32_t mpba; /* 0:2 pbir;
302  * 3:31> pbao;
303  */
304  };
305 };
306 
308 {
309  struct
310  {
311  uint32_t addr_lo;
312  uint32_t addr_hi;
313  uint32_t msg_data;
314  uint32_t vec_ctrl;
315  } fields;
316  uint32_t data[4];
317 };
318 
319 #define MSIXVECS_PER_PBA 64
321 {
322  uint64_t bits;
323 };
324 
329 struct PXCAP
330 {
331  uint8_t data[48];
332  struct
333  {
334  uint16_t pxid; /* 0:7 cid
335  * 8:15 next
336  */
337  uint16_t pxcap; /* 0:3 ver;
338  * 4:7 dpt;
339  * 8 si;
340  * 9:13 imn;
341  * 14:15 reserved;
342  */
343  uint32_t pxdcap; /* 0:2 mps;
344  * 3:4 pfs;
345  * 5 etfs;
346  * 6:8 l0sl;
347  * 9:11 l1l;
348  * 12:14 reserved;
349  * 15 rer;
350  * 16:17 reserved;
351  * 18:25 csplv;
352  * 26:27 cspls;
353  * 28 flrc;
354  * 29:31 reserved;
355  */
356  uint16_t pxdc; /* 0 cere;
357  * 1 nfere;
358  * 2 fere;
359  * 3 urre;
360  * 4 ero;
361  * 5:7 mps;
362  * 8 ete;
363  * 9 pfe;
364  * 10 appme;
365  * 11 ens;
366  * 12:14 mrrs;
367  * 15 func_reset;
368  */
369  uint16_t pxds; /* 0 ced;
370  * 1 nfed;
371  * 2 fed;
372  * 3 urd;
373  * 4 apd;
374  * 5 tp;
375  * 6:15 reserved;
376  */
377  uint32_t pxlcap; /* 0:3 sls;
378  * 4:9 mlw;
379  * 10:11 aspms;
380  * 12:14 l0sel;
381  * 15:17 l1el;
382  * 18 cpm;
383  * 19 sderc;
384  * 20 dllla;
385  * 21 lbnc;
386  * 22:23 reserved;
387  * 24:31 pn;
388  */
389  uint16_t pxlc; /* 0:1 aspmc;
390  * 2 reserved;
391  * 3 rcb;
392  * 4:5 reserved;
393  * 6 ccc;
394  * 7 es;
395  * 8 ecpm;
396  * 9 hawd;
397  * 10:15 reserved;
398  */
399  uint16_t pxls; /* 0:3 cls;
400  * 4:9 nlw;
401  * 10:11 reserved;
402  * 12 slot_clk_config;
403  * 13:15 reserved;
404  */
405  uint8_t reserved[20];
406  uint32_t pxdcap2; /* 0:3 ctrs;
407  * 4 ctds;
408  * 5 arifs;
409  * 6 aors;
410  * 7 aocs32;
411  * 8 aocs64;
412  * 9 ccs128;
413  * 10 nprpr;
414  * 11 ltrs;
415  * 12:13 tphcs;
416  * 14:17 reserved;
417  * 18:19 obffs;
418  * 20 effs;
419  * 21 eetps;
420  * 22:23 meetp;
421  * 24:31 reserved;
422  */
423  uint32_t pxdc2; /* 0:3 ctv;
424  * 4 ctd;
425  * 5:9 reserved;
426  * 10 ltrme;
427  * 11:12 reserved;
428  * 13:14 obffe;
429  * 15:31 reserved;
430  */
431  };
432 };
433 #endif // __PCIREG_H__
MSIXCAP::mtab
uint32_t mtab
Definition: pcireg.h:298
MSIXTable::msg_data
uint32_t msg_data
Definition: pcireg.h:313
PXCAP::pxdc2
uint32_t pxdc2
Definition: pcireg.h:423
MSIXCAP::data
uint8_t data[12]
Definition: pcireg.h:287
data
const char data[]
Definition: circlebuf.test.cc:48
MSIXTable::data
uint32_t data[4]
Definition: pcireg.h:316
PMCAP::pc
uint16_t pc
Definition: pcireg.h:229
MSIXTable::vec_ctrl
uint32_t vec_ctrl
Definition: pcireg.h:314
PXCAP::reserved
uint8_t reserved[20]
Definition: pcireg.h:405
memorySpace
Bitfield< 1 > memorySpace
Definition: pcireg.h:63
PXCAP::pxlcap
uint32_t pxlcap
Definition: pcireg.h:377
fastBackToBackEn
Bitfield< 9 > fastBackToBackEn
Definition: pcireg.h:55
busMaster
Bitfield< 2 > busMaster
Definition: pcireg.h:62
MSIXTable::addr_hi
uint32_t addr_hi
Definition: pcireg.h:312
PXCAP::pxds
uint16_t pxds
Definition: pcireg.h:369
specialCycles
Bitfield< 3 > specialCycles
Definition: pcireg.h:61
MSICAP::mmask
uint32_t mmask
Definition: pcireg.h:276
MSIXTable
Definition: pcireg.h:307
PXCAP::data
uint8_t data[48]
Definition: pcireg.h:331
steppingControl
Bitfield< 7 > steppingControl
Definition: pcireg.h:57
reserved
reserved
Definition: pcireg.h:54
MSICAP::data
uint8_t data[24]
Definition: pcireg.h:258
MSIXCAP::mxc
uint16_t mxc
Definition: pcireg.h:293
MSIXPbaEntry
Definition: pcireg.h:320
bitfield.hh
PMCAP
Definition: pcireg.h:221
MSICAP::mc
uint16_t mc
Definition: pcireg.h:264
MSIXCAP::mpba
uint32_t mpba
Definition: pcireg.h:301
EndBitUnion
EndBitUnion(PciCommandRegister) union PCIConfig
Definition: pcireg.h:65
MSIXPbaEntry::bits
uint64_t bits
Definition: pcireg.h:322
bitunion.hh
PXCAP::pxid
uint16_t pxid
Definition: pcireg.h:334
MSICAP::md
uint16_t md
Definition: pcireg.h:275
PXCAP::pxdcap
uint32_t pxdcap
Definition: pcireg.h:343
PXCAP::pxdcap2
uint32_t pxdcap2
Definition: pcireg.h:406
MSIXTable::fields
struct MSIXTable::@95 fields
PXCAP
Definition: pcireg.h:329
MSIXCAP::mxid
uint16_t mxid
Definition: pcireg.h:290
PXCAP::pxls
uint16_t pxls
Definition: pcireg.h:399
memWriteInvEn
Bitfield< 4 > memWriteInvEn
Definition: pcireg.h:60
PXCAP::pxcap
uint16_t pxcap
Definition: pcireg.h:337
vgaPaletteSnoopEn
Bitfield< 5 > vgaPaletteSnoopEn
Definition: pcireg.h:59
MSIXTable::addr_lo
uint32_t addr_lo
Definition: pcireg.h:311
ioSpace
Bitfield< 0 > ioSpace
Definition: pcireg.h:64
BitUnion16
BitUnion16(PciCommandRegister) Bitfield< 15
MSIXCAP
Definition: pcireg.h:285
PMCAP::pid
uint16_t pid
Definition: pcireg.h:226
PMCAP::data
uint8_t data[6]
Definition: pcireg.h:223
MSICAP
Definition: pcireg.h:256
MSICAP::mid
uint16_t mid
Definition: pcireg.h:261
MSICAP::mpend
uint32_t mpend
Definition: pcireg.h:277
MSICAP::mua
uint32_t mua
Definition: pcireg.h:274
MSICAP::ma
uint32_t ma
Definition: pcireg.h:271
parityErrResp
Bitfield< 6 > parityErrResp
Definition: pcireg.h:58
serrEn
Bitfield< 8 > serrEn
Definition: pcireg.h:56
PXCAP::pxdc
uint16_t pxdc
Definition: pcireg.h:356
PMCAP::pmcs
uint16_t pmcs
Definition: pcireg.h:238
PXCAP::pxlc
uint16_t pxlc
Definition: pcireg.h:389
gem5::ArmISA::status
Bitfield< 5, 0 > status
Definition: misc_types.hh:422

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