gem5
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arch
riscv
idle_event.hh
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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*/
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#ifndef __KERN_RISCV_IDLE_EVENT_HH__
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#define __KERN_RISCV_IDLE_EVENT_HH__
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#include "
cpu/pc_event.hh
"
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namespace
gem5
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{
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class
IdleStartEvent
:
public
PCEvent
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{
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public
:
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IdleStartEvent
(
PCEventScope
*
s
,
const
std::string &desc,
Addr
addr
)
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:
PCEvent
(
s
, desc,
addr
)
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{}
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virtual
void
process
(
ThreadContext
*tc);
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};
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}
// namespace gem5
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#endif
// __KERN_RISCV_IDLE_EVENT_HH__
gem5::IdleStartEvent
Definition
idle_event.hh:38
gem5::IdleStartEvent::process
virtual void process(ThreadContext *tc)
gem5::IdleStartEvent::IdleStartEvent
IdleStartEvent(PCEventScope *s, const std::string &desc, Addr addr)
Definition
idle_event.hh:40
gem5::PCEventScope
Definition
pc_event.hh:68
gem5::PCEvent
Definition
pc_event.hh:46
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::ArmISA::s
Bitfield< 4 > s
Definition
misc_types.hh:646
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition
types.hh:84
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
pc_event.hh
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