gem5 v24.0.0.0
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pci_host.cc
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1/*
2 * Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
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23 * this software without specific prior written permission.
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36 */
37
38#include "dev/riscv/pci_host.hh"
39#include "params/GenericRiscvPciHost.hh"
40
41namespace gem5
42{
43
44GenericRiscvPciHost::GenericRiscvPciHost(const GenericRiscvPciHostParams &p)
45 : GenericPciHost(p), intBase(p.int_base), intCount(p.int_count)
46{
47}
48
49uint32_t
51 const PciBusAddr &addr, PciIntPin pin) const
52{
54 "%02x:%02x.%i: Interrupt from a device without interrupts\n",
55 addr.bus, addr.dev, addr.func);
56
57 return intBase + (addr.dev % intCount);
58}
59
60}
Configurable generic PCI host interface.
Definition host.hh:277
const uint32_t intCount
Definition pci_host.hh:52
const uint32_t intBase
Definition pci_host.hh:51
uint32_t mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const override
Definition pci_host.cc:50
GenericRiscvPciHost(const GenericRiscvPciHostParams &p)
Definition pci_host.cc:44
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition logging.hh:236
Bitfield< 0 > p
Bitfield< 3 > addr
Definition types.hh:84
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
PciIntPin
Definition types.hh:67

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