gem5
v24.0.0.0
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dev
riscv
pci_host.cc
Go to the documentation of this file.
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/*
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* Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "
dev/riscv/pci_host.hh
"
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#include "params/GenericRiscvPciHost.hh"
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namespace
gem5
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{
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GenericRiscvPciHost::GenericRiscvPciHost
(
const
GenericRiscvPciHostParams &
p
)
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:
GenericPciHost
(
p
), intBase(
p
.int_base), intCount(
p
.int_count)
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{
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}
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uint32_t
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GenericRiscvPciHost::mapPciInterrupt
(
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const
PciBusAddr
&
addr
,
PciIntPin
pin)
const
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{
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fatal_if
(pin ==
PciIntPin::NO_INT
,
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"%02x:%02x.%i: Interrupt from a device without interrupts\n"
,
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addr
.bus,
addr
.dev,
addr
.func);
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return
intBase
+ (
addr
.dev %
intCount
);
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}
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}
gem5::GenericPciHost
Configurable generic PCI host interface.
Definition
host.hh:277
gem5::GenericRiscvPciHost::intCount
const uint32_t intCount
Definition
pci_host.hh:52
gem5::GenericRiscvPciHost::intBase
const uint32_t intBase
Definition
pci_host.hh:51
gem5::GenericRiscvPciHost::mapPciInterrupt
uint32_t mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const override
Definition
pci_host.cc:50
gem5::GenericRiscvPciHost::GenericRiscvPciHost
GenericRiscvPciHost(const GenericRiscvPciHostParams &p)
Definition
pci_host.cc:44
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition
logging.hh:236
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition
types.hh:84
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::PciIntPin
PciIntPin
Definition
types.hh:67
gem5::PciIntPin::NO_INT
@ NO_INT
pci_host.hh
gem5::PciBusAddr
Definition
types.hh:45
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