gem5  v21.1.0.2
host.cc
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37 
38 #include "dev/pci/host.hh"
39 
40 #include <utility>
41 
42 #include "debug/PciHost.hh"
43 #include "dev/pci/device.hh"
44 #include "dev/platform.hh"
45 #include "params/GenericPciHost.hh"
46 #include "params/PciHost.hh"
47 
48 namespace gem5
49 {
50 
51 PciHost::PciHost(const PciHostParams &p)
52  : PioDevice(p)
53 {
54 }
55 
57 {
58 }
59 
62 {
63  auto map_entry = devices.emplace(bus_addr, device);
64 
65  DPRINTF(PciHost, "%02x:%02x.%i: Registering device\n",
66  bus_addr.bus, bus_addr.dev, bus_addr.func);
67 
68  fatal_if(!map_entry.second,
69  "%02x:%02x.%i: PCI bus ID collision\n",
70  bus_addr.bus, bus_addr.dev, bus_addr.func);
71 
72  return DeviceInterface(*this, bus_addr, pin);
73 }
74 
75 PciDevice *
77 {
78  auto device = devices.find(addr);
79  return device != devices.end() ? device->second : nullptr;
80 }
81 
82 const PciDevice *
84 {
85  auto device = devices.find(addr);
86  return device != devices.end() ? device->second : nullptr;
87 }
88 
90  PciHost &_host,
91  PciBusAddr &bus_addr, PciIntPin interrupt_pin)
92  : host(_host),
93  busAddr(bus_addr), interruptPin(interrupt_pin)
94 {
95 }
96 
97 const std::string
99 {
100  return csprintf("%s.interface[%02x:%02x.%i]",
101  host.name(), busAddr.bus, busAddr.dev, busAddr.func);
102 }
103 
104 void
106 {
107  DPRINTF(PciHost, "postInt\n");
108 
109  host.postInt(busAddr, interruptPin);
110 }
111 
112 void
114 {
115  DPRINTF(PciHost, "clearInt\n");
116 
117  host.clearInt(busAddr, interruptPin);
118 }
119 
120 
121 GenericPciHost::GenericPciHost(const GenericPciHostParams &p)
122  : PciHost(p),
123  platform(*p.platform),
124  confBase(p.conf_base), confSize(p.conf_size),
125  confDeviceBits(p.conf_device_bits),
126  pciPioBase(p.pci_pio_base), pciMemBase(p.pci_mem_base),
127  pciDmaBase(p.pci_dma_base)
128 {
129 }
130 
132 {
133 }
134 
135 
136 Tick
138 {
139  const auto dev_addr(decodeAddress(pkt->getAddr() - confBase));
140  const Addr size(pkt->getSize());
141 
142  DPRINTF(PciHost, "%02x:%02x.%i: read: offset=0x%x, size=0x%x\n",
143  dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func,
144  dev_addr.second,
145  size);
146 
147  PciDevice *const pci_dev(getDevice(dev_addr.first));
148  if (pci_dev) {
149  // @todo Remove this after testing
150  pkt->headerDelay = pkt->payloadDelay = 0;
151  return pci_dev->readConfig(pkt);
152  } else {
153  uint8_t *pkt_data(pkt->getPtr<uint8_t>());
154  std::fill(pkt_data, pkt_data + size, 0xFF);
155  pkt->makeAtomicResponse();
156  return 0;
157  }
158 }
159 
160 Tick
162 {
163  const auto dev_addr(decodeAddress(pkt->getAddr() - confBase));
164 
165  DPRINTF(PciHost, "%02x:%02x.%i: write: offset=0x%x, size=0x%x\n",
166  dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func,
167  dev_addr.second,
168  pkt->getSize());
169 
170  PciDevice *const pci_dev(getDevice(dev_addr.first));
171  panic_if(!pci_dev,
172  "%02x:%02x.%i: Write to config space on non-existent PCI device\n",
173  dev_addr.first.bus, dev_addr.first.dev, dev_addr.first.func);
174 
175  // @todo Remove this after testing
176  pkt->headerDelay = pkt->payloadDelay = 0;
177 
178  return pci_dev->writeConfig(pkt);
179 }
180 
183 {
185 }
186 
189 {
190  const Addr offset(addr & mask(confDeviceBits));
191  const Addr bus_addr(addr >> confDeviceBits);
192 
193  return std::make_pair(
194  PciBusAddr(bits(bus_addr, 15, 8),
195  bits(bus_addr, 7, 3),
196  bits(bus_addr, 2, 0)),
197  offset);
198 }
199 
200 
201 void
203 {
204  platform.postPciInt(mapPciInterrupt(addr, pin));
205 }
206 
207 void
209 {
210  platform.clearPciInt(mapPciInterrupt(addr, pin));
211 }
212 
213 
214 uint32_t
216 {
217  const PciDevice *dev(getDevice(addr));
218  assert(dev);
219 
220  return dev->interruptLine();
221 }
222 
223 } // namespace gem5
gem5::GenericPciHost::~GenericPciHost
virtual ~GenericPciHost()
Definition: host.cc:131
gem5::GenericPciHost::postInt
void postInt(const PciBusAddr &addr, PciIntPin pin) override
Post an interrupt to the CPU.
Definition: host.cc:202
gem5::MipsISA::fill
fill
Definition: pra_constants.hh:57
gem5::GenericPciHost::clearInt
void clearInt(const PciBusAddr &addr, PciIntPin pin) override
Post an interrupt to the CPU.
Definition: host.cc:208
gem5::GenericPciHost::decodeAddress
virtual std::pair< PciBusAddr, Addr > decodeAddress(Addr address)
Decode a configuration space address.
Definition: host.cc:188
gem5::PioDevice
This device is the base class which all devices senstive to an address range inherit from.
Definition: io_device.hh:102
gem5::PciHost::PciHost
PciHost(const PciHostParams &p)
Definition: host.cc:51
gem5::RangeSize
AddrRange RangeSize(Addr start, Addr size)
Definition: addr_range.hh:661
gem5::GenericPciHost::confSize
const Addr confSize
Definition: host.hh:323
gem5::AddrRangeList
std::list< AddrRange > AddrRangeList
Convenience typedef for a collection of address ranges.
Definition: addr_range.hh:641
gem5::PciDevice::interruptLine
uint8_t interruptLine() const
Definition: device.hh:367
gem5::PciBusAddr::dev
uint8_t dev
Definition: types.hh:57
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::Packet::makeAtomicResponse
void makeAtomicResponse()
Definition: packet.hh:1043
gem5::Packet::headerDelay
uint32_t headerDelay
The extra delay from seeing the packet until the header is transmitted.
Definition: packet.hh:420
device.hh
gem5::GenericPciHost::confDeviceBits
const uint8_t confDeviceBits
Definition: host.hh:324
gem5::GenericPciHost::GenericPciHost
GenericPciHost(const GenericPciHostParams &p)
Definition: host.cc:121
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::GenericPciHost::platform
Platform & platform
Definition: host.hh:320
gem5::GenericPciHost::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: host.cc:137
gem5::Packet::payloadDelay
uint32_t payloadDelay
The extra pipelining delay from seeing the packet until the end of payload is transmitted by the comp...
Definition: packet.hh:438
gem5::PciDevice::writeConfig
virtual Tick writeConfig(PacketPtr pkt)
Write to the PCI config space data that is stored locally.
Definition: device.cc:283
gem5::GenericPciHost::confBase
const Addr confBase
Definition: host.hh:322
gem5::PciHost
The PCI host describes the interface between PCI devices and a simulated system.
Definition: host.hh:75
gem5::GenericPciHost::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: host.cc:161
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:283
gem5::PciHost::DeviceInterface::clearInt
void clearInt()
Clear a posted PCI interrupt.
Definition: host.cc:113
gem5::PciBusAddr::func
uint8_t func
Definition: types.hh:58
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::PciHost::DeviceInterface
Callback interface from PCI devices to the host.
Definition: host.hh:94
gem5::PciDevice
PCI device, base implementation is only config space.
Definition: device.hh:269
gem5::PciHost::DeviceInterface::postInt
void postInt()
Post a PCI interrupt to the CPU.
Definition: host.cc:105
gem5::ArmISA::offset
Bitfield< 23, 0 > offset
Definition: types.hh:144
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::PciHost::DeviceInterface::name
const std::string name() const
Definition: host.cc:98
std::pair
STL pair class.
Definition: stl.hh:58
gem5::PciBusAddr
Definition: types.hh:44
platform.hh
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::GenericPciHost::getAddrRanges
AddrRangeList getAddrRanges() const override
Every PIO device is obliged to provide an implementation that returns the address ranges the device r...
Definition: host.cc:182
host.hh
gem5::PciBusAddr::bus
uint8_t bus
Definition: types.hh:56
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:203
gem5::PciDevice::readConfig
virtual Tick readConfig(PacketPtr pkt)
Read from the PCI config space data that is stored locally.
Definition: device.cc:212
gem5::PciHost::registerDevice
virtual DeviceInterface registerDevice(PciDevice *device, PciBusAddr bus_addr, PciIntPin pin)
Register a PCI device with the host.
Definition: host.cc:61
gem5::PciHost::devices
std::map< PciBusAddr, PciDevice * > devices
Currently registered PCI devices.
Definition: host.hh:245
gem5::PciHost::DeviceInterface::DeviceInterface
DeviceInterface()=delete
gem5::PciHost::getDevice
PciDevice * getDevice(const PciBusAddr &addr)
Retrieve a PCI device from its bus address.
Definition: host.cc:76
gem5::PciHost::~PciHost
virtual ~PciHost()
Definition: host.cc:56
std::list< AddrRange >
gem5::Packet::getAddr
Addr getAddr() const
Definition: packet.hh:781
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:225
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PciIntPin
PciIntPin
Definition: types.hh:66
gem5::Packet::getSize
unsigned getSize() const
Definition: packet.hh:791
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::GenericPciHost::mapPciInterrupt
virtual uint32_t mapPciInterrupt(const PciBusAddr &bus_addr, PciIntPin pin) const
Definition: host.cc:215
gem5::Packet::getPtr
T * getPtr()
get a pointer to the data ptr.
Definition: packet.hh:1184

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