gem5
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sim
se_workload.hh
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/*
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* Copyright 2020 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SIM_SE_WORKLOAD_HH__
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#define __SIM_SE_WORKLOAD_HH__
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#include "params/SEWorkload.hh"
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#include "
sim/mem_pool.hh
"
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#include "
sim/workload.hh
"
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namespace
gem5
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{
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class
SEWorkload
:
public
Workload
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{
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protected
:
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MemPools
memPools
;
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public
:
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using
Params
= SEWorkloadParams;
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SEWorkload
(
const
Params
&
p
,
Addr
page_shift=0);
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void
setSystem
(
System
*sys)
override
;
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Addr
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getEntry
()
const override
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{
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// This object represents the OS, not the individual processes running
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// within it.
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panic
(
"No workload entry point for syscall emulation mode."
);
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}
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loader::Arch
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getArch
()
const override
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{
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// ISA specific subclasses should implement this method.
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// This implemenetation is just to avoid having to implement those for
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// now, and will be removed in the future.
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panic
(
"SEWorkload::getArch() not implemented."
);
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}
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const
loader::SymbolTable
&
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symtab
(
ThreadContext
*)
override
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{
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// This object represents the OS, not the individual processes running
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// within it.
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panic
(
"No workload symbol table for syscall emulation mode."
);
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}
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bool
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insertSymbol
(
const
loader::Symbol
&symbol)
override
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{
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// This object represents the OS, not the individual processes running
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// within it.
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panic
(
"No workload symbol table for syscall emulation mode."
);
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}
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void
serialize
(
CheckpointOut
&cp)
const override
;
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void
unserialize
(
CheckpointIn
&cp)
override
;
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void
syscall
(
ThreadContext
*tc)
override
;
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// For now, assume the only type of events are system calls.
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void
event
(
ThreadContext
*tc)
override
{
syscall
(tc); }
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Addr
allocPhysPages
(
int
npages,
int
pool_id=0);
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Addr
memSize
(
int
pool_id=0)
const
;
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Addr
freeMemSize
(
int
pool_id=0)
const
;
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};
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}
// namespace gem5
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#endif
// __SIM_SE_WORKLOAD_HH__
gem5::ArmISA::SEWorkload
Definition
se_workload.hh:43
gem5::CheckpointIn
Definition
serialize.hh:69
gem5::MemPools
Definition
mem_pool.hh:87
gem5::SEWorkload::Params
SEWorkloadParams Params
Definition
se_workload.hh:45
gem5::SEWorkload::getEntry
Addr getEntry() const override
Definition
se_workload.hh:52
gem5::SEWorkload::syscall
void syscall(ThreadContext *tc) override
Definition
se_workload.cc:69
gem5::SEWorkload::allocPhysPages
Addr allocPhysPages(int npages, int pool_id=0)
Definition
se_workload.cc:75
gem5::SEWorkload::SEWorkload
SEWorkload(const Params &p, Addr page_shift=0)
gem5::SEWorkload::freeMemSize
Addr freeMemSize(int pool_id=0) const
Definition
se_workload.cc:87
gem5::SEWorkload::memPools
MemPools memPools
Memory allocation objects for all physical memories in the system.
Definition
se_workload.hh:42
gem5::SEWorkload::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition
se_workload.cc:57
gem5::SEWorkload::getArch
loader::Arch getArch() const override
Definition
se_workload.hh:60
gem5::SEWorkload::event
void event(ThreadContext *tc) override
Definition
se_workload.hh:90
gem5::SEWorkload::setSystem
void setSystem(System *sys) override
gem5::SEWorkload::symtab
const loader::SymbolTable & symtab(ThreadContext *) override
Definition
se_workload.hh:69
gem5::SEWorkload::memSize
Addr memSize(int pool_id=0) const
Definition
se_workload.cc:81
gem5::SEWorkload::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition
se_workload.cc:63
gem5::SEWorkload::insertSymbol
bool insertSymbol(const loader::Symbol &symbol) override
Definition
se_workload.hh:77
gem5::System
Definition
system.hh:75
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::Workload
Definition
workload.hh:51
gem5::loader::SymbolTable
Definition
symtab.hh:152
gem5::loader::Symbol
Definition
symtab.hh:63
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition
logging.hh:188
mem_pool.hh
gem5::MipsISA::p
Bitfield< 0 > p
Definition
pra_constants.hh:326
gem5::loader::Arch
Arch
Definition
object_file.hh:62
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::CheckpointOut
std::ostream CheckpointOut
Definition
serialize.hh:66
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition
types.hh:147
workload.hh
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