gem5 v24.0.0.0
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simple_mem.hh
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1/*
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14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
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40
46#ifndef __MEM_SIMPLE_MEMORY_HH__
47#define __MEM_SIMPLE_MEMORY_HH__
48
49#include <list>
50
51#include "mem/abstract_mem.hh"
52#include "mem/port.hh"
53#include "params/SimpleMemory.hh"
54
55namespace gem5
56{
57
58namespace memory
59{
60
68{
69
70 private:
71
77 {
78
79 public:
80
81 const Tick tick;
83
84 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
85 { }
86 };
87
88 class MemoryPort : public ResponsePort
89 {
90 private:
92
93 public:
94 MemoryPort(const std::string& _name, SimpleMemory& _memory);
95
96 protected:
97 Tick recvAtomic(PacketPtr pkt) override;
99 PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
100 void recvFunctional(PacketPtr pkt) override;
101 void recvMemBackdoorReq(const MemBackdoorReq &req,
102 MemBackdoorPtr &backdoor) override;
103 bool recvTimingReq(PacketPtr pkt) override;
104 void recvRespRetry() override;
105 AddrRangeList getAddrRanges() const override;
106 };
107
109
115
120
127
133 const double bandwidth;
134
139 bool isBusy;
140
146
152
157 void release();
158
160
165 void dequeue();
166
168
174 Tick getLatency() const;
175
180 std::unique_ptr<Packet> pendingDelete;
181
182 public:
183
184 SimpleMemory(const SimpleMemoryParams &p);
185
186 DrainState drain() override;
187
188 Port &getPort(const std::string &if_name,
189 PortID idx=InvalidPortID) override;
190 void init() override;
191
192 protected:
195 void recvFunctional(PacketPtr pkt);
196 void recvMemBackdoorReq(const MemBackdoorReq &req,
198 bool recvTimingReq(PacketPtr pkt);
199 void recvRespRetry();
200};
201
202} // namespace memory
203} // namespace gem5
204
205#endif //__MEM_SIMPLE_MEMORY_HH__
AbstractMemory declaration.
const std::string _name
Definition named.hh:41
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition packet.hh:295
Ports are used to interface objects to each other.
Definition port.hh:62
A ResponsePort is a specialization of a port.
Definition port.hh:349
An abstract memory represents a contiguous block of physical memory, with an associated address range...
A deferred packet stores a packet along with its scheduled transmission time.
Definition simple_mem.hh:77
DeferredPacket(PacketPtr _pkt, Tick _tick)
Definition simple_mem.hh:84
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor) override
Receive a request for a back door to a range of memory.
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
void recvRespRetry() override
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
MemoryPort(const std::string &_name, SimpleMemory &_memory)
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
The simple memory is a basic single-ported memory controller with a configurable throughput and laten...
Definition simple_mem.hh:68
void recvFunctional(PacketPtr pkt)
Definition simple_mem.cc:94
void dequeue()
Dequeue a packet from our internal packet queue and move it to the port where it will be sent as soon...
void release()
Release the memory after being busy and send a retry if a request was rejected in the meanwhile.
const Tick latency
Latency from that a request is accepted until the response is ready to be sent.
std::list< DeferredPacket > packetQueue
Internal (unbounded) storage to mimic the delay caused by the actual memory access.
bool retryResp
Remember if we failed to send a response and are awaiting a retry.
Tick getLatency() const
Detemine the latency.
EventFunctionWrapper dequeueEvent
bool retryReq
Remember if we have to retry an outstanding request that arrived while we were busy.
SimpleMemory(const SimpleMemoryParams &p)
Definition simple_mem.cc:53
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
Definition simple_mem.cc:86
const double bandwidth
Bandwidth in ticks per byte.
bool recvTimingReq(PacketPtr pkt)
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Tick recvAtomic(PacketPtr pkt)
Definition simple_mem.cc:76
DrainState drain() override
Provide a default implementation of the drain interface for objects that don't need draining.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition simple_mem.cc:64
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor)
EventFunctionWrapper releaseEvent
bool isBusy
Track the state of the memory as either idle or busy, no need for an enum with only two states.
const Tick latency_var
Fudge factor added to the latency.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
DrainState
Object drain/handover states.
Definition drain.hh:75
Port Object Declaration.
Bitfield< 0 > p
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
const PortID InvalidPortID
Definition types.hh:246
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition types.hh:245
uint64_t Tick
Tick count type.
Definition types.hh:58
Definition mem.h:38

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