46#ifndef __MEM_SIMPLE_MEMORY_HH__
47#define __MEM_SIMPLE_MEMORY_HH__
53#include "params/SimpleMemory.hh"
190 void init()
override;
AbstractMemory declaration.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Ports are used to interface objects to each other.
A ResponsePort is a specialization of a port.
An abstract memory represents a contiguous block of physical memory, with an associated address range...
A deferred packet stores a packet along with its scheduled transmission time.
DeferredPacket(PacketPtr _pkt, Tick _tick)
Tick recvAtomic(PacketPtr pkt) override
Receive an atomic request packet from the peer.
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor) override
Receive a request for a back door to a range of memory.
AddrRangeList getAddrRanges() const override
Get a list of the non-overlapping address ranges the owner is responsible for.
bool recvTimingReq(PacketPtr pkt) override
Receive a timing request from the peer.
void recvRespRetry() override
Called by the peer if sendTimingResp was called on this protocol (causing recvTimingResp to be called...
MemoryPort(const std::string &_name, SimpleMemory &_memory)
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor) override
Receive an atomic request packet from the peer, and optionally provide a backdoor to the data being a...
void recvFunctional(PacketPtr pkt) override
Receive a functional request packet from the peer.
The simple memory is a basic single-ported memory controller with a configurable throughput and laten...
void recvFunctional(PacketPtr pkt)
void dequeue()
Dequeue a packet from our internal packet queue and move it to the port where it will be sent as soon...
void release()
Release the memory after being busy and send a retry if a request was rejected in the meanwhile.
const Tick latency
Latency from that a request is accepted until the response is ready to be sent.
std::list< DeferredPacket > packetQueue
Internal (unbounded) storage to mimic the delay caused by the actual memory access.
bool retryResp
Remember if we failed to send a response and are awaiting a retry.
Tick getLatency() const
Detemine the latency.
EventFunctionWrapper dequeueEvent
bool retryReq
Remember if we have to retry an outstanding request that arrived while we were busy.
SimpleMemory(const SimpleMemoryParams &p)
Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor)
const double bandwidth
Bandwidth in ticks per byte.
bool recvTimingReq(PacketPtr pkt)
std::unique_ptr< Packet > pendingDelete
Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent c...
Tick recvAtomic(PacketPtr pkt)
DrainState drain() override
Provide a default implementation of the drain interface for objects that don't need draining.
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
void recvMemBackdoorReq(const MemBackdoorReq &req, MemBackdoorPtr &backdoor)
EventFunctionWrapper releaseEvent
bool isBusy
Track the state of the memory as either idle or busy, no need for an enum with only two states.
const Tick latency_var
Fudge factor added to the latency.
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
DrainState
Object drain/handover states.
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
const PortID InvalidPortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
uint64_t Tick
Tick count type.