gem5  v21.2.1.1
pagetable.hh
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28 
29 #ifndef __ARCH_SPARC_PAGETABLE_HH__
30 #define __ARCH_SPARC_PAGETABLE_HH__
31 
32 #include <cassert>
33 
34 #include "base/bitfield.hh"
35 #include "base/logging.hh"
36 #include "base/types.hh"
37 #include "sim/serialize.hh"
38 
39 namespace gem5
40 {
41 
42 namespace SparcISA
43 {
44 
45 class TteTag
46 {
47  private:
48  uint64_t entry;
49  bool populated;
50 
51  public:
52  TteTag() : entry(0), populated(false) {}
53  TteTag(uint64_t e) : entry(e), populated(true) {}
54 
55  const TteTag &
56  operator=(uint64_t e)
57  {
58  populated = true;
59  entry = e;
60  return *this;
61  }
62 
63  bool valid() const { assert(populated); return !bits(entry,62,62); }
64  Addr va() const { assert(populated); return bits(entry,41,0); }
65 };
66 
67 
69 {
70  public:
71  enum EntryType
72  {
76  };
77 
78  private:
79  uint64_t entry;
81  uint64_t entry4u;
82  bool populated;
83 
84  public:
86  {}
87 
89  : entry(e), type(t), populated(true)
90  {
92  }
93 
94  void
95  populate(uint64_t e, EntryType t = sun4u)
96  {
97  entry = e;
98  type = t;
99  populated = true;
100 
101  // If we get a sun4v format TTE, turn it into a sun4u
102  if (type == sun4u)
103  entry4u = entry;
104  else {
105  entry4u = 0;
106  entry4u |= mbits(entry,63,63); // valid
107  entry4u |= bits(entry,1,0) << 61; // size[1:0]
108  entry4u |= bits(entry,62,62) << 60; // nfo
109  entry4u |= bits(entry,12,12) << 59; // ie
110  entry4u |= bits(entry,2,2) << 48; // size[2]
111  entry4u |= mbits(entry,39,13); // paddr
112  entry4u |= bits(entry,61,61) << 6;; // locked
113  entry4u |= bits(entry,10,10) << 5; // cp
114  entry4u |= bits(entry,9,9) << 4; // cv
115  entry4u |= bits(entry,11,11) << 3; // e
116  entry4u |= bits(entry,8,8) << 2; // p
117  entry4u |= bits(entry,6,6) << 1; // w
118  }
119  }
120 
121  void
123  {
124  populated = false;
125  }
126 
127  static int pageSizes[6];
128 
129  uint64_t operator()() const { assert(populated); return entry4u; }
130 
131  const PageTableEntry &
132  operator=(uint64_t e)
133  {
134  populated = true;
135  entry4u = e;
136  return *this;
137  }
138 
139  const PageTableEntry &
141  {
142  populated = true;
143  entry4u = e.entry4u;
144  type = e.type;
145  return *this;
146  }
147 
148  bool valid() const { return bits(entry4u,63,63) && populated; }
149 
150  uint8_t
151  _size() const
152  {
153  assert(populated);
154  return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
155  }
156 
157  Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
158  Addr sizeMask() const { return size() - 1; }
159  bool ie() const { return bits(entry4u, 59,59); }
160  Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
161  Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
162  bool locked() const { assert(populated); return bits(entry4u,6,6); }
163  bool cv() const { assert(populated); return bits(entry4u,4,4); }
164  bool cp() const { assert(populated); return bits(entry4u,5,5); }
165  bool priv() const { assert(populated); return bits(entry4u,2,2); }
166  bool writable() const { assert(populated); return bits(entry4u,1,1); }
167  bool nofault() const { assert(populated); return bits(entry4u,60,60); }
168  bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
169  Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
170 
171  Addr
173  {
174  assert(populated);
175  Addr mask = sizeMask();
176  return (paddr() & ~mask) | (vaddr & mask);
177  }
178 };
179 
180 struct TlbRange
181 {
186  bool real;
187 
188  inline bool
189  operator<(const TlbRange &r2) const
190  {
191  if (real && !r2.real)
192  return true;
193  if (!real && r2.real)
194  return false;
195 
196  if (!real && !r2.real) {
197  if (contextId < r2.contextId)
198  return true;
199  else if (contextId > r2.contextId)
200  return false;
201  }
202 
203  if (partitionId < r2.partitionId)
204  return true;
205  else if (partitionId > r2.partitionId)
206  return false;
207 
208  if (va < r2.va)
209  return true;
210  return false;
211  }
212 
213  inline bool
214  operator==(const TlbRange &r2) const
215  {
216  return va == r2.va &&
217  size == r2.size &&
218  contextId == r2.contextId &&
219  partitionId == r2.partitionId &&
220  real == r2.real;
221  }
222 };
223 
224 
225 struct TlbEntry
226 {
228  {}
229 
230  TlbEntry(Addr asn, Addr vaddr, Addr paddr,
231  bool uncacheable, bool read_only)
232  {
233  uint64_t entry = 0;
234  if (!read_only)
235  entry |= 1ULL << 1; // Writable
236  entry |= 0ULL << 2; // Available in nonpriveleged mode
237  entry |= 0ULL << 3; // No side effects
238  if (!uncacheable) {
239  entry |= 1ULL << 4; // Virtually cachable
240  entry |= 1ULL << 5; // Physically cachable
241  }
242  entry |= 0ULL << 6; // Not locked
243  entry |= mbits(paddr, 39, 13); // Physical address
244  entry |= 0ULL << 48; // size = 8k
245  entry |= 0uLL << 59; // Endianness not inverted
246  entry |= 0ULL << 60; // Not no fault only
247  entry |= 0ULL << 61; // size = 8k
248  entry |= 1ULL << 63; // valid
249  pte = PageTableEntry(entry);
250 
251  range.va = vaddr;
252  range.size = 8*(1<<10);
253  range.contextId = asn;
254  range.partitionId = 0;
255  range.real = false;
256 
257  valid = true;
258  }
259 
262  bool used;
263  bool valid;
264 
265  Addr
267  {
268  return pte.paddr();
269  }
270 
271  void
272  updateVaddr(Addr new_vaddr)
273  {
274  range.va = new_vaddr;
275  }
276 
277  void serialize(CheckpointOut &cp) const;
278  void unserialize(CheckpointIn &cp);
279 };
280 
281 } // namespace SparcISA
282 } // namespace gem5
283 
284 #endif // __ARCH_SPARC_PAGE_TABLE_HH__
gem5::SparcISA::TlbEntry::pageStart
Addr pageStart()
Definition: pagetable.hh:266
gem5::SparcISA::PageTableEntry::invalid
@ invalid
Definition: pagetable.hh:75
gem5::SparcISA::PageTableEntry::ie
bool ie() const
Definition: pagetable.hh:159
gem5::SparcISA::PageTableEntry::sun4u
@ sun4u
Definition: pagetable.hh:74
gem5::SparcISA::PageTableEntry::cp
bool cp() const
Definition: pagetable.hh:164
gem5::SparcISA::TlbEntry::range
TlbRange range
Definition: pagetable.hh:260
gem5::SparcISA::TteTag::populated
bool populated
Definition: pagetable.hh:49
gem5::SparcISA::TteTag::va
Addr va() const
Definition: pagetable.hh:64
gem5::SparcISA::TlbEntry::serialize
void serialize(CheckpointOut &cp) const
Definition: pagetable.cc:40
serialize.hh
gem5::SparcISA::PageTableEntry::PageTableEntry
PageTableEntry(uint64_t e, EntryType t=sun4u)
Definition: pagetable.hh:88
gem5::SparcISA::PageTableEntry::pageSizes
static int pageSizes[6]
Definition: pagetable.hh:127
gem5::SparcISA::PageTableEntry::sizeMask
Addr sizeMask() const
Definition: pagetable.hh:158
gem5::SparcISA::PageTableEntry::type
EntryType type
Definition: pagetable.hh:80
gem5::SparcISA::PageTableEntry::populated
bool populated
Definition: pagetable.hh:82
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::SparcISA::PageTableEntry::priv
bool priv() const
Definition: pagetable.hh:165
gem5::ArmISA::e
Bitfield< 9 > e
Definition: misc_types.hh:65
gem5::SparcISA::PageTableEntry::operator()
uint64_t operator()() const
Definition: pagetable.hh:129
gem5::mbits
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition: bitfield.hh:103
gem5::SparcISA::TlbRange::real
bool real
Definition: pagetable.hh:186
gem5::SparcISA::PageTableEntry::writable
bool writable() const
Definition: pagetable.hh:166
gem5::SparcISA::PageTableEntry::sun4v
@ sun4v
Definition: pagetable.hh:73
gem5::SparcISA::TteTag
Definition: pagetable.hh:45
gem5::mask
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
Definition: bitfield.hh:63
gem5::SparcISA::TlbEntry::unserialize
void unserialize(CheckpointIn &cp)
Definition: pagetable.cc:57
gem5::SparcISA::TlbRange::va
Addr va
Definition: pagetable.hh:182
gem5::SparcISA::TlbRange
Definition: pagetable.hh:180
gem5::SparcISA::PageTableEntry::PageTableEntry
PageTableEntry()
Definition: pagetable.hh:85
gem5::SparcISA::TlbEntry::TlbEntry
TlbEntry()
Definition: pagetable.hh:227
gem5::SparcISA::TlbRange::size
Addr size
Definition: pagetable.hh:183
bitfield.hh
gem5::SparcISA::TlbRange::partitionId
int partitionId
Definition: pagetable.hh:185
gem5::SparcISA::PageTableEntry::size
Addr size() const
Definition: pagetable.hh:157
gem5::SparcISA::PageTableEntry::operator=
const PageTableEntry & operator=(const PageTableEntry &e)
Definition: pagetable.hh:140
gem5::SparcISA::TlbEntry::updateVaddr
void updateVaddr(Addr new_vaddr)
Definition: pagetable.hh:272
gem5::SparcISA::PageTableEntry::populate
void populate(uint64_t e, EntryType t=sun4u)
Definition: pagetable.hh:95
gem5::SparcISA::PageTableEntry
Definition: pagetable.hh:68
gem5::SparcISA::TlbRange::contextId
int contextId
Definition: pagetable.hh:184
gem5::SparcISA::PageTableEntry::pfn
Addr pfn() const
Definition: pagetable.hh:160
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:71
gem5::SparcISA::TteTag::TteTag
TteTag()
Definition: pagetable.hh:52
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::SparcISA::TteTag::entry
uint64_t entry
Definition: pagetable.hh:48
gem5::SparcISA::PageTableEntry::paddrMask
Addr paddrMask() const
Definition: pagetable.hh:169
gem5::SparcISA::TteTag::operator=
const TteTag & operator=(uint64_t e)
Definition: pagetable.hh:56
gem5::SparcISA::PageTableEntry::operator=
const PageTableEntry & operator=(uint64_t e)
Definition: pagetable.hh:132
gem5::SparcISA::PageTableEntry::EntryType
EntryType
Definition: pagetable.hh:71
gem5::SparcISA::TlbEntry::TlbEntry
TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only)
Definition: pagetable.hh:230
gem5::SparcISA::PageTableEntry::translate
Addr translate(Addr vaddr) const
Definition: pagetable.hh:172
gem5::SparcISA::PageTableEntry::sideffect
bool sideffect() const
Definition: pagetable.hh:168
gem5::SparcISA::PageTableEntry::paddr
Addr paddr() const
Definition: pagetable.hh:161
types.hh
gem5::SparcISA::PageTableEntry::nofault
bool nofault() const
Definition: pagetable.hh:167
gem5::SparcISA::PageTableEntry::cv
bool cv() const
Definition: pagetable.hh:163
gem5::SparcISA::TteTag::valid
bool valid() const
Definition: pagetable.hh:63
logging.hh
gem5::SparcISA::PageTableEntry::clear
void clear()
Definition: pagetable.hh:122
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::SparcISA::TlbRange::operator==
bool operator==(const TlbRange &r2) const
Definition: pagetable.hh:214
gem5::SparcISA::PageTableEntry::valid
bool valid() const
Definition: pagetable.hh:148
gem5::SparcISA::PageTableEntry::_size
uint8_t _size() const
Definition: pagetable.hh:151
gem5::SparcISA::TlbEntry::pte
PageTableEntry pte
Definition: pagetable.hh:261
gem5::SparcISA::TlbEntry::used
bool used
Definition: pagetable.hh:262
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: tlb.cc:60
gem5::SparcISA::PageTableEntry::locked
bool locked() const
Definition: pagetable.hh:162
gem5::SparcISA::PageTableEntry::entry4u
uint64_t entry4u
Definition: pagetable.hh:81
gem5::SparcISA::PageTableEntry::entry
uint64_t entry
Definition: pagetable.hh:79
gem5::SparcISA::TlbEntry::valid
bool valid
Definition: pagetable.hh:263
gem5::SparcISA::TlbEntry
Definition: pagetable.hh:225
gem5::SparcISA::TlbRange::operator<
bool operator<(const TlbRange &r2) const
Definition: pagetable.hh:189
gem5::SparcISA::TteTag::TteTag
TteTag(uint64_t e)
Definition: pagetable.hh:53

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