gem5 v24.0.0.0
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pagetable.hh
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1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_SPARC_PAGETABLE_HH__
30#define __ARCH_SPARC_PAGETABLE_HH__
31
32#include <cassert>
33
34#include "base/bitfield.hh"
35#include "base/logging.hh"
36#include "base/types.hh"
37#include "sim/serialize.hh"
38
39namespace gem5
40{
41
42namespace SparcISA
43{
44
45class TteTag
46{
47 private:
48 uint64_t entry;
50
51 public:
52 TteTag() : entry(0), populated(false) {}
53 TteTag(uint64_t e) : entry(e), populated(true) {}
54
55 const TteTag &
56 operator=(uint64_t e)
57 {
58 populated = true;
59 entry = e;
60 return *this;
61 }
62
63 bool valid() const { assert(populated); return !bits(entry,62,62); }
64 Addr va() const { assert(populated); return bits(entry,41,0); }
65};
66
67
69{
70 public:
77
78 private:
79 uint64_t entry;
81 uint64_t entry4u;
83
84 public:
86 {}
87
89 : entry(e), type(t), populated(true)
90 {
92 }
93
94 void
95 populate(uint64_t e, EntryType t = sun4u)
96 {
97 entry = e;
98 type = t;
99 populated = true;
100
101 // If we get a sun4v format TTE, turn it into a sun4u
102 if (type == sun4u)
103 entry4u = entry;
104 else {
105 entry4u = 0;
106 entry4u |= mbits(entry,63,63); // valid
107 entry4u |= bits(entry,1,0) << 61; // size[1:0]
108 entry4u |= bits(entry,62,62) << 60; // nfo
109 entry4u |= bits(entry,12,12) << 59; // ie
110 entry4u |= bits(entry,2,2) << 48; // size[2]
111 entry4u |= mbits(entry,39,13); // paddr
112 entry4u |= bits(entry,61,61) << 6;; // locked
113 entry4u |= bits(entry,10,10) << 5; // cp
114 entry4u |= bits(entry,9,9) << 4; // cv
115 entry4u |= bits(entry,11,11) << 3; // e
116 entry4u |= bits(entry,8,8) << 2; // p
117 entry4u |= bits(entry,6,6) << 1; // w
118 }
119 }
120
121 void
123 {
124 populated = false;
125 }
126
127 static int pageSizes[6];
128
129 uint64_t operator()() const { assert(populated); return entry4u; }
130
131 const PageTableEntry &
132 operator=(uint64_t e)
133 {
134 populated = true;
135 entry4u = e;
136 return *this;
137 }
138
139 const PageTableEntry &
141 {
142 populated = true;
143 entry4u = e.entry4u;
144 type = e.type;
145 return *this;
146 }
147
148 bool valid() const { return bits(entry4u,63,63) && populated; }
149
150 uint8_t
151 _size() const
152 {
153 assert(populated);
154 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
155 }
156
157 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
158 Addr sizeMask() const { return size() - 1; }
159 bool ie() const { return bits(entry4u, 59,59); }
160 Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
161 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
162 bool locked() const { assert(populated); return bits(entry4u,6,6); }
163 bool cv() const { assert(populated); return bits(entry4u,4,4); }
164 bool cp() const { assert(populated); return bits(entry4u,5,5); }
165 bool priv() const { assert(populated); return bits(entry4u,2,2); }
166 bool writable() const { assert(populated); return bits(entry4u,1,1); }
167 bool nofault() const { assert(populated); return bits(entry4u,60,60); }
168 bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
169 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
170
171 Addr
173 {
174 assert(populated);
175 Addr mask = sizeMask();
176 return (paddr() & ~mask) | (vaddr & mask);
177 }
178};
179
181{
186 bool real;
187
188 inline bool
189 operator<(const TlbRange &r2) const
190 {
191 if (real && !r2.real)
192 return true;
193 if (!real && r2.real)
194 return false;
195
196 if (!real && !r2.real) {
197 if (contextId < r2.contextId)
198 return true;
199 else if (contextId > r2.contextId)
200 return false;
201 }
202
203 if (partitionId < r2.partitionId)
204 return true;
205 else if (partitionId > r2.partitionId)
206 return false;
207
208 if (va < r2.va)
209 return true;
210 return false;
211 }
212
213 inline bool
214 operator==(const TlbRange &r2) const
215 {
216 return va == r2.va &&
217 size == r2.size &&
218 contextId == r2.contextId &&
219 partitionId == r2.partitionId &&
220 real == r2.real;
221 }
222};
223
224
226{
228 {}
229
231 bool uncacheable, bool read_only)
232 {
233 uint64_t entry = 0;
234 if (!read_only)
235 entry |= 1ULL << 1; // Writable
236 entry |= 0ULL << 2; // Available in nonpriveleged mode
237 entry |= 0ULL << 3; // No side effects
238 if (!uncacheable) {
239 entry |= 1ULL << 4; // Virtually cachable
240 entry |= 1ULL << 5; // Physically cachable
241 }
242 entry |= 0ULL << 6; // Not locked
243 entry |= mbits(paddr, 39, 13); // Physical address
244 entry |= 0ULL << 48; // size = 8k
245 entry |= 0uLL << 59; // Endianness not inverted
246 entry |= 0ULL << 60; // Not no fault only
247 entry |= 0ULL << 61; // size = 8k
248 entry |= 1ULL << 63; // valid
249 pte = PageTableEntry(entry);
250
251 range.va = vaddr;
252 range.size = 8*(1<<10);
253 range.contextId = asn;
254 range.partitionId = 0;
255 range.real = false;
256
257 valid = true;
258 }
259
262 bool used;
263 bool valid;
264
265 Addr
267 {
268 return pte.paddr();
269 }
270
271 void
272 updateVaddr(Addr new_vaddr)
273 {
274 range.va = new_vaddr;
275 }
276
277 void serialize(CheckpointOut &cp) const;
278 void unserialize(CheckpointIn &cp);
279};
280
281} // namespace SparcISA
282} // namespace gem5
283
284#endif // __ARCH_SPARC_PAGE_TABLE_HH__
Defines global host-dependent types: Counter, Tick, and (indirectly) {int,uint}{8,...
Addr translate(Addr vaddr) const
Definition pagetable.hh:172
const PageTableEntry & operator=(const PageTableEntry &e)
Definition pagetable.hh:140
void populate(uint64_t e, EntryType t=sun4u)
Definition pagetable.hh:95
PageTableEntry(uint64_t e, EntryType t=sun4u)
Definition pagetable.hh:88
const PageTableEntry & operator=(uint64_t e)
Definition pagetable.hh:132
const TteTag & operator=(uint64_t e)
Definition pagetable.hh:56
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition bitfield.hh:79
constexpr T mbits(T val, unsigned first, unsigned last)
Mask off the given bits in place like bits() but without shifting.
Definition bitfield.hh:106
Bitfield< 3, 0 > mask
Definition pcstate.hh:63
Bitfield< 5 > t
Definition misc_types.hh:71
Bitfield< 9 > e
Definition misc_types.hh:65
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition types.hh:147
void unserialize(CheckpointIn &cp)
Definition pagetable.cc:57
void updateVaddr(Addr new_vaddr)
Definition pagetable.hh:272
TlbEntry(Addr asn, Addr vaddr, Addr paddr, bool uncacheable, bool read_only)
Definition pagetable.hh:230
void serialize(CheckpointOut &cp) const
Definition pagetable.cc:40
bool operator==(const TlbRange &r2) const
Definition pagetable.hh:214
bool operator<(const TlbRange &r2) const
Definition pagetable.hh:189

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