gem5 v24.0.0.0
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rdy.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20/*****************************************************************************
21
22 rdy.h --
23
24 Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25
26 *****************************************************************************/
27
28/*****************************************************************************
29
30 MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31 changes you are making here.
32
33 Name, Affiliation, Date:
34 Description of Modification:
35
36 *****************************************************************************/
37
38#include "systemc.h"
39
40/******************************************************************************/
41/*************************** rdy Function **********************/
42/******************************************************************************/
43
44SC_MODULE( RDY )
45{
46 SC_HAS_PROCESS( RDY );
47
48 sc_in_clk clk;
49
50 /*** Input and Output Ports ***/
51 sc_signal<bool>& data;
52
53 /*** Constructor ***/
54 RDY ( sc_module_name NAME,
55 sc_clock& TICK_N,
56 sc_signal<bool>& DATA )
57
58 :
59 data (DATA)
60
61 {
62 clk (TICK_N);
63 SC_CTHREAD( entry, clk.neg() );
64 }
65
66 /*** Call to Process Functionality ***/
67 void entry();
68
69};
70
71void
72RDY::entry()
73{
74 // int a;
75 int a = 0;
76
77 cout << "\nSTART OF SIM -- CLOCK AT NEGEDGE (10,30,50,...) " << endl;
78 cout << sc_time_stamp() << " : "
79 << " ready[S] = " << data
80 << " a[V] = " << a
81 << endl;
82
83 a = 0; cout << "\t\t\t a = 0 " << endl;
84 cout << sc_time_stamp() << " : "
85 << " ready[S] = " << data
86 << " a[V] = " << a
87 << endl;
88 data.write(0); cout << " ready = 0 " << endl;
89 cout << sc_time_stamp() << " : "
90 << " ready[S] = " << data
91 << " a[V] = " << a
92 << endl;
93 wait(); cout << "\nCLK " << endl;
94 cout << sc_time_stamp() << " : "
95 << " ready[S] = " << data
96 << " a[V] = " << a
97 << endl;
98
99 a = 1; cout << "\t\t a = 1 " << endl;
100 cout << sc_time_stamp() << " : "
101 << " ready[S] = " << data
102 << " a[V] = " << a
103 << endl;
104 data.write(1); cout << " ready = 1 " << endl;
105 cout << sc_time_stamp() << " : "
106 << " ready[S] = " << data
107 << " a[V] = " << a
108 << endl;
109 wait(); cout << "\nCLK " << endl;
110 cout << sc_time_stamp() << " : "
111 << " ready[S] = " << data
112 << " a[V] = " << a
113 << endl;
114
115 a = 0; cout << "\t\t a = 0 " << endl;
116 cout << sc_time_stamp() << " : "
117 << " ready[S] = " << data
118 << " a[V] = " << a
119 << endl;
120 data.write(0); cout << " ready = 0 " << endl;
121 cout << sc_time_stamp() << " : "
122 << " ready[S] = " << data
123 << " a[V] = " << a
124 << endl;
125 wait(); cout << "\nCLK " << endl;
126 cout << sc_time_stamp() << " : "
127 << " ready[S] = " << data
128 << " a[V] = " << a
129 << endl;
130
131 a = 1; cout << "\t\t a = 1 " << endl;
132 cout << sc_time_stamp() << " : "
133 << " ready[S] = " << data
134 << " a[V] = " << a
135 << endl;
136 data.write(1); cout << " ready = 1 " << endl;
137 cout << sc_time_stamp() << " : "
138 << " ready[S] = " << data
139 << " a[V] = " << a
140 << endl;
141 wait(); cout << "\nCLK " << endl;
142 cout << sc_time_stamp() << " : "
143 << " ready[S] = " << data
144 << " a[V] = " << a
145 << endl;
146
147 halt();
148}
data
const char data[]
Definition circlebuf.test.cc:48
a
SwitchingFiber a
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition sc_module.hh:323
SC_MODULE
#define SC_MODULE(name)
Definition sc_module.hh:295
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition sc_module.hh:301
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