51 sc_signal<bool>&
data;
54 RDY ( sc_module_name NAME,
56 sc_signal<bool>& DATA )
77 cout <<
"\nSTART OF SIM -- CLOCK AT NEGEDGE (10,30,50,...) " << endl;
79 <<
" ready[S] = " <<
data
83 a = 0; cout <<
"\t\t\t a = 0 " << endl;
85 <<
" ready[S] = " <<
data
88 data.write(0); cout <<
" ready = 0 " << endl;
90 <<
" ready[S] = " <<
data
93 wait(); cout <<
"\nCLK " << endl;
95 <<
" ready[S] = " <<
data
99 a = 1; cout <<
"\t\t a = 1 " << endl;
101 <<
" ready[S] = " <<
data
104 data.write(1); cout <<
" ready = 1 " << endl;
106 <<
" ready[S] = " <<
data
109 wait(); cout <<
"\nCLK " << endl;
111 <<
" ready[S] = " <<
data
115 a = 0; cout <<
"\t\t a = 0 " << endl;
117 <<
" ready[S] = " <<
data
120 data.write(0); cout <<
" ready = 0 " << endl;
122 <<
" ready[S] = " <<
data
125 wait(); cout <<
"\nCLK " << endl;
127 <<
" ready[S] = " <<
data
131 a = 1; cout <<
"\t\t a = 1 " << endl;
133 <<
" ready[S] = " <<
data
136 data.write(1); cout <<
" ready = 1 " << endl;
138 <<
" ready[S] = " <<
data
141 wait(); cout <<
"\nCLK " << endl;
143 <<
" ready[S] = " <<
data
const sc_time & sc_time_stamp()
#define SC_CTHREAD(name, clk)
#define SC_HAS_PROCESS(name)