- r -

• radvProcess() : IGbE
• raise() : ArmInterruptPin , ArmPPI , ArmSPI , IntSinkPinBase , IntSourcePinBase
• raiseInterrupt() : ArmISA::PMU
• raiseInterruptPin() : X86ISA::I82094AA , X86ISA::I8259
• raiseInterrupts() : Pl011
• raiseOnDevice() : IntSinkPin< Device > , IntSinkPinBase
• rand() : QTIsaac< ALPHA >
• randctx() : QTIsaac< ALPHA >::randctx
• randinit() : QTIsaac< ALPHA >
• Random() : Random
• random() : Random
• RandomGen() : RandomGen
• randomPick() : RandomStreamGen
• randomPriority() : MinorCPU
• RandomReplData() : RandomRP::RandomReplData
• RandomRP() : RandomRP
• RandomStreamGen() : RandomStreamGen
• range() : MemBackdoor , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_dt::sc_fxnum , sc_dt::sc_fxnum_fast , sc_dt::sc_int_base , sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_uint_base , sc_dt::sc_unsigned
• RangeAddrMapper() : RangeAddrMapper
• Rank() : DRAMCtrl::Rank
• rankParam() : DistIface
• RankStats() : DRAMCtrl::RankStats
• rao() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer
• raw_ptr() : VecRegContainer< Sz >
• RawDiskImage() : RawDiskImage
• RawImage() : RawImage
• raz() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer
• rdtrProcess() : IGbE
• rdy() : WaitClass
• read() : A9GlobalTimer , A9GlobalTimer::Timer , A9SCU , AlphaBackdoor , AmbaFake , ArmSemihosting::File , ArmSemihosting::FileBase , ArmSemihosting::FileFeatures , BadDevice , BaseRemoteGDB , CircleBuf< T > , ConditionRegisterState , CopyEngine::CopyEngineChannel , CopyEngine , CowDiskImage , CpuLocalTimer , CpuLocalTimer::Timer , DiskImage , DumbTOD , EnergyCtrl , FastModel::GIC , Fifo< T > , FullO3CPU< Impl > , GenericPciHost , GenericTimerMem , GicV2 , Gicv2m , Gicv3 , Gicv3Distributor , Gicv3Its , Gicv3Redistributor , GpuDispatcher , HDLcd , I2CBus , I2CDevice , IdeController , IGbE , Intel8254Timer::Counter , Iob , IsaFake , LdsChunk , LSQ< Impl > , LSQUnit< Impl > , MaltaCChip , MaltaIO , MmDisk , MmioVirtIO , MuxingKvmGic , NoMaliGpu , NSGigE , PciVirtIO , PerfKvmCounter , PioDevice , Pl011 , PL031 , Pl050 , Pl111 , PortProxy , ProtoInputStream , RawDiskImage , RealViewCtrl::Device , RealViewCtrl , RealViewOsc , RealViewTemperatureSensor , sc_core::sc_fifo< T > , sc_core::sc_fifo_blocking_in_if< T > , sc_core::sc_fifo_in< T > , sc_core::sc_in< T > , sc_core::sc_in< bool > , sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_logic > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< T > , sc_core::sc_inout< bool > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_logic > , sc_core::sc_inout< sc_dt::sc_uint< W > > , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signal_in_if< T > , sc_core::sc_signal_in_if< bool > , sc_core::sc_signal_in_if< sc_dt::sc_bigint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_biguint< W > > , sc_core::sc_signal_in_if< sc_dt::sc_int< W > > , sc_core::sc_signal_in_if< sc_dt::sc_logic > , sc_core::sc_signal_in_if< sc_dt::sc_uint< W > > , sc_dt::sc_fxnum_fast_observer , sc_dt::sc_fxnum_observer , sc_dt::sc_fxval_fast_observer , sc_dt::sc_fxval_observer , sc_gem5::ScSignalBaseT< T, WRITER_POLICY > , SimpleDisk , SimpleUart , Sinic::Device , Sp804 , Sp804::Timer , Sp805 , Terminal , tlm::circular_buffer< T > , Trace::NativeTrace , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , TsunamiCChip , TsunamiIO , TsunamiPChip , Uart8250 , UFSHostDevice , VecRegisterState , VectorRegisterFile , VGic , VirtDescriptor , VirtIO9PDiod , VirtIO9PProxy , VirtIO9PSocket , VirtIOBlock , VirtQueue::VirtRing< T > , VncServer , X86ISA::Cmos , X86ISA::I8042 , X86ISA::I82094AA , X86ISA::I8237 , X86ISA::I8254 , X86ISA::I8259 , X86ISA::Interrupts , X86ISA::LongModePTE , X86ISA::Speaker
• read1() : VncServer
• read_data() : tlm::circular_buffer< T >
• read_event() : tlm::tlm_fifo< T >
• read_part() : sc_core::sc_int_part_if , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signed_part_if , sc_core::sc_uint_part_if , sc_core::sc_unsigned_part_if
• readable() : MemBackdoor
• readAll() : VirtIO9PProxy
• readArchCCReg() : FullO3CPU< Impl >
• readArchFloatReg() : FullO3CPU< Impl >
• readArchIntReg() : FullO3CPU< Impl >
• readArchVecElem() : FullO3CPU< Impl >
• readArchVecLane() : FullO3CPU< Impl >
• readArchVecPredReg() : FullO3CPU< Impl >
• readArchVecReg() : FullO3CPU< Impl >
• readBankedMiscReg() : Gicv3CPUInterface
• readBlob() : PortProxy
• readBlobPhys() : PortProxy
• readByte() : SubBlock
• readCallArgMem() : Wavefront
• readCallback() : GPUCoalescer , Sequencer , UFSHostDevice , UFSHostDevice::UFSSCSIDevice
• readCCReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readCCRegFlat() : CheckerThreadContext< TC > , FastModel::CortexA76TC , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readCCRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readCommand() : IdeDisk , ItsCommand
• readComplete() : DRAMSim2
• readCompressedTrace() : RubySystem
• readConfig() : IdeController , PciDevice , VirtIO9PBase , VirtIOBlock , VirtIOConsole , VirtIODeviceBase
• readConfigBlob() : VirtIODeviceBase
• readControl() : IdeDisk , SMMUv3
• readCopyBytes() : CopyEngine::CopyEngineChannel
• readCopyBytesComplete() : CopyEngine::CopyEngineChannel
• readCounter() : Intel8254Timer , X86ISA::I8254
• readCpu() : BaseGicRegisters , GicV2 , KvmKernelGicV2
• readCtrl() : VGic
• readData() : MC146818 , SerialDevice , SerialNullDevice , Terminal
• readDataOut() : X86ISA::I8042
• readDataTimed() : ArmISA::Stage2MMU
• readDataUntimed() : ArmISA::Stage2MMU
• readDevice() : UFSHostDevice
• readDeviceTable() : ItsProcess
• readDisk() : IdeDisk
• readDistributor() : BaseGicRegisters , GicV2 , KvmKernelGicV2
• readDone() : UFSHostDevice
• readEntryLPI() : Gicv3Redistributor
• readFillStart() : SparcProcess
• readFlash() : UFSHostDevice::UFSSCSIDevice
• readFloatReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readFloatRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readFloatRegOperandBits() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readFramebuffer() : Pl111
• readFreeEntries() : DefaultRename< Impl >
• readFSReg() : SparcISA::ISA
• readFuncExeInst() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• readGarbage() : UFSHostDevice
• readHeader() : VirtQueue::VirtRing< T >
• readHeadInst() : ROB< Impl >
• readId() : AmbaDevice
• readIE() : RiscvISA::Interrupts
• readIntReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readIntRegFlat() : CheckerThreadContext< TC > , FastModel::CortexA76TC , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readIntRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readIob() : Iob
• readIP() : RiscvISA::Interrupts
• readIpr() : AlphaISA::ISA
• readIrqCollectionTable() : ItsProcess
• readIrqTranslationTable() : ItsProcess
• readJBus() : Iob
• readLastActivate() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• readLastSuspend() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext , ThreadState
• readMem() : AtomicSimpleCPU , BaseSimpleCPU , CheckerCPU , ExecContext
• ReadMem() : Shader
• readMem() : SimpleExecContext
• readMemAccPredicate() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , Minor::MinorDynInst , SimpleExecContext , SimpleThread
• readMemNoEffect() : Trace::TarmacParserRecord
• readMemory() : AbstractNVM , FlashDevice
• readMiscReg() : AlphaISA::ISA , ArmISA::BaseISADevice , ArmISA::DummyISADevice , ArmISA::ISA , ArmISA::PMU , BaseO3DynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , FullO3CPU< Impl > , GenericTimer , GenericTimerISA , Gicv3CPUInterface , GPUExecContext , HsailISA::GPUISA , Iris::ThreadContext , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< Impl > , PowerISA::ISA , RiscvISA::ISA , SimpleExecContext , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegInt() : ArmISA::PMU
• readMiscRegNoEffect() : AlphaISA::ISA , ArmISA::ISA , CheckerCPU , CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , Minor::ExecContext , MipsISA::ISA , O3ThreadContext< Impl > , PowerISA::ISA , RiscvISA::ISA , SimpleThread , SparcISA::ISA , ThreadContext , X86ISA::ISA
• readMiscRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readNextWindow() : TraceCPU::ElasticDataGen
• readonly() : X86ISA::LongModePTE
• readPC() : ArmISA::ArmStaticInst
• readPredicate() : BaseDynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , Minor::MinorDynInst , SimpleExecContext , SimpleThread
• readPredTaken() : BaseDynInst< Impl >
• readPredTarg() : BaseDynInst< Impl >
• readQueueFull() : DRAMCtrl , QoS::MemSinkCtrl
• readReg() : HDLcd , NoMaliGpu , O3ThreadContext< Impl > , X86ISA::I82094AA , X86ISA::Interrupts
• readRegister() : X86ISA::Cmos
• readRegRaw() : NoMaliGpu
• reads() : ArmISA::ISA::MiscRegLUTEntryInitializer
• readSpillStart() : SparcProcess
• readsSCC() : GPUDynInst , GPUStaticInst
• readStallSignals() : DefaultDecode< Impl > , DefaultRename< Impl >
• readStCondFailures() : BaseDynInst< Impl > , CheckerCPU , CheckerThreadContext< TC > , ExecContext , Iris::ThreadContext , Minor::ExecContext , O3ThreadContext< Impl > , SimpleExecContext , SimpleThread , ThreadContext
• readString() : ArmSemihosting , PortProxy , X86ISA::SMBios::SMBiosStructure
• readsVCC() : GPUDynInst , GPUStaticInst
• readTailInst() : ROB< Impl >
• readVCpu() : VGic
• readVec16BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec16BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVec32BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec32BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVec64BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec64BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVec8BitLaneOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVec8BitLaneReg() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecElem() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readVecElemFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecElemOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVecLane() : FullO3CPU< Impl > , PhysRegFile , SimpleThread
• readVecLaneFlat() : O3ThreadContext< Impl > , SimpleThread
• readVecLaneOperand() : SimpleExecContext
• readVecPredReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readVecPredRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecPredRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readVecReg() : CheckerThreadContext< TC > , FullO3CPU< Impl > , Iris::ThreadContext , O3ThreadContext< Impl > , PhysRegFile , SimpleThread , ThreadContext
• readVecRegFlat() : CheckerThreadContext< TC > , Iris::ThreadContext , O3ThreadContext< Impl > , SimpleThread , ThreadContext
• readVecRegOperand() : BaseO3DynInst< Impl > , CheckerCPU , ExecContext , Minor::ExecContext , SimpleExecContext
• readWord() : PixelConverter
• ready() : sc_gem5::Process , sc_gem5::Scheduler , Wavefront
• readyToCkpt() : DistIface
• readyToCommit() : BaseDynInst< Impl >
• readyToExit() : DistIface
• readyToIssue() : BaseDynInst< Impl >
• ReadyWorkgroup() : ComputeUnit
• RealView() : RealView
• RealViewCtrl() : RealViewCtrl
• RealViewOsc() : RealViewOsc
• RealViewTemperatureSensor() : RealViewTemperatureSensor
• reanalyzeAllMessages() : MessageBuffer
• reanalyzeList() : MessageBuffer
• reanalyzeMessages() : MessageBuffer
• receiveDeviceInterrupt() : Iob
• receiveJBusInterrupt() : Iob
• RECENCY() : MultiperspectivePerceptron::RECENCY
• RECENCYPOS() : MultiperspectivePerceptron::RECENCYPOS
• reconstructSequence() : STeMSPrefetcher
• recordAccess() : FALRU::CacheTracking
• recordCacheContents() : CacheMemory
• recordCacheTrace() : AbstractController
• recordCPReadCallBack() : GPUCoalescer
• recordCPWriteCallBack() : GPUCoalescer
• recordExecTick() : ElasticTrace
• recordIndirect() : IndirectPredictor , SimpleIndirectPredictor
• recordMissLatency() : GPUCoalescer , Sequencer
• recordPCChange() : CheckerCPU
• recordProducer() : InstructionQueue< Impl >
• recordRequestType() : CacheMemory , DirectoryMemory , DMASequencer , GPUCoalescer , Sequencer
• recordResult() : BaseDynInst< Impl >
• recordTarget() : IndirectPredictor , SimpleIndirectPredictor
• recordToCommTick() : ElasticTrace
• recordTurnaroundStats() : QoS::MemCtrl
• recreateable() : OutputFile< StreamType > , OutputStream
• recv() : BaseRemoteGDB , PS2Device , PS2Keyboard , PS2Mouse , PS2TouchKit
• recvAtomic() : AbstractController , AddrMapper::MapperSlavePort , AddrMapper , AtomicResponseProtocol , BaseCache::CpuSidePort , BaseCache , Bridge::BridgeSlavePort , Cache , CoherentXBar::CoherentXBarSlavePort , CommMonitor::MonitorSlavePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , GpuDispatcher::TLBPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , MemDelay::SlavePort , NoncoherentCache , NoncoherentXBar::NoncoherentXBarSlavePort , PioPort< Device > , QoS::MemSinkCtrl::MemoryPort , QoS::MemSinkCtrl , RubyPort::MemSlavePort , RubyPort::PioSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkSlavePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SMMUATSSlavePort , SMMUControlPort , SMMUSlavePort , SMMUv3SlaveInterface , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::IntSlavePort< Device >
• recvAtomicBackdoor() : AtomicResponseProtocol , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SimpleMemory::MemoryPort , SimpleMemory , SlavePort
• recvAtomicSnoop() : AddrMapper::MapperMasterPort , AddrMapper , AtomicRequestProtocol , AtomicSimpleCPU::AtomicCPUDPort , BaseCache::MemSidePort , BaseCache , BaseTrafficGen::TrafficGenPort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemDelay::MasterPort , MemTest::CpuPort , NoncoherentCache
• recvCommand() : CopyEngine::CopyEngineChannel
• recvCutText() : VncServer
• recvDone() : EtherInt
• recvFunctional() : AddrMapper::MapperSlavePort , AddrMapper , BaseCache::CpuSidePort , Bridge::BridgeSlavePort , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , FunctionalResponseProtocol , GpuDispatcher::TLBPort , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , MemDelay::SlavePort , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , QoS::MemSinkCtrl::MemoryPort , QoS::MemSinkCtrl , RubyPort::MemSlavePort , RubyPort::PioSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkSlavePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SMMUATSSlavePort , SMMUSlavePort , StubSlavePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvFunctionalSnoop() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUDPort , BaseCache::MemSidePort , BaseTrafficGen::TrafficGenPort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , FunctionalRequestProtocol , LSQ< Impl >::DcachePort , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemDelay::MasterPort , MemTest::CpuPort , Minor::LSQ::DcachePort , PortProxy , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , StubSlavePort , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort
• recvHeader() : DistIface , TCPIface
• recvKeyboardInput() : VncServer
• recvMessage() : X86ISA::Interrupts
• recvPacket() : DistEtherLink::LocalIface , DistIface , EtherInt , EtherLink::Interface , EtherSwitch::Interface , EtherTapInt , IGbEInt , NSGigE , NSGigEInt , Sinic::Device , Sinic::Interface , TCPIface , X86ISA::Walker::WalkerState
• recvPointerInput() : VncServer
• recvRangeChange() : AddrMapper::MapperMasterPort , AddrMapper , BaseXBar , CoherentXBar::CoherentXBarMasterPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , GpuDispatcher::TLBPort , HMCController , LdsState::CuSidePort , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemDelay::MasterPort , NoncoherentXBar::NoncoherentXBarMasterPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeMasterPort , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SimpleCache::MemSidePort , SimpleMemobj::MemSidePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort
• recvReal() : EtherTapBase , EtherTapStub
• recvReqRetry() : AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseKvmCPU::KVMCpuPort , BaseTrafficGen , BaseTrafficGen::TrafficGenPort , Bridge::BridgeMasterPort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DefaultFetch< Impl >::IcachePort , DefaultFetch< Impl > , DmaPort , GarnetSyntheticTraffic::CpuPort , Gicv3Its::DataPort , Gicv3Its , GpuDispatcher::TLBPort , LSQ< Impl >::DcachePort , LSQ< Impl > , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemTest::CpuPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentXBar::NoncoherentXBarMasterPort , NoncoherentXBar , QueuedMasterPort , RubyDirectedTester::CpuPort , RubyTester::CpuPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeMasterPort , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SerialLink::SerialLinkMasterPort , SimpleCache::MemSidePort , SimpleMemobj::MemSidePort , SMMUMasterPort , SMMUMasterTableWalkPort , System::SystemPort , TimingRequestProtocol , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , X86ISA::GpuTLB::CpuSidePort , X86ISA::GpuTLB::MemSidePort , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvResponse() : X86ISA::I82094AA
• recvRespRetry() : AddrMapper::MapperSlavePort , AddrMapper , Bridge::BridgeSlavePort , CommMonitor::MonitorSlavePort , CommMonitor , DRAMSim2::MemoryPort , DRAMSim2 , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , QueuedSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkSlavePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , StubSlavePort , TimingResponseProtocol , TLBCoalescer::CpuSidePort , TLBCoalescer::MemSidePort , X86ISA::GpuTLB::CpuSidePort
• recvRetry() : BaseXBar::Layer< SrcType, DstType > , LdsState::CuSidePort , LSQUnit< Impl > , MemTest
• recvRetrySnoopResp() : CommMonitor::MonitorMasterPort , CommMonitor , MasterPort , QueuedMasterPort , TimingRequestProtocol
• RecvScheduler() : DistIface::RecvScheduler
• recvSimulated() : EtherTapBase
• recvTCP() : TCPIface
• recvThreadFunc() : DistIface
• recvTimingReq() : AddrMapper::MapperSlavePort , AddrMapper , BaseCache::CpuSidePort , BaseCache , Bridge::BridgeSlavePort , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , DRAMCtrl::MemoryPort , DRAMCtrl , DRAMSim2::MemoryPort , DRAMSim2 , HMCController , LdsState::CuSidePort , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , MemDelay::SlavePort , NoncoherentCache , NoncoherentXBar::NoncoherentXBarSlavePort , NoncoherentXBar , QoS::MemSinkCtrl::MemoryPort , QoS::MemSinkCtrl , RubyPort::MemSlavePort , RubyPort::PioSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SerialLink::SerialLinkSlavePort , SimpleCache::CPUSidePort , SimpleMemobj::CPUSidePort , SimpleMemory::MemoryPort , SimpleMemory , SimpleTimingPort , SMMUATSSlavePort , SMMUSlavePort , SMMUv3SlaveInterface , StubSlavePort , TimingResponseProtocol , TLBCoalescer::CpuSidePort , X86ISA::GpuTLB::CpuSidePort
• recvTimingResp() : AbstractController::MemoryPort , AbstractController , AddrMapper::MapperMasterPort , AddrMapper , AtomicSimpleCPU::AtomicCPUPort , BaseCache::MemSidePort , BaseCache , BaseKvmCPU::KVMCpuPort , BaseTrafficGen , BaseTrafficGen::TrafficGenPort , Bridge::BridgeMasterPort , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CoherentXBar::SnoopRespPort , CommMonitor::MonitorMasterPort , CommMonitor , ComputeUnit::DataPort , ComputeUnit::DTLBPort , ComputeUnit::ITLBPort , ComputeUnit::LDSPort , ComputeUnit::SQCPort , DefaultFetch< Impl >::IcachePort , DmaPort , GarnetSyntheticTraffic::CpuPort , Gicv3Its::DataPort , Gicv3Its , GpuDispatcher::TLBPort , LSQ< Impl >::DcachePort , LSQ< Impl >::LSQRequest , LSQ< Impl > , LSQ< Impl >::SingleDataRequest , LSQ< Impl >::SplitDataRequest , LSQUnit< Impl > , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemDelay::MasterPort , MemTest::CpuPort , Minor::Fetch1::IcachePort , Minor::Fetch1 , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentCache , NoncoherentXBar::NoncoherentXBarMasterPort , NoncoherentXBar , RubyDirectedTester::CpuPort , RubyPort::MemMasterPort , RubyPort::PioMasterPort , RubyPort , RubyTester::CpuPort , sc_gem5::TlmToGem5Bridge< BITWIDTH >::BridgeMasterPort , sc_gem5::TlmToGem5Bridge< BITWIDTH > , SerialLink::SerialLinkMasterPort , SimpleCache::MemSidePort , SimpleMemobj::MemSidePort , SMMUATSMasterPort , SMMUMasterPort , SMMUMasterTableWalkPort , System::SystemPort , TimingRequestProtocol , TimingSimpleCPU::DcachePort , TimingSimpleCPU::IcachePort , TLBCoalescer::MemSidePort , TraceCPU::DcachePort , TraceCPU::IcachePort , X86ISA::GpuTLB::MemSidePort , X86ISA::IntMasterPort< Device > , X86ISA::Walker , X86ISA::Walker::WalkerPort
• recvTimingSnoopReq() : AddrMapper::MapperMasterPort , AddrMapper , BaseCache::MemSidePort , BaseCache , BaseTrafficGen::TrafficGenPort , Cache , CoherentXBar::CoherentXBarMasterPort , CoherentXBar , CommMonitor::MonitorMasterPort , CommMonitor , LSQ< Impl >::DcachePort , LSQ< Impl > , MasterPort , MemCheckerMonitor::MonitorMasterPort , MemCheckerMonitor , MemDelay::MasterPort , MemTest::CpuPort , Minor::LSQ::DcachePort , Minor::LSQ , NoncoherentCache , TimingRequestProtocol , TimingSimpleCPU::DcachePort , TraceCPU::DcachePort , TraceCPU::IcachePort
• recvTimingSnoopResp() : AddrMapper::MapperSlavePort , AddrMapper , BaseCache::CpuSidePort , BaseCache , Cache , CoherentXBar::CoherentXBarSlavePort , CoherentXBar , CommMonitor::MonitorSlavePort , CommMonitor , MemCheckerMonitor::MonitorSlavePort , MemCheckerMonitor , MemDelay::SlavePort , NoncoherentCache , sc_gem5::Gem5ToTlmBridge< BITWIDTH >::BridgeSlavePort , sc_gem5::Gem5ToTlmBridge< BITWIDTH > , SlavePort , StubSlavePort , TimingResponseProtocol
• recvTMsg() : VirtIO9PBase , VirtIO9PProxy
• recvTouchKit() : PS2TouchKit
• recycle() : MessageBuffer , WireBuffer
• RedirectPath() : RedirectPath
• ReExec() : ReExec
• RefCounted() : RefCounted
• RefCountingPtr() : RefCountingPtr< T >
• refLabel() : HsailCode , LabelMap
• refresh() : PerfKvmCounter , VPtr< T >
• Reg() : CopyEngineReg::Reg< T >
• reg() : EtherBus
• Reg() : iGbReg::Regs::Reg< T >
• reg() : sc_gem5::Scheduler
• regBusy() : ConditionRegisterState , VectorRegisterFile
• regData32() : Sinic::Device
• regData64() : Sinic::Device
• regData8() : Sinic::Device
• regenerateAddr() : BaseIndexingPolicy , SetAssociative , SkewedAssociative
• regenerateBlkAddr() : BaseCache , BaseSetAssoc , BaseTags , FALRU , SectorTags
• RegEntry() : Trace::TarmacBaseRecord::RegEntry
• regEtraceListeners() : ElasticTrace
• RegId() : RegId
• RegImmImmOp() : RegImmImmOp
• RegImmOp() : RegImmOp
• RegImmRegOp() : RegImmRegOp
• RegImmRegShiftOp() : RegImmRegShiftOp
• regIndex() : BaseOperand , BaseRegOperand , RegAddrOperand< RegOperandType > , RegOrImmOperand< RegOperand, T >
• regInterfaceCallback() : SerialDevice
• regionSize() : PoolManager , SimplePoolManager
• register_b_transport() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_extension() : tlm::tlm_extension_base
• register_get_direct_mem_ptr() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_id() : sc_core::sc_report
• register_invalidate_direct_mem_ptr() : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_nb_transport_bw() : tlm_utils::multi_passthrough_initiator_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::simple_initiator_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_initiator_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_nb_transport_fw() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• register_port() : sc_core::sc_fifo< T > , sc_core::sc_interface , sc_core::sc_signal< sc_dt::sc_bigint< W > > , sc_core::sc_signal< sc_dt::sc_biguint< W > > , sc_core::sc_signal< sc_dt::sc_int< W > > , sc_core::sc_signal< sc_dt::sc_uint< W > > , sc_core::sc_signal_resolved , sc_core::sc_signal_rv< W > , sc_gem5::ScSignalBaseT< T, WRITER_POLICY > , tlm_utils::callback_binder_fw< TYPES >
• register_private_extension() : tlm_utils::ispex_base
• register_transport_dbg() : tlm_utils::multi_passthrough_target_socket< MODULE, BUSWIDTH, TYPES, N, POL > , tlm_utils::passthrough_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::passthrough_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_b< MODULE, BUSWIDTH, TYPES, POL > , tlm_utils::simple_target_socket_tagged_b< MODULE, BUSWIDTH, TYPES, POL >
• registerAbstractController() : RubySystem
• registerCU() : Shader
• registerDequeueCallback() : MessageBuffer
• registerDevice() : PciHost , RealViewCtrl
• registerDrainable() : DrainManager
• registerEvent() : ArmISA::PMU , ComputeUnit
• registerHandler() : ExternalMaster , ExternalSlave
• registerKickCallback() : VirtIODeviceBase
• registerNetwork() : RubySystem
• registerPowerProducer() : SubSystem
• registerQueue() : VirtIODeviceBase
• registerSrcClockDom() : VoltageDomain
• registerThreadContext() : System
• registerThreadContexts() : BaseCPU
• registerTraceFile() : sc_gem5::Scheduler
• registerWithClockDomain() : ClockDomain
• RegMiscRegImmOp() : RegMiscRegImmOp
• RegMiscRegImmOp64() : RegMiscRegImmOp64
• regNxtBusy() : VectorRegisterFile
• RegOp() : RegOp , X86ISA::RegOp
• RegOpBase() : X86ISA::RegOpBase
• RegOpImm() : X86ISA::RegOpImm
• RegOrImmOperand() : RegOrImmOperand< RegOperand, T >
• regPort() : sc_gem5::Port
• regProbeListeners() : ArmISA::PMU , BaseMemProbe , BasePrefetcher , ElasticTrace , SimObject , SimpleTrace , SimPoint
• regProbePoints() : ArmISA::TLB , AtomicSimpleCPU , BaseCache , BaseCPU , BPredUnit , CommMonitor , DefaultCommit< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , FullO3CPU< Impl > , PowerModel , SimObject
• RegRegImmImmOp() : RegRegImmImmOp
• RegRegImmImmOp64() : RegRegImmImmOp64
• RegRegImmOp() : RegRegImmOp
• RegRegOp() : RegRegOp
• RegRegRegImmOp() : RegRegRegImmOp
• RegRegRegImmOp64() : RegRegRegImmOp64
• RegRegRegOp() : RegRegRegOp
• RegRegRegRegOp() : RegRegRegRegOp
• regSize() : VecRegisterState
• regsReady() : MemDepUnit< MemDepPred, Impl >
• regsReset() : NSGigE
• regStats() : AbstractController , AbstractMemory::MemStats , AddressProfiler , AlphaISA::Kernel::Statistics , AlphaISA::TLB , ArmISA::TableWalker , ArmISA::TLB , BaseCache::CacheStats , BaseCacheCompressor::BaseCacheCompressorStats , BaseCPU , BaseDictionaryCompressor , BaseKvmCPU , BaseO3CPU , BasePrefetcher , BaseSimpleCPU , BaseTags::BaseTagStats , BaseXBar , BPredUnit , CacheMemory , CheckerThreadContext< TC > , ClockedObject::ClockedObjectStats , CoherentXBar , ComputeUnit , ConditionRegisterState , CopyEngine , DefaultCommit< Impl > , DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultIEW< Impl > , DefaultRename< Impl > , DRAMCtrl::DRAMStats , DRAMCtrl::Rank , DRAMCtrl::RankStats , ElasticTrace , EtherDevice , ExecStage , FALRU::CacheTracking , FALRU , FetchStage , FlashDevice , FullO3CPU< Impl > , GarnetNetwork , GlobalMemPipeline , GPUCoalescer , HDLcd , IdeDisk , InstructionQueue< Impl > , Iris::ThreadContext , Kernel::Statistics , LocalMemPipeline , LoopPredictor , LSQ< Impl > , LSQUnit< Impl > , LTAGE , MathExprPowerModel , MemDepUnit< MemDepPred, Impl > , MemFootprintProbe , MemTest , MessageBuffer , Minor::Fetch2 , Minor::MinorStats , Minor::Pipeline , MinorCPU , MipsISA::TLB , MultiCompressor , O3ThreadContext< Impl > , PowerISA::TLB , PowerModel , PowerModelState , Prefetcher , Process , Profiler , QoS::MemCtrl::MemCtrlStats , QoS::MemSinkCtrl , QoS::Policy , QueuedPrefetcher , RiscvISA::TLB , ROB< Impl > , Router , RubySystem , sc_gem5::Kernel , ScheduleStage , ScoreboardCheckStage , SectorTags::SectorTagsStats , Sequencer , SimpleCache , SimpleNetwork , SimpleThread , Sinic::Device , SMMUv3 , SMMUv3BaseCache , SnoopFilter , StackDistProbe , StatisticalCorrector , Stats::Group , Switch , System , TAGE_SC_L , TAGEBase , ThermalDomain , ThreadContext , Throttle , Ticked , TickedObject , TLBCoalescer , TraceCPU::ElasticDataGen , TraceCPU::FixedRetryGen , TraceCPU , UFSHostDevice , VecRegisterState , WalkCache , Wavefront , X86ISA::GpuTLB , X86ISA::TLB
• regStatsFromParent() : BaseCache::CacheCmdStats
• RegularProbe() : ArmISA::PMU::RegularEvent::RegularProbe
• reinit() : ItsProcess , SMMUProcess
• release() : Event , LSQ< Impl >::LSQRequest , sc_core::sc_mempool , SimpleATInitiator1::SimplePool , SimpleATInitiator2::SimplePool , SimpleMemory , tlm::tlm_generic_payload , TraceCPU::ElasticDataGen::HardwareResource
• release_carrier() : tlm_utils::instance_specific_extension_accessor
• release_extension() : tlm::tlm_generic_payload
• releaseImpl() : Event , PyEvent
• releaseLayer() : BaseXBar::Layer< SrcType, DstType >
• releaseSpace() : LdsState
• releaseStoreBuffer() : TraceCPU::ElasticDataGen::HardwareResource
• reloadRegMap() : SparcISA::ISA
• relocatable() : ElfObject , ObjectFile
• relocate() : OutputFile< StreamType > , OutputStream
• remainingSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• remap() : EmulationPageTable , FlashDevice , MultiLevelPageTable< EntryTypes > , Wavefront
• remapAddr() : AddrMapper , RangeAddrMapper
• RemoteGDB() : AlphaISA::RemoteGDB , ArmISA::RemoteGDB , MipsISA::RemoteGDB , PowerISA::RemoteGDB , RiscvISA::RemoteGDB , SparcISA::RemoteGDB , X86ISA::RemoteGDB
• remove() : CheckerThreadContext< TC > , DependencyGraph< DynInstPtr > , EventQueue , Iris::ThreadContext , NetDest , O3ThreadContext< Impl > , OutputDirectory , PacketFifo , PCEvent , PCEventQueue , PCEventScope , PollQueue , sc_core::sc_attr_cltn , sc_dt::scfx_string , Set , SimpleThread , System , Trie< Key, Value >
• remove_all() : sc_core::sc_attr_cltn
• remove_all_attributes() : sc_core::sc_object , sc_gem5::Object
• remove_attribute() : sc_core::sc_object , sc_gem5::Object
• remove_it() : sc_dt::scfx_mant_ref
• remove_traces() : sc_core::sc_in< sc_dt::sc_bigint< W > > , sc_core::sc_in< sc_dt::sc_biguint< W > > , sc_core::sc_in< sc_dt::sc_int< W > > , sc_core::sc_in< sc_dt::sc_uint< W > > , sc_core::sc_inout< sc_dt::sc_bigint< W > > , sc_core::sc_inout< sc_dt::sc_biguint< W > > , sc_core::sc_inout< sc_dt::sc_int< W > > , sc_core::sc_inout< sc_dt::sc_uint< W > >
• removeDepOnInst() : TraceCPU::ElasticDataGen::GraphNode
• removeFromHistory() : DefaultRename< Impl >
• removeFrontInst() : FullO3CPU< Impl >
• removeHardBreak() : BaseRemoteGDB
• removeInLSQ() : BaseDynInst< Impl >
• removeInstsNotInROB() : FullO3CPU< Impl >
• removeInstsUntil() : FullO3CPU< Impl >
• removeIntlvBits() : AddrRange
• removeItem() : Event
• removeListener() : ProbeManager , ProbePoint , ProbePointArg< Arg >
• removeNetDest() : NetDest
• removeRegDep() : TraceCPU::ElasticDataGen::GraphNode
• removeRegDepMapEntry() : ElasticTrace
• removeRequest() : GPUCoalescer
• removeRobDep() : TraceCPU::ElasticDataGen::GraphNode
• removeSet() : Set
• removeSoftBreak() : BaseRemoteGDB
• removeThread() : FullO3CPU< Impl >
• rename() : CxxConfigManager , DefaultRename< Impl > , SimpleRenameMap , UnifiedRenameMap
• renamedDestRegIdx() : BaseDynInst< Impl >
• renameDestReg() : BaseDynInst< Impl >
• renameDestRegs() : DefaultRename< Impl >
• renamedSrcRegIdx() : BaseDynInst< Impl >
• RenameHistory() : DefaultRename< Impl >::RenameHistory
• renameInsts() : DefaultRename< Impl >
• renameSrcReg() : BaseDynInst< Impl >
• renameSrcRegs() : DefaultRename< Impl >
• Renaming() : CxxConfigManager::Renaming
• renderFrame() : BasePixelPump
• renderLine() : BasePixelPump
• renderPixels() : BasePixelPump
• RepeatedQwordsCompressor() : RepeatedQwordsCompressor
• RepeatedValuePattern() : DictionaryCompressor< T >::RepeatedValuePattern< RepT >
• repeatEvent() : CPUProgressEvent
• ReplaceableEntry() : ReplaceableEntry
• replaceHead() : EventQueue
• replaceThreadContext() : BaseRemoteGDB , CpuEvent , System
• replaceUpgrades() : MSHR::TargetList
• replay() : MemDepUnit< MemDepPred, Impl >
• replayMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• replicatePage() : Process
• report() : sc_core::sc_report_handler
• report_error() : sc_core::sc_port_base
• reportData() : Minor::BranchData , Minor::Fetch1::FetchRequest , Minor::ForwardInstData , Minor::ForwardLineData , Minor::LSQ::LSQRequest , Minor::MinorDynInst , Minor::QueuedInst , Minor::ReportIF , Minor::ReportTraitsAdaptor< ElemType > , Minor::ReportTraitsPtrAdaptor< PtrType >
• reportEmpty() : sc_core::sc_vector_base
• ReportMsgInfo() : sc_gem5::ReportMsgInfo
• ReportSevInfo() : sc_gem5::ReportSevInfo
• reqIPI() : MaltaCChip , TsunamiCChip
• ReqLayer() : BaseXBar::ReqLayer
• ReqLookupResult() : SnoopFilter::ReqLookupResult
• ReqPacketQueue() : ReqPacketQueue
• reqQueueFull() : Bridge::BridgeMasterPort , SerialLink::SerialLinkMasterPort
• request() : LSQ< Impl >::LSQRequest , LSQ< Impl >::LSQSenderState , LSQUnit< Impl >::LSQEntry
• Request() : Request
• request_update() : sc_core::sc_prim_channel
• requestCkpt() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• RequestDesc() : RequestDesc
• requestExit() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• requestFbUpdate() : VncServer
• requestHandler() : UFSHostDevice
• requestInterrupt() : X86ISA::I8259 , X86ISA::Interrupts
• RequestQueue() : VirtIOBlock::RequestQueue
• requestSize() : DmaReadFifo::DmaDoneEvent
• requestStopSync() : DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch
• RequestThread() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >
• requestUpdate() : sc_gem5::Channel , sc_gem5::Scheduler
• requeue() : FutexMap
• res0() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer
• res1() : ArmISA::ISA::MiscRegLUTEntry , ArmISA::ISA::MiscRegLUTEntryInitializer
• reschedule() : BaseGlobalEvent , EventManager , EventQueue , MemDepUnit< MemDepPred, Impl >
• rescheduleMemInst() : DefaultIEW< Impl > , InstructionQueue< Impl >
• reserve() : BankedArray , Minor::InputBuffer< ElemType, ReportTraits, BubbleTraits > , Minor::Queue< ElemType, ReportTraits, BubbleTraits > , Minor::Reservable , PacketFifo
• reserved() : PacketFifo
• reservedSpace() : Minor::Queue< ElemType, ReportTraits, BubbleTraits >
• reserveSpace() : LdsState
• reset() : ActivityRecorder , AlphaISA::Decoder , ArmISA::Decoder , ArmISA::ISA::MiscRegLUTEntry , BaseReplacementPolicy , BIPRP , BRRIPRP , DefaultBTB , DependencyGraph< DynInstPtr > , DmaReadFifo::DmaDoneEvent , FIFORP , Gicv3 , IdeDisk , IGbE::DescCache< T > , LFURP , LRURP , MemChecker , MipsISA::Decoder , MRURP , NoMaliGpu , PowerISA::Decoder , ProtoInputStream , RandomRP , ReturnAddrStack , RiscvISA::Decoder
• Reset() : RiscvISA::Reset
• reset() : SatCounter , sc_core::sc_process_handle , sc_core::sc_simcontext
• Reset() : sc_core::sc_spawn_options::Reset< T >
• reset() : sc_core::sc_vpool< T > , sc_gem5::Process
• Reset() : sc_gem5::Reset
• reset() : SecondChanceRP , Sinic::Device , SparcISA::Decoder , Stats::AvgSampleStor , Stats::AvgStor , Stats::DataWrapVec< Derived, InfoProxyType > , Stats::DistBase< Derived, Stor > , Stats::DistProxy< Stat > , Stats::DistStor , Stats::Formula , Stats::HistStor , Stats::Info , Stats::InfoAccess , Stats::InfoProxy< Stat, Base > , Stats::ProxyInfo , Stats::SampleStor , Stats::ScalarBase< Derived, Stor > , Stats::SparseHistBase< Derived, Stor > , Stats::SparseHistStor , Stats::StatStor , Stats::ValueBase< Derived > , Stats::Vector2dBase< Derived, Stor > , tlm::tlm_generic_payload , tlm_utils::peq_with_cb_and_phase< OWNER, TYPES >::delta_list , tlm_utils::time_ordered_list< PAYLOAD > , tlm_utils::tlm_quantumkeeper , TraceCPU::ElasticDataGen::InputStream , TraceCPU::FixedRetryGen::InputStream , TraceGen::InputStream , TreePLRURP , UFSHostDevice::SCSIReply , VecPredRegContainer< NumBits, Packed > , VecPredRegT< VecElem, NumElems, Packed, Const > , VirtIODeviceBase , WeightedLRUPolicy , WriteAllocator , X86ISA::Decoder , X86ISA::ExtMachInst , X86ISA::LongModePTE
• reset_event() : sc_core::sc_process_handle
• reset_loop() : test
• reset_signal_is() : sc_core::sc_module , sc_core::sc_spawn_options
• resetAddr() : ArmSystem
• resetClock() : Clocked
• resetDelay() : WriteAllocator
• resetDictionary() : BaseDelta< BaseType, DeltaSizeBits > , DictionaryCompressor< T >
• resetEntries() : DefaultIEW< Impl > , InstructionQueue< Impl > , ROB< Impl >
• resetEvent() : sc_gem5::Process
• resetEventCounts() : ArmISA::PMU
• resetFlags() : MSHR::TargetList
• resetHppi() : Gicv3CPUInterface
• resetLastStopped() : Ticked
• resetOffset() : StorageMap , StorageSpace
• resetScores() : BOPPrefetcher
• resetStage() : DefaultDecode< Impl > , DefaultFetch< Impl > , DefaultRename< Impl >
• resetState() : InstructionQueue< Impl > , LSQUnit< Impl > , ROB< Impl >
• resetStats() : AbstractController , BaseSimpleCPU , CrossbarSwitch , DRAMCtrl::DRAMStats , DRAMCtrl::Rank , DRAMCtrl::RankStats , GPUCoalescer , InputUnit , NetworkLink , Router , RubySystem , Sequencer , Sinic::Device , Stats::Group , Switch , SwitchAllocator
• resetUctr() : MPP_TAGE , TAGE_SC_L_TAGE_8KB , TAGEBase
• resetVect() : RiscvSystem
• resize() : DependencyGraph< DynInstPtr > , FrameBuffer , Minor::ForwardInstData , NetDest , sc_dt::scfx_rep , sc_dt::scfx_string , SubBlock , tlm::circular_buffer< T > , tlm_utils::instance_specific_extension_container
• resize_extensions() : tlm::tlm_generic_payload , tlm_utils::instance_specific_extensions_per_accessor
• resize_to() : sc_dt::scfx_mant , sc_dt::scfx_rep
• resizeRegFiles() : ComputeUnit , Wavefront
• resolution() : BaseKvmTimer
• resolve() : OutputDirectory
• resolveFile() : TrafficGen
• resolveSimObject() : CxxConfigManager::SimObjectResolver , PybindSimObjectResolver , SimObjectResolver
• RespLayer() : BaseXBar::RespLayer
• responderHadWritable() : Packet
• responseCommand() : MemCmd
• ResponseThread() : SimpleBusAT< NR_OF_INITIATORS, NR_OF_TARGETS >
• RespPacketQueue() : RespPacketQueue
• respQueueFull() : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• restartClock() : IGbE
• restartCounter() : A9GlobalTimer::Timer , Sp804::Timer , Sp805
• restartStateMachine() : CopyEngine::CopyEngineChannel
• restartTimerCounter() : CpuLocalTimer::Timer
• restartWatchdogCounter() : CpuLocalTimer::Timer
• restore() : ReturnAddrStack
• restoreFileOffsets() : FDArray
• result() : Stats::AvgStor , Stats::BinaryNode< Op > , Stats::ConstNode< T > , Stats::ConstVectorNode< T > , Stats::Formula , Stats::FormulaInfoProxy< Stat > , Stats::FormulaNode , Stats::FunctorProxy< T > , Stats::MethodProxy< T, V > , Stats::Node , Stats::ScalarBase< Derived, Stor > , Stats::ScalarInfo , Stats::ScalarInfoProxy< Stat > , Stats::ScalarProxy< Stat > , Stats::ScalarProxyNode< Stat > , Stats::ScalarStatNode , Stats::StatStor , Stats::SumNode< Op > , Stats::UnaryNode< Op > , Stats::ValueBase< Derived > , Stats::ValueProxy< T > , Stats::VectorBase< Derived, Stor > , Stats::VectorInfo , Stats::VectorInfoProxy< Stat > , Stats::VectorProxy< Stat > , Stats::VectorStatNode
• resultInt() : sc_gem5::ScMainFiber
• resultSize() : BaseDynInst< Impl >
• resultStr() : sc_gem5::ScMainFiber
• resume() : BasePixelPump::PixelEvent , DrainManager , sc_core::sc_process_handle , sc_gem5::Process , sc_gem5::Scheduler
• resumeFill() : DmaReadFifo
• resumeFillFunctional() : DmaReadFifo
• resumeFillTiming() : DmaReadFifo
• resumeRecvTicks() : DistIface::RecvScheduler
• resumeTransaction() : SMMUTranslationProcess
• resyncMatch() : PL031
• Ret() : HsailISA::Ret
• retError() : ArmSemihosting
• retireHead() : ROB< Impl >
• retireResponse() : Minor::LSQ::LSQRequest , Minor::LSQ::SingleDataRequest , Minor::LSQ::SpecialDataRequest , Minor::LSQ::SplitDataRequest
• retOK() : ArmSemihosting
• retransmit() : EtherTapBase
• retry() : PacketQueue , SyscallReturn , X86ISA::Walker::WalkerState
• retryReq() : BaseTrafficGen
• retryStalledReq() : Bridge::BridgeSlavePort , SerialLink::SerialLinkSlavePort
• retryWaiting() : BaseXBar::Layer< SrcType, DstType >
• ReturnAddrStack() : ReturnAddrStack
• returnQueuePush() : LdsState
• returnValue() : SyscallReturn
• rev() : AtagRev
• reverse() : sc_dt::sc_proxy< X > , sc_dt::sc_signed , sc_dt::sc_unsigned
• reversed() : sc_dt::sc_subref_r< X >
• revokeThreadContext() : Process
• RfeOp() : ArmISA::RfeOp
• RiscvFault() : RiscvISA::RiscvFault
• RiscvLinuxProcess32() : RiscvLinuxProcess32
• RiscvLinuxProcess64() : RiscvLinuxProcess64
• RiscvMacroInst() : RiscvISA::RiscvMacroInst
• RiscvMicroInst() : RiscvISA::RiscvMicroInst
• RiscvProcess() : RiscvProcess
• RiscvProcess32() : RiscvProcess32
• RiscvProcess64() : RiscvProcess64
• RiscvSystem() : RiscvSystem
• rngstep() : QTIsaac< ALPHA >
• ROB() : ROB< Impl >
• Root() : Root
• root() : Root
• rootdev() : AtagCore
• ror() : ArmISA::Crypto
• rotate_counter() : HMCController
• rotateValue() : PowerISA::IntRotateOp
• round() : sc_dt::scfx_rep
• rounding_flag() : sc_dt::sc_fxval , sc_dt::sc_fxval_fast , sc_dt::scfx_rep
• roundRobin() : DefaultCommit< Impl > , DefaultFetch< Impl >
• roundRobinPriority() : MinorCPU
• route() : Gicv3Distributor
• route_compute() : Router
• Router() : Router
• routeToHyp() : ArmISA::ArmFault , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::Interrupt , ArmISA::PCAlignmentFault , ArmISA::PrefetchAbort , ArmISA::SoftwareBreakpoint , ArmISA::SPAlignmentFault , ArmISA::SupervisorCall , ArmISA::SupervisorTrap , ArmISA::SystemError , ArmISA::UndefinedInstruction
• routeToMonitor() : ArmISA::ArmFault , ArmISA::ArmFaultVals< T > , ArmISA::DataAbort , ArmISA::FastInterrupt , ArmISA::Interrupt , ArmISA::PrefetchAbort , ArmISA::SystemError
• RoutingUnit() : RoutingUnit
• rpc() : Wavefront
• rrotate() : sc_dt::sc_proxy< X >
• RRSchedulingPolicy() : RRSchedulingPolicy
• RSDP() : X86ISA::ACPI::RSDP
• RSDT() : X86ISA::ACPI::RSDT
• rshift() : sc_dt::scfx_rep
• RTC() : MaltaIO::RTC , TsunamiIO::RTC
• RTCEvent() : MC146818::RTCEvent
• RTCTickEvent() : MC146818::RTCTickEvent
• rtralt() : Net::IpOpt
• rtType2Addr() : Net::Ip6Opt
• rtType2SegLft() : Net::Ip6Opt
• rtType2Type() : Net::Ip6Opt
• rtTypeExt() : Net::Ip6Hdr
• ruby_eviction_callback() : RubyPort
• ruby_hit_callback() : RubyPort
• RubyDirectedTester() : RubyDirectedTester
• RubyDummyPort() : RubyDummyPort
• RubyPort() : RubyPort
• RubyPortProxy() : RubyPortProxy
• RubyRequest() : RubyRequest
• RubyStatsCallback() : RubyStatsCallback
• RubySystem() : RubySystem
• RubyTester() : RubyTester
• run() : CoreDecouplingLTInitiator , DistIface::Sync , DistIface::SyncNode , DistIface::SyncSwitch , Fiber , ItsProcess , sc_gem5::Process , sc_gem5::PythonInitFunc , sc_gem5::PythonReadyFunc , sc_gem5::ScEvent , SimpleATInitiator1 , SimpleATInitiator2 , SimpleLTInitiator1 , SimpleLTInitiator1_dmi , SimpleLTInitiator2 , SimpleLTInitiator2_dmi , SimpleLTInitiator3 , SimpleLTInitiator3_dmi , SimpleLTInitiator_ext , SMMUProcess , StatTest , tlm::tlm_slave_to_transport< REQ, RSP >
• runDelta() : sc_gem5::Scheduler
• runNext() : sc_gem5::Scheduler
• runNow() : sc_gem5::Scheduler
• runProcess() : Gicv3Its , SMMUv3
• runProcessAtomic() : Gicv3Its , SMMUv3
• runProcessTiming() : Gicv3Its , SMMUv3
• runReady() : sc_gem5::Scheduler
• runUpdate() : sc_gem5::Scheduler
• rv32() : RiscvISA::PCState
• rw() : ArmISA::TableWalker::LongDescriptor
• rwTable() : ArmISA::TableWalker::LongDescriptor
• RxDescCache() : IGbE::RxDescCache
• rxDmaDone() : Sinic::Device
• rxDmaReadDone() : NSGigE
• rxDmaWriteDone() : NSGigE
• rxDone() : DistEtherLink::RxLink
• rxDump() : NSGigE , Sinic::Device
• rxFilter() : NSGigE , Sinic::Device
• rxKick() : NSGigE , Sinic::Device
• RxLink() : DistEtherLink::RxLink
• rxReset() : NSGigE
• rxStateMachine() : IGbE