47 #include "debug/Decoder.hh" 100 uint16_t highBits = word & 0xF800;
101 if (highBits == 0xE800 || highBits == 0xF000 ||
102 highBits == 0xF800) {
114 "First half of 32 bit Thumb.\n");
115 emi.instBits = (uint32_t)word << 16;
129 if (
bits(word, 15, 8) == 0xbf &&
130 bits(word, 3, 0) != 0x0) {
134 "IT detected, cond = %#x, mask = %#x\n",
155 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
156 emi.thumb = pc.thumb();
157 emi.aarch64 = pc.aarch64();
162 const Addr alignment(pc.thumb() ? 0x1 : 0x3);
163 emi.decoderFault =
static_cast<uint8_t
>(
176 const int inst_size((!
emi.thumb ||
emi.bigThumb) ? 4 : 2);
179 pc.npc(pc.pc() + inst_size);
182 this_emi.itstate = pc.itstate();
183 this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
191 return decode(this_emi, pc.instAddr());
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
void process()
Pre-decode an instruction from the current state of the decoder.
static GenericISA::BasicDecodeCache defaultCache
A cache of decoded instruction objects.
unsigned getCurSveVecLenInBitsAtReset() const
Bitfield< 41, 40 > fpscrStride
StaticInstPtr decode(ArmISA::PCState &pc)
Decode an instruction or fetch it from the code cache.
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
Feed data to the decoder.
Bitfield< 39, 37 > fpscrLen
Decoder(ISA *isa=nullptr)
void reset()
Reset the decoders internal state.
T bits(T val, int first, int last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it...
Unaligned instruction fault.
GenericISA::DelaySlotPCState< MachInst > PCState