gem5
v20.0.0.0
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#include <i8254xGBe.hh>
Classes | |
class | DescCache |
class | RxDescCache |
class | TxDescCache |
Public Types | |
typedef IGbEParams | Params |
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typedef EtherDeviceParams | Params |
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typedef DmaDeviceParams | Params |
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typedef PioDeviceParams | Params |
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typedef ClockedObjectParams | Params |
Parameters of ClockedObject. More... | |
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typedef SimObjectParams | Params |
Public Member Functions | |
const Params * | params () const |
IGbE (const Params *params) | |
~IGbE () | |
void | init () override |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) override |
Get a port with a given name and index. More... | |
Tick | read (PacketPtr pkt) override |
Pure virtual function that the device must implement. More... | |
Tick | write (PacketPtr pkt) override |
Pure virtual function that the device must implement. More... | |
Tick | writeConfig (PacketPtr pkt) override |
Write to the PCI config space data that is stored locally. More... | |
bool | ethRxPkt (EthPacketPtr packet) |
void | ethTxDone () |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
DrainState | drain () override |
Notify an object that it needs to drain its state. More... | |
void | drainResume () override |
Resume execution after a successful drain. More... | |
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EtherDevice (const Params *params) | |
const Params * | params () const |
void | regStats () |
Callback to set stat parameters. More... | |
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virtual Tick | readConfig (PacketPtr pkt) |
Read from the PCI config space data that is stored locally. More... | |
Addr | pciToDma (Addr pci_addr) const |
void | intrPost () |
void | intrClear () |
uint8_t | interruptLine () const |
AddrRangeList | getAddrRanges () const override |
Determine the address ranges that this device responds to. More... | |
PciDevice (const PciDeviceParams *params) | |
Constructor for PCI Dev. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize this object to the given output stream. More... | |
void | unserialize (CheckpointIn &cp) override |
Reconstruct the state of this object from a checkpoint. More... | |
const PciBusAddr & | busAddr () const |
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DmaDevice (const Params *p) | |
virtual | ~DmaDevice () |
void | dmaWrite (Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) |
void | dmaWrite (Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) |
void | dmaRead (Addr addr, int size, Event *event, uint8_t *data, uint32_t sid, uint32_t ssid, Tick delay=0) |
void | dmaRead (Addr addr, int size, Event *event, uint8_t *data, Tick delay=0) |
bool | dmaPending () const |
unsigned int | cacheBlockSize () const |
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PioDevice (const Params *p) | |
virtual | ~PioDevice () |
const Params * | params () const |
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ClockedObject (const ClockedObjectParams *p) | |
const Params * | params () const |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
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virtual | ~SimObject () |
virtual const std::string | name () const |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. More... | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. More... | |
virtual void | regProbePoints () |
Register probe points for this object. More... | |
virtual void | regProbeListeners () |
Register probe listeners for this object. More... | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. More... | |
virtual void | startup () |
startup() is the final initialization call before simulation. More... | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. More... | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. More... | |
virtual void | memInvalidate () |
Invalidate the contents of memory buffers. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
const Params * | params () const |
SimObject (const Params *_params) | |
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EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
void | setCurTick (Tick newVal) |
EventManager (EventManager &em) | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. More... | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. More... | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. More... | |
virtual void | notifyFork () |
Notify a child process of a fork. More... | |
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Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. More... | |
virtual | ~Group () |
virtual void | resetStats () |
Callback to reset stats. More... | |
virtual void | preDumpStats () |
Callback before stats are dumped. More... | |
void | addStat (Stats::Info *info) |
Register a stat with this group. More... | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. More... | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. More... | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. More... | |
const Info * | resolveStat (std::string name) const |
Resolve a stat by its name within this group. More... | |
Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
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void | updateClockPeriod () |
Update the tick to the current tick. More... | |
Tick | clockEdge (Cycles cycles=Cycles(0)) const |
Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More... | |
Cycles | curCycle () const |
Determine the current cycle, corresponding to a tick aligned to a clock edge. More... | |
Tick | nextCycle () const |
Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More... | |
uint64_t | frequency () const |
Tick | clockPeriod () const |
double | voltage () const |
Cycles | ticksToCycles (Tick t) const |
Tick | cyclesToTicks (Cycles c) const |
Public Attributes | |
Tick | lastInterrupt |
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PowerState * | powerState |
Private Member Functions | |
void | rdtrProcess () |
void | radvProcess () |
void | tadvProcess () |
void | tidvProcess () |
void | tick () |
void | rxStateMachine () |
void | txStateMachine () |
void | txWire () |
void | postInterrupt (iGbReg::IntTypes t, bool now=false) |
Write an interrupt into the interrupt pending register and check mask and interrupt limit timer before sending interrupt to CPU. More... | |
void | chkInterrupt () |
Check and see if changes to the mask register have caused an interrupt to need to be sent or perhaps removed an interrupt cause. More... | |
void | delayIntEvent () |
Send an interrupt to the cpu. More... | |
void | cpuPostInt () |
void | cpuClearInt () |
Clear the interupt line to the cpu. More... | |
Tick | intClock () |
void | restartClock () |
This function is used to restart the clock so it can handle things like draining and resume in one place. More... | |
void | checkDrain () |
Check if all the draining things that need to occur have occured and handle the drain event if so. More... | |
void | anBegin (std::string sm, std::string st, int flags=CPA::FL_NONE) |
void | anQ (std::string sm, std::string q) |
void | anDq (std::string sm, std::string q) |
void | anPq (std::string sm, std::string q, int num=1) |
void | anRq (std::string sm, std::string q, int num=1) |
void | anWe (std::string sm, std::string q) |
void | anWf (std::string sm, std::string q) |
Private Attributes | |
IGbEInt * | etherInt |
CPA * | cpa |
iGbReg::Regs | regs |
int | eeOpBits |
int | eeAddrBits |
int | eeDataBits |
uint8_t | eeOpcode |
uint8_t | eeAddr |
uint16_t | flash [iGbReg::EEPROM_SIZE] |
PacketFifo | rxFifo |
PacketFifo | txFifo |
EthPacketPtr | txPacket |
bool | inTick |
bool | rxTick |
bool | txTick |
bool | txFifoTick |
bool | rxDmaPacket |
unsigned | pktOffset |
Tick | fetchDelay |
Tick | wbDelay |
Tick | fetchCompDelay |
Tick | wbCompDelay |
Tick | rxWriteDelay |
Tick | txReadDelay |
EventFunctionWrapper | rdtrEvent |
EventFunctionWrapper | radvEvent |
EventFunctionWrapper | tadvEvent |
EventFunctionWrapper | tidvEvent |
EventFunctionWrapper | tickEvent |
uint64_t | macAddr |
EventFunctionWrapper | interEvent |
RxDescCache | rxDescCache |
TxDescCache | txDescCache |
Friends | |
class | RxDescCache |
class | TxDescCache |
Additional Inherited Members | |
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static void | serializeAll (CheckpointOut &cp) |
Serialize all SimObjects in the system. More... | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. More... | |
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static const std::string & | currentSection () |
Gets the fully-qualified name of the active section. More... | |
static void | serializeAll (const std::string &cpt_dir) |
static void | unserializeGlobals (CheckpointIn &cp) |
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bool | isLargeBAR (int bar) const |
Does the given BAR represent 32 lower bits of a 64-bit address? More... | |
bool | isBAR (Addr addr, int bar) const |
Does the given address lie within the space mapped by the given base address register? More... | |
int | getBAR (Addr addr) |
Which base address register (if any) maps the given address? More... | |
bool | getBAR (Addr addr, int &bar, Addr &offs) |
Which base address register (if any) maps the given address? More... | |
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Drainable () | |
virtual | ~Drainable () |
void | signalDrainDone () const |
Signal that an object is drained. More... | |
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Clocked (ClockDomain &clk_domain) | |
Create a clocked object and set the clock domain based on the parameters. More... | |
Clocked (Clocked &)=delete | |
Clocked & | operator= (Clocked &)=delete |
virtual | ~Clocked () |
Virtual destructor due to inheritance. More... | |
void | resetClock () const |
Reset the object's clock using the current global tick value. More... | |
virtual void | clockPeriodUpdated () |
A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More... | |
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Stats::Scalar | txBytes |
Stats::Scalar | rxBytes |
Stats::Scalar | txPackets |
Stats::Scalar | rxPackets |
Stats::Scalar | txIpChecksums |
Stats::Scalar | rxIpChecksums |
Stats::Scalar | txTcpChecksums |
Stats::Scalar | rxTcpChecksums |
Stats::Scalar | txUdpChecksums |
Stats::Scalar | rxUdpChecksums |
Stats::Scalar | descDmaReads |
Stats::Scalar | descDmaWrites |
Stats::Scalar | descDmaRdBytes |
Stats::Scalar | descDmaWrBytes |
Stats::Formula | totBandwidth |
Stats::Formula | totPackets |
Stats::Formula | totBytes |
Stats::Formula | totPacketRate |
Stats::Formula | txBandwidth |
Stats::Formula | rxBandwidth |
Stats::Formula | txPacketRate |
Stats::Formula | rxPacketRate |
Stats::Scalar | postedSwi |
Stats::Formula | coalescedSwi |
Stats::Scalar | totalSwi |
Stats::Scalar | postedRxIdle |
Stats::Formula | coalescedRxIdle |
Stats::Scalar | totalRxIdle |
Stats::Scalar | postedRxOk |
Stats::Formula | coalescedRxOk |
Stats::Scalar | totalRxOk |
Stats::Scalar | postedRxDesc |
Stats::Formula | coalescedRxDesc |
Stats::Scalar | totalRxDesc |
Stats::Scalar | postedTxOk |
Stats::Formula | coalescedTxOk |
Stats::Scalar | totalTxOk |
Stats::Scalar | postedTxIdle |
Stats::Formula | coalescedTxIdle |
Stats::Scalar | totalTxIdle |
Stats::Scalar | postedTxDesc |
Stats::Formula | coalescedTxDesc |
Stats::Scalar | totalTxDesc |
Stats::Scalar | postedRxOrn |
Stats::Formula | coalescedRxOrn |
Stats::Scalar | totalRxOrn |
Stats::Formula | coalescedTotal |
Stats::Scalar | postedInterrupts |
Stats::Scalar | droppedPackets |
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const PciBusAddr | _busAddr |
PCIConfig | config |
The current config space. More... | |
std::vector< MSIXTable > | msix_table |
MSIX Table and PBA Structures. More... | |
std::vector< MSIXPbaEntry > | msix_pba |
uint32_t | BARSize [6] |
The size of the BARs. More... | |
Addr | BARAddrs [6] |
The current address mapping of the BARs. More... | |
bool | legacyIO [6] |
Whether the BARs are really hardwired legacy IO locations. More... | |
PciHost::DeviceInterface | hostInterface |
Tick | pioDelay |
Tick | configDelay |
const int | PMCAP_BASE |
The capability list structures and base addresses. More... | |
const int | PMCAP_ID_OFFSET |
const int | PMCAP_PC_OFFSET |
const int | PMCAP_PMCS_OFFSET |
PMCAP | pmcap |
const int | MSICAP_BASE |
MSICAP | msicap |
const int | MSIXCAP_BASE |
const int | MSIXCAP_ID_OFFSET |
const int | MSIXCAP_MXC_OFFSET |
const int | MSIXCAP_MTAB_OFFSET |
const int | MSIXCAP_MPBA_OFFSET |
int | MSIX_TABLE_OFFSET |
int | MSIX_TABLE_END |
int | MSIX_PBA_OFFSET |
int | MSIX_PBA_END |
MSIXCAP | msixcap |
const int | PXCAP_BASE |
PXCAP | pxcap |
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DmaPort | dmaPort |
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System * | sys |
PioPort< PioDevice > | pioPort |
The pioPort that handles the requests for us and provides us requests that it sees. More... | |
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const SimObjectParams * | _params |
Cached copy of the object parameters. More... | |
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EventQueue * | eventq |
A pointer to this object's event queue. More... | |
Definition at line 54 of file i8254xGBe.hh.
typedef IGbEParams IGbE::Params |
Definition at line 510 of file i8254xGBe.hh.
IGbE::IGbE | ( | const Params * | params | ) |
Definition at line 58 of file i8254xGBe.cc.
References PacketFifo::clear(), iGbReg::Regs::ctrl, delayIntEvent(), eeAddrBits, iGbReg::Regs::eecd, eeDataBits, eeOpBits, eeOpcode, iGbReg::EEPROM_CSUM, EEPROM_SIZE, etherInt, iGbReg::Regs::fcrth, flash, htobe(), iGbReg::Regs::iam, iGbReg::Regs::imr, interEvent, lastInterrupt, macAddr, SimObject::name(), MipsISA::p, iGbReg::Regs::pba, radvEvent, radvProcess(), rdtrProcess(), regs, iGbReg::Regs::rlpml, iGbReg::Regs::rxdctl, rxDescCache, rxFifo, iGbReg::Regs::sts, iGbReg::Regs::sw_fw_sync, tadvEvent, tadvProcess(), iGbReg::Regs::tdwba, tick(), tickEvent, tidvEvent, tidvProcess(), txDescCache, txFifo, and RiscvISA::x.
Referenced by params(), and unserialize().
IGbE::~IGbE | ( | ) |
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inlineprivate |
Definition at line 175 of file i8254xGBe.hh.
References CPA::hwBegin(), and PioDevice::sys.
Referenced by ethRxPkt(), ethTxDone(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), rxStateMachine(), txStateMachine(), and txWire().
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inlineprivate |
Definition at line 185 of file i8254xGBe.hh.
References CPA::FL_NONE, CPA::hwDq(), and PioDevice::sys.
Referenced by IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), IGbE::TxDescCache::processContextDesc(), rxStateMachine(), and txWire().
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inlineprivate |
Definition at line 190 of file i8254xGBe.hh.
References CPA::FL_NONE, CPA::hwPq(), and PioDevice::sys.
Referenced by rxStateMachine(), txStateMachine(), and txWire().
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inlineprivate |
Definition at line 180 of file i8254xGBe.hh.
References CPA::FL_NONE, CPA::hwQ(), and PioDevice::sys.
Referenced by ethRxPkt(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), IGbE::TxDescCache::processContextDesc(), txStateMachine(), and txWire().
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inlineprivate |
Definition at line 195 of file i8254xGBe.hh.
References CPA::FL_NONE, CPA::hwRq(), and PioDevice::sys.
Referenced by txStateMachine().
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inlineprivate |
Definition at line 200 of file i8254xGBe.hh.
References CPA::FL_NONE, CPA::hwWe(), and PioDevice::sys.
Referenced by rxStateMachine(), txStateMachine(), and txWire().
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inlineprivate |
Definition at line 205 of file i8254xGBe.hh.
References CPA::FL_NONE, CPA::hwWf(), and PioDevice::sys.
Referenced by txStateMachine().
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private |
Check if all the draining things that need to occur have occured and handle the drain event if so.
Definition at line 2115 of file i8254xGBe.cc.
References DPRINTF, Draining, Drainable::drainState(), IGbE::RxDescCache::hasOutstandingEvents(), IGbE::TxDescCache::hasOutstandingEvents(), rxDescCache, rxTick, Drainable::signalDrainDone(), txDescCache, txFifoTick, and txTick.
Referenced by IGbE::TxDescCache::headerComplete(), intClock(), IGbE::RxDescCache::pktComplete(), and IGbE::TxDescCache::pktComplete().
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private |
Check and see if changes to the mask register have caused an interrupt to need to be sent or perhaps removed an interrupt cause.
Definition at line 789 of file i8254xGBe.cc.
References cpuClearInt(), cpuPostInt(), curTick(), EventManager::deschedule(), DPRINTF, iGbReg::Regs::icr, iGbReg::Regs::imr, interEvent, iGbReg::Regs::itr, SimClock::Int::ns, regs, EventManager::schedule(), Event::scheduled(), and ArmISA::t.
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private |
Clear the interupt line to the cpu.
Definition at line 777 of file i8254xGBe.cc.
References DPRINTF, iGbReg::Regs::icr, PciDevice::intrClear(), and regs.
Referenced by chkInterrupt().
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private |
Definition at line 733 of file i8254xGBe.cc.
References curTick(), EventManager::deschedule(), DPRINTF, iGbReg::Regs::icr, iGbReg::Regs::imr, interEvent, PciDevice::intrPost(), lastInterrupt, EtherDevice::postedInterrupts, radvEvent, rdtrEvent, regs, Event::scheduled(), tadvEvent, and tidvEvent.
Referenced by chkInterrupt(), delayIntEvent(), and postInterrupt().
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private |
Send an interrupt to the cpu.
Definition at line 726 of file i8254xGBe.cc.
References cpuPostInt().
Referenced by IGbE().
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overridevirtual |
Notify an object that it needs to drain its state.
If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.
Implements Drainable.
Definition at line 2079 of file i8254xGBe.cc.
References X86ISA::count, EventManager::deschedule(), DPRINTF, Drained, Draining, IGbE::RxDescCache::hasOutstandingEvents(), IGbE::TxDescCache::hasOutstandingEvents(), rxDescCache, rxTick, Event::scheduled(), tickEvent, txDescCache, txFifoTick, and txTick.
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overridevirtual |
Resume execution after a successful drain.
Reimplemented from Drainable.
Definition at line 2102 of file i8254xGBe.cc.
References DPRINTF, Drainable::drainResume(), restartClock(), rxTick, txFifoTick, and txTick.
bool IGbE::ethRxPkt | ( | EthPacketPtr | packet | ) |
Definition at line 2233 of file i8254xGBe.cc.
References anBegin(), anQ(), CPA::available(), cpa, DPRINTF, Draining, Drainable::drainState(), CPA::enabled(), CPA::FL_BAD, CPA::FL_NONE, CPA::hwDq(), CPA::hwWe(), iGbReg::IT_RXO, macAddr, System::numSystemsRunning, postInterrupt(), PacketFifo::push(), iGbReg::Regs::rctl, regs, restartClock(), EtherDevice::rxBytes, rxFifo, EtherDevice::rxPackets, rxTick, Event::scheduled(), PioDevice::sys, System::systemList, tickEvent, and txTick.
Referenced by IGbEInt::recvPacket().
void IGbE::ethTxDone | ( | ) |
Definition at line 2461 of file i8254xGBe.cc.
References anBegin(), IGbE::DescCache< T >::descLeft(), DPRINTF, Draining, Drainable::drainState(), inTick, restartClock(), txDescCache, txFifoTick, and txTick.
Referenced by IGbEInt::sendDone().
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overridevirtual |
Get a port with a given name and index.
This is used at binding time and returns a reference to a protocol-agnostic port.
if_name | Port name |
idx | Index in the case of a VectorPort |
Reimplemented from DmaDevice.
Definition at line 141 of file i8254xGBe.cc.
References etherInt, and DmaDevice::getPort().
Referenced by params().
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overridevirtual |
init() is called after all C++ SimObjects have been created and all ports are connected.
Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.
Reimplemented from DmaDevice.
Definition at line 134 of file i8254xGBe.cc.
References cpa, CPA::cpa(), and DmaDevice::init().
Referenced by params().
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inlineprivate |
Definition at line 164 of file i8254xGBe.hh.
References checkDrain(), SimClock::Int::ns, and restartClock().
Referenced by IGbE::RxDescCache::pktComplete(), and IGbE::TxDescCache::pktComplete().
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inline |
Definition at line 512 of file i8254xGBe.hh.
References SimObject::_params, getPort(), IGbE(), init(), InvalidPortID, and ~IGbE().
Referenced by write().
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private |
Write an interrupt into the interrupt pending register and check mask and interrupt limit timer before sending interrupt to CPU.
t | the type of interrupt we are posting |
now | should we ignore the interrupt limiting timer |
Definition at line 693 of file i8254xGBe.cc.
References cpuPostInt(), curTick(), EventManager::deschedule(), DPRINTF, iGbReg::Regs::icr, interEvent, iGbReg::Regs::itr, lastInterrupt, SimClock::Int::ns, regs, EventManager::schedule(), Event::scheduled(), and ArmISA::t.
Referenced by IGbE::TxDescCache::actionAfterWb(), ethRxPkt(), IGbE::RxDescCache::pktComplete(), radvProcess(), rdtrProcess(), read(), rxStateMachine(), tadvProcess(), tidvProcess(), txStateMachine(), and write().
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inlineprivate |
Definition at line 102 of file i8254xGBe.hh.
References DPRINTF, iGbReg::IT_RXT, postInterrupt(), rxDescCache, and IGbE::DescCache< T >::writeback().
Referenced by IGbE().
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inlineprivate |
Definition at line 92 of file i8254xGBe.hh.
References DPRINTF, iGbReg::IT_RXT, postInterrupt(), rxDescCache, and IGbE::DescCache< T >::writeback().
Referenced by IGbE().
Pure virtual function that the device must implement.
Called when a read command is recieved by the port.
pkt | Packet describing this request |
Implements PioDevice.
Definition at line 168 of file i8254xGBe.cc.
References chkInterrupt(), iGbReg::Regs::ctrl, iGbReg::Regs::ctrl_ext, DPRINTF, iGbReg::Regs::eecd, iGbReg::Regs::eerd, iGbReg::Regs::fcrth, iGbReg::Regs::fcrtl, iGbReg::Regs::fcttv, iGbReg::Regs::fwsm, Packet::getAddr(), PciDevice::getBAR(), Packet::getSize(), iGbReg::Regs::iam, iGbReg::Regs::icr, iGbReg::Regs::imr, IN_RANGE, iGbReg::IT_RXT, iGbReg::Regs::itr, Packet::makeAtomicResponse(), iGbReg::Regs::manc, ArmISA::mask, iGbReg::Regs::mdic, iGbReg::MULTICAST_TABLE_SIZE, panic, iGbReg::Regs::pba, PciDevice::pioDelay, postInterrupt(), iGbReg::Regs::radv, iGbReg::Regs::rctl, iGbReg::RCV_ADDRESS_TABLE_SIZE, iGbReg::Regs::rdba, iGbReg::Regs::rdh, iGbReg::Regs::rdlen, iGbReg::Regs::rdt, iGbReg::Regs::rdtr, iGbReg::REG_CRCERRS, iGbReg::REG_CTRL, iGbReg::REG_CTRL_EXT, iGbReg::REG_EECD, iGbReg::REG_EERD, iGbReg::REG_EICR, iGbReg::REG_FCRTH, iGbReg::REG_FCRTL, iGbReg::REG_FCTTV, iGbReg::REG_FWSM, iGbReg::REG_ICR, iGbReg::REG_ITR, iGbReg::REG_LEDCTL, iGbReg::REG_MANC, iGbReg::REG_MDIC, iGbReg::REG_MTA, iGbReg::REG_PBA, iGbReg::REG_RADV, iGbReg::REG_RAL, iGbReg::REG_RCTL, iGbReg::REG_RDBAH, iGbReg::REG_RDBAL, iGbReg::REG_RDH, iGbReg::REG_RDLEN, iGbReg::REG_RDT, iGbReg::REG_RDTR, iGbReg::REG_RFCTL, iGbReg::REG_RLPML, iGbReg::REG_RXCSUM, iGbReg::REG_RXDCTL, iGbReg::REG_SRRCTL, iGbReg::REG_STATUS, iGbReg::REG_SWFWSYNC, iGbReg::REG_SWSM, iGbReg::REG_TADV, iGbReg::REG_TCTL, iGbReg::REG_TDBAH, iGbReg::REG_TDBAL, iGbReg::REG_TDH, iGbReg::REG_TDLEN, iGbReg::REG_TDT, iGbReg::REG_TDWBAH, iGbReg::REG_TDWBAL, iGbReg::REG_TIDV, iGbReg::REG_TXDCA_CTL, iGbReg::REG_TXDCTL, iGbReg::REG_VFTA, iGbReg::REG_WUC, iGbReg::REG_WUFC, iGbReg::REG_WUS, regs, iGbReg::Regs::rfctl, iGbReg::Regs::rlpml, iGbReg::Regs::rxcsum, iGbReg::Regs::rxdctl, rxDescCache, Packet::setLE(), iGbReg::Regs::srrctl, iGbReg::STATS_REGS_SIZE, iGbReg::Regs::sts, iGbReg::Regs::sw_fw_sync, iGbReg::Regs::swsm, iGbReg::Regs::tadv, iGbReg::Regs::tctl, iGbReg::Regs::tdba, iGbReg::Regs::tdh, iGbReg::Regs::tdlen, iGbReg::Regs::tdt, iGbReg::Regs::tdwba, iGbReg::Regs::tidv, iGbReg::Regs::txdca_ctl, iGbReg::Regs::txdctl, iGbReg::VLAN_FILTER_TABLE_SIZE, and IGbE::DescCache< T >::writeback().
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This function is used to restart the clock so it can handle things like draining and resume in one place.
Definition at line 2071 of file i8254xGBe.cc.
References Clocked::clockEdge(), Drainable::drainState(), Running, rxTick, EventManager::schedule(), Event::scheduled(), tickEvent, txFifoTick, and txTick.
Referenced by drainResume(), IGbE::RxDescCache::enableSm(), IGbE::TxDescCache::enableSm(), ethRxPkt(), ethTxDone(), intClock(), and write().
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Definition at line 2281 of file i8254xGBe.cc.
References anBegin(), anDq(), IGbE::DescCache< T >::annUnusedCacheQ, anPq(), anWe(), DmaDevice::cacheBlockSize(), IGbE::DescCache< T >::descLeft(), IGbE::DescCache< iGbReg::TxDesc >::descLeft(), IGbE::DescCache< T >::descUnused(), IGbE::DescCache< T >::descUsed(), DPRINTF, PacketFifo::empty(), IGbE::DescCache< T >::fetchDescriptors(), PacketFifo::front(), iGbReg::IT_RXDMT, IGbE::RxDescCache::packetDone(), pktOffset, PacketFifo::pop(), postInterrupt(), iGbReg::Regs::rctl, iGbReg::Regs::rdlen, regs, iGbReg::Regs::rxdctl, rxDescCache, rxDmaPacket, rxFifo, rxTick, ULL, IGbE::DescCache< T >::writeback(), and IGbE::RxDescCache::writePacket().
Referenced by tick().
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Serialize an object.
Output an object's state into the current checkpoint section.
cp | Checkpoint state |
Implements Serializable.
Definition at line 2477 of file i8254xGBe.cc.
References eeAddr, eeAddrBits, eeDataBits, eeOpBits, eeOpcode, iGbReg::EEPROM_SIZE, flash, interEvent, lastInterrupt, pktOffset, radvEvent, rdtrEvent, regs, rxDescCache, rxFifo, Event::scheduled(), PacketFifo::serialize(), PciDevice::serialize(), iGbReg::Regs::serialize(), SERIALIZE_ARRAY, SERIALIZE_SCALAR, Serializable::serializeSection(), tadvEvent, tidvEvent, txDescCache, txFifo, txPacket, and Event::when().
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Definition at line 112 of file i8254xGBe.hh.
References DPRINTF, iGbReg::IT_TXDW, postInterrupt(), txDescCache, and IGbE::DescCache< T >::writeback().
Referenced by IGbE().
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Definition at line 2433 of file i8254xGBe.cc.
References Clocked::clockPeriod(), curTick(), DPRINTF, inTick, rxStateMachine(), rxTick, EventManager::schedule(), tickEvent, txFifoTick, txStateMachine(), txTick, and txWire().
Referenced by IGbE().
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Definition at line 122 of file i8254xGBe.hh.
References DPRINTF, iGbReg::IT_TXDW, postInterrupt(), txDescCache, and IGbE::DescCache< T >::writeback().
Referenced by IGbE().
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Definition at line 2131 of file i8254xGBe.cc.
References anBegin(), IGbE::DescCache< T >::annUnusedCacheQ, anPq(), anQ(), anRq(), anWe(), anWf(), PacketFifo::avail(), DmaDevice::cacheBlockSize(), IGbE::DescCache< T >::descLeft(), IGbE::DescCache< T >::descUnused(), DPRINTF, Draining, Drainable::drainState(), IGbE::DescCache< T >::fetchDescriptors(), IGbE::TxDescCache::getPacketData(), IGbE::TxDescCache::getPacketSize(), iGbReg::IT_TXDLOW, iGbReg::IT_TXQE, IGbE::TxDescCache::packetAvailable(), IGbE::TxDescCache::packetMultiDesc(), IGbE::TxDescCache::packetWaiting(), postInterrupt(), IGbE::TxDescCache::processContextDesc(), PacketFifo::push(), regs, PacketFifo::reserve(), IGbE::DescCache< iGbReg::TxDesc >::size, iGbReg::Regs::tctl, iGbReg::Regs::txdctl, txDescCache, txFifo, txFifoTick, txPacket, txTick, and IGbE::DescCache< T >::writeback().
Referenced by tick().
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Definition at line 2398 of file i8254xGBe.cc.
References anBegin(), anDq(), anPq(), anQ(), anWe(), PacketFifo::avail(), DPRINTF, DTRACE, PacketFifo::empty(), etherInt, PacketFifo::front(), iGbReg::TxdOp::ip(), PacketFifo::pop(), EtherInt::sendPacket(), EtherDevice::txBytes, txFifo, txFifoTick, and EtherDevice::txPackets.
Referenced by tick().
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Unserialize an object.
Read an object's state from the current checkpoint section.
cp | Checkpoint state |
Implements Serializable.
Definition at line 2528 of file i8254xGBe.cc.
References eeAddr, eeAddrBits, eeDataBits, eeOpBits, eeOpcode, iGbReg::EEPROM_SIZE, flash, IGbE(), interEvent, lastInterrupt, pktOffset, radvEvent, rdtrEvent, regs, rxDescCache, rxFifo, rxTick, EventManager::schedule(), tadvEvent, tidvEvent, txDescCache, txFifo, txFifoTick, txPacket, txTick, PacketFifo::unserialize(), PciDevice::unserialize(), iGbReg::Regs::unserialize(), UNSERIALIZE_ARRAY, UNSERIALIZE_SCALAR, and Serializable::unserializeSection().
Pure virtual function that the device must implement.
Called when a write command is recieved by the port.
pkt | Packet describing this request |
Implements PioDevice.
Definition at line 356 of file i8254xGBe.cc.
References IGbE::DescCache< T >::areaChanged(), bits(), chkInterrupt(), PacketFifo::clear(), IGbE::TxDescCache::completionWriteback(), iGbReg::Regs::ctrl, iGbReg::Regs::ctrl_ext, DPRINTF, Drainable::drainState(), eeAddr, eeAddrBits, iGbReg::Regs::eecd, eeDataBits, eeOpBits, eeOpcode, iGbReg::EEPROM_RDSR_OPCODE_SPI, iGbReg::EEPROM_READ_OPCODE_SPI, EEPROM_SIZE, iGbReg::Regs::eerd, iGbReg::Regs::fcrth, iGbReg::Regs::fcrtl, iGbReg::Regs::fcttv, IGbE::DescCache< T >::fetchDescriptors(), flash, iGbReg::Regs::fwsm, Packet::getAddr(), PciDevice::getBAR(), Packet::getLE(), Packet::getSize(), iGbReg::Regs::iam, iGbReg::Regs::icr, iGbReg::Regs::imr, IN_RANGE, iGbReg::Regs::itr, Packet::makeAtomicResponse(), iGbReg::Regs::manc, ArmISA::mask, iGbReg::Regs::mdic, iGbReg::MULTICAST_TABLE_SIZE, panic, params(), iGbReg::Regs::pba, iGbReg::PHY_AGC, iGbReg::PHY_EPID, iGbReg::PHY_EPSTATUS, iGbReg::PHY_GSTATUS, iGbReg::PHY_PID, iGbReg::PHY_PSTATUS, PciDevice::pioDelay, postInterrupt(), iGbReg::Regs::radv, iGbReg::Regs::rctl, iGbReg::RCV_ADDRESS_TABLE_SIZE, iGbReg::Regs::rdba, iGbReg::Regs::rdh, iGbReg::Regs::rdlen, iGbReg::Regs::rdt, iGbReg::Regs::rdtr, iGbReg::REG_AIFS, iGbReg::REG_CTRL, iGbReg::REG_CTRL_EXT, iGbReg::REG_EECD, iGbReg::REG_EERD, iGbReg::REG_FCAH, iGbReg::REG_FCAL, iGbReg::REG_FCRTH, iGbReg::REG_FCRTL, iGbReg::REG_FCT, iGbReg::REG_FCTTV, iGbReg::REG_IAM, iGbReg::REG_ICR, iGbReg::REG_ICS, iGbReg::REG_IMC, iGbReg::REG_IMS, iGbReg::REG_ITR, iGbReg::REG_IVAR0, iGbReg::REG_LEDCTL, iGbReg::REG_MANC, iGbReg::REG_MDIC, iGbReg::REG_MTA, iGbReg::REG_PBA, iGbReg::REG_RADV, iGbReg::REG_RAL, iGbReg::REG_RCTL, iGbReg::REG_RDBAH, iGbReg::REG_RDBAL, iGbReg::REG_RDH, iGbReg::REG_RDLEN, iGbReg::REG_RDT, iGbReg::REG_RDTR, iGbReg::REG_RFCTL, iGbReg::REG_RLPML, iGbReg::REG_RXCSUM, iGbReg::REG_RXDCTL, iGbReg::REG_SRRCTL, iGbReg::REG_STATUS, iGbReg::REG_SWFWSYNC, iGbReg::REG_SWSM, iGbReg::REG_TADV, iGbReg::REG_TCTL, iGbReg::REG_TDBAH, iGbReg::REG_TDBAL, iGbReg::REG_TDH, iGbReg::REG_TDLEN, iGbReg::REG_TDT, iGbReg::REG_TDWBAH, iGbReg::REG_TDWBAL, iGbReg::REG_TIDV, iGbReg::REG_TIPG, iGbReg::REG_TXDCA_CTL, iGbReg::REG_TXDCTL, iGbReg::REG_VET, iGbReg::REG_VFTA, iGbReg::REG_WUC, iGbReg::REG_WUFC, iGbReg::REG_WUS, regs, IGbE::DescCache< T >::reset(), restartClock(), iGbReg::Regs::rfctl, iGbReg::Regs::rlpml, Running, iGbReg::Regs::rxcsum, iGbReg::Regs::rxdctl, rxDescCache, rxFifo, rxTick, iGbReg::Regs::srrctl, iGbReg::Regs::sts, iGbReg::Regs::sw_fw_sync, iGbReg::Regs::swsm, iGbReg::Regs::tadv, iGbReg::Regs::tctl, iGbReg::Regs::tdba, iGbReg::Regs::tdh, iGbReg::Regs::tdlen, iGbReg::Regs::tdt, iGbReg::Regs::tdwba, iGbReg::Regs::tidv, iGbReg::Regs::txdca_ctl, iGbReg::Regs::txdctl, txDescCache, txTick, X86ISA::val, iGbReg::VLAN_FILTER_TABLE_SIZE, and warn.
Write to the PCI config space data that is stored locally.
This may be overridden by the device but at some point it will eventually call this for normal operations that it does not need to override.
pkt | packet containing the write the offset into config space |
Reimplemented from PciDevice.
Definition at line 149 of file i8254xGBe.cc.
References PciDevice::configDelay, Packet::getAddr(), ArmISA::offset, panic, PCI_CONFIG_SIZE, PCI_DEVICE_SPECIFIC, and PciDevice::writeConfig().
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Definition at line 393 of file i8254xGBe.hh.
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Definition at line 505 of file i8254xGBe.hh.
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Definition at line 58 of file i8254xGBe.hh.
Referenced by ethRxPkt(), and init().
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Definition at line 65 of file i8254xGBe.hh.
Referenced by serialize(), unserialize(), and write().
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Definition at line 64 of file i8254xGBe.hh.
Referenced by IGbE(), serialize(), unserialize(), and write().
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Definition at line 64 of file i8254xGBe.hh.
Referenced by IGbE(), serialize(), unserialize(), and write().
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Definition at line 64 of file i8254xGBe.hh.
Referenced by IGbE(), serialize(), unserialize(), and write().
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Definition at line 65 of file i8254xGBe.hh.
Referenced by IGbE(), serialize(), unserialize(), and write().
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Definition at line 88 of file i8254xGBe.hh.
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Definition at line 87 of file i8254xGBe.hh.
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Definition at line 66 of file i8254xGBe.hh.
Referenced by IGbE(), serialize(), unserialize(), and write().
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Definition at line 158 of file i8254xGBe.hh.
Referenced by chkInterrupt(), cpuPostInt(), IGbE(), postInterrupt(), serialize(), and unserialize().
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Definition at line 76 of file i8254xGBe.hh.
Referenced by ethTxDone(), and tick().
Tick IGbE::lastInterrupt |
Definition at line 523 of file i8254xGBe.hh.
Referenced by cpuPostInt(), IGbE(), postInterrupt(), serialize(), and unserialize().
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Definition at line 135 of file i8254xGBe.hh.
Referenced by ethRxPkt(), and IGbE().
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Definition at line 84 of file i8254xGBe.hh.
Referenced by rxStateMachine(), serialize(), and unserialize().
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Definition at line 109 of file i8254xGBe.hh.
Referenced by cpuPostInt(), IGbE(), IGbE::RxDescCache::pktComplete(), serialize(), and unserialize().
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Definition at line 99 of file i8254xGBe.hh.
Referenced by cpuPostInt(), IGbE::RxDescCache::pktComplete(), serialize(), and unserialize().
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Definition at line 61 of file i8254xGBe.hh.
Referenced by IGbE::TxDescCache::actionAfterWb(), chkInterrupt(), cpuClearInt(), cpuPostInt(), IGbE::RxDescCache::descBase(), IGbE::TxDescCache::descBase(), IGbE::RxDescCache::descHead(), IGbE::TxDescCache::descHead(), IGbE::RxDescCache::descLen(), IGbE::TxDescCache::descLen(), IGbE::RxDescCache::descTail(), IGbE::TxDescCache::descTail(), ethRxPkt(), IGbE(), IGbE::RxDescCache::pktComplete(), IGbE::TxDescCache::pktComplete(), postInterrupt(), read(), rxStateMachine(), serialize(), txStateMachine(), unserialize(), IGbE::RxDescCache::updateHead(), IGbE::TxDescCache::updateHead(), write(), and IGbE::RxDescCache::writePacket().
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Definition at line 395 of file i8254xGBe.hh.
Referenced by checkDrain(), drain(), IGbE(), radvProcess(), rdtrProcess(), read(), rxStateMachine(), serialize(), unserialize(), and write().
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Definition at line 81 of file i8254xGBe.hh.
Referenced by rxStateMachine().
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Definition at line 69 of file i8254xGBe.hh.
Referenced by ethRxPkt(), IGbE(), rxStateMachine(), serialize(), unserialize(), and write().
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Definition at line 77 of file i8254xGBe.hh.
Referenced by checkDrain(), drain(), drainResume(), IGbE::RxDescCache::enableSm(), ethRxPkt(), IGbE::RxDescCache::fetchAfterWb(), restartClock(), rxStateMachine(), tick(), unserialize(), and write().
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Definition at line 89 of file i8254xGBe.hh.
Referenced by IGbE::RxDescCache::writePacket().
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Definition at line 119 of file i8254xGBe.hh.
Referenced by cpuPostInt(), IGbE(), IGbE::TxDescCache::pktComplete(), serialize(), and unserialize().
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Definition at line 132 of file i8254xGBe.hh.
Referenced by drain(), ethRxPkt(), IGbE(), restartClock(), and tick().
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Definition at line 128 of file i8254xGBe.hh.
Referenced by cpuPostInt(), IGbE(), IGbE::TxDescCache::pktComplete(), serialize(), and unserialize().
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Definition at line 507 of file i8254xGBe.hh.
Referenced by checkDrain(), drain(), ethTxDone(), IGbE(), serialize(), tadvProcess(), tidvProcess(), txStateMachine(), unserialize(), and write().
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Definition at line 70 of file i8254xGBe.hh.
Referenced by IGbE(), serialize(), txStateMachine(), txWire(), and unserialize().
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Definition at line 79 of file i8254xGBe.hh.
Referenced by checkDrain(), drain(), drainResume(), ethTxDone(), restartClock(), tick(), txStateMachine(), txWire(), and unserialize().
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Definition at line 73 of file i8254xGBe.hh.
Referenced by serialize(), txStateMachine(), and unserialize().
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Definition at line 89 of file i8254xGBe.hh.
Referenced by IGbE::TxDescCache::getPacketData().
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Definition at line 78 of file i8254xGBe.hh.
Referenced by checkDrain(), drain(), drainResume(), IGbE::TxDescCache::enableSm(), ethRxPkt(), ethTxDone(), IGbE::TxDescCache::fetchAfterWb(), restartClock(), tick(), txStateMachine(), unserialize(), and write().
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Definition at line 88 of file i8254xGBe.hh.
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Definition at line 87 of file i8254xGBe.hh.