ArmISA::TLB Class Reference

#include <tlb.hh>

Inheritance diagram for ArmISA::TLB:

Public Types
enum	ArmFlags {   AlignmentMask = 0x7, AlignByte = 0x0, AlignHalfWord = 0x1, AlignWord = 0x2,   AlignDoubleWord = 0x3, AlignQuadWord = 0x4, AlignOctWord = 0x5, AllowUnaligned = 0x8,   UserMode = 0x10 }
enum	ArmTranslationType {   NormalTran = 0, S1CTran = 0x1, HypMode = 0x2, S1S2NsTran = 0x4,   S1E0Tran = 0x8, S1E1Tran = 0x10, S1E2Tran = 0x20, S1E3Tran = 0x40,   S12E0Tran = 0x80, S12E1Tran = 0x100 }
Public Types inherited from BaseTLB
enum	Mode { Read, Write, Execute }
Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
	TLB (const ArmTLBParams *p)
	TLB (const Params *p, int _size, TableWalker *_walker)
TlbEntry *	lookup (Addr vpn, uint16_t asn, uint8_t vmid, bool hyp, bool secure, bool functional, bool ignore_asn, ExceptionLevel target_el)
	Lookup an entry in the TLB. More...
virtual	~TLB ()
void	takeOverFrom (BaseTLB *otlb) override
	Take over from an old tlb context. More...
void	init () override
	setup all the back pointers More...
void	setTestInterface (SimObject *ti)
TableWalker *	getTableWalker ()
void	setMMU (Stage2MMU *m, MasterID master_id)
int	getsize () const
void	insert (Addr vaddr, TlbEntry &pte)
Fault	getTE (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, ArmTranslationType tranType)
Fault	getResultTe (TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe)
Fault	checkPermissions (TlbEntry *te, const RequestPtr &req, Mode mode)
Fault	checkPermissions64 (TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc)
bool	checkPAN (ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode)
void	flushAllSecurity (bool secure_lookup, ExceptionLevel target_el, bool ignore_el=false)
	Reset the entire TLB. More...
void	flushAllNs (ExceptionLevel target_el, bool ignore_el=false)
	Remove all entries in the non secure world, depending on whether they were allocated in hyp mode or not. More...
void	flushAll () override
	Reset the entire TLB. More...
void	flushMvaAsid (Addr mva, uint64_t asn, bool secure_lookup, ExceptionLevel target_el)
	Remove any entries that match both a va and asn. More...
void	flushAsid (uint64_t asn, bool secure_lookup, ExceptionLevel target_el)
	Remove any entries that match the asn. More...
void	flushMva (Addr mva, bool secure_lookup, ExceptionLevel target_el)
	Remove all entries that match the va regardless of asn. More...
void	flushIpaVmid (Addr ipa, bool secure_lookup, ExceptionLevel target_el)
	Invalidate all entries in the stage 2 TLB that match the given ipa and the current VMID. More...
Fault	trickBoxCheck (const RequestPtr &req, Mode mode, TlbEntry::DomainType domain)
Fault	walkTrickBoxCheck (Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level)
void	printTlb () const
void	demapPage (Addr vaddr, uint64_t asn) override
bool	translateFunctional (ThreadContext *tc, Addr vaddr, Addr &paddr)
	Do a functional lookup on the TLB (for debugging) and don't modify any internal state. More...
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, Mode mode, ArmTranslationType tranType)
	Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state. More...
Fault	translateFunctional (const RequestPtr &req, ThreadContext *tc, Mode mode) override
void	setAttr (uint64_t attr)
	Accessor functions for memory attributes for last accessed TLB entry. More...
uint64_t	getAttr () const
Fault	translateMmuOff (ThreadContext *tc, const RequestPtr &req, Mode mode, TLB::ArmTranslationType tranType, Addr vaddr, bool long_desc_format)
Fault	translateMmuOn (ThreadContext *tc, const RequestPtr &req, Mode mode, Translation *translation, bool &delay, bool timing, bool functional, Addr vaddr, ArmFault::TranMethod tranMethod)
Fault	translateFs (const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, ArmTranslationType tranType, bool functional=false)
Fault	translateSe (const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing)
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode, ArmTranslationType tranType)
Fault	translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode) override
void	translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType)
void	translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override
Fault	translateComplete (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, ArmTranslationType tranType, bool callFromS2)
Fault	finalizePhysical (const RequestPtr &req, ThreadContext *tc, Mode mode) const override
	Do post-translation physical address finalization. More...
void	drainResume () override
	Resume execution after a successful drain. More...
void	regStats () override
	Callback to set stat parameters. More...
void	regProbePoints () override
	Register probe points for this object. More...
Port *	getTableWalkerPort () override
	Get the table walker port. More...
const Params *	params () const
void	invalidateMiscReg ()
Fault	testTranslation (const RequestPtr &req, Mode mode, TlbEntry::DomainType domain)
Fault	testWalk (Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level)
Public Member Functions inherited from BaseTLB
void	memInvalidate ()
	Invalidate the contents of memory buffers. More...
Public Member Functions inherited from SimObject
virtual	~SimObject ()
virtual const std::string	name () const
virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...
virtual void	initState ()
	initState() is called on each SimObject when not restoring from a checkpoint. More...
virtual void	regProbeListeners ()
	Register probe listeners for this object. More...
ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...
virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID)
	Get a port with a given name and index. More...
virtual void	startup ()
	startup() is the final initialization call before simulation. More...
DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...
virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...
void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...
void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...
const Params *	params () const
	SimObject (const Params *_params)
Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const
void	schedule (Event &event, Tick when)
void	deschedule (Event &event)
void	reschedule (Event &event, Tick when, bool always=false)
void	schedule (Event *event, Tick when)
void	deschedule (Event *event)
void	reschedule (Event *event, Tick when, bool always=false)
void	wakeupEventQueue (Tick when=(Tick) -1)
void	setCurTick (Tick newVal)
	EventManager (EventManager &em)
	EventManager (EventManager *em)
	EventManager (EventQueue *eq)
Public Member Functions inherited from Serializable
	Serializable ()
virtual	~Serializable ()
void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...
void	serializeSection (CheckpointOut &cp, const std::string &name) const
void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...
void	unserializeSection (CheckpointIn &cp, const std::string &name)
Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...
virtual void	notifyFork ()
	Notify a child process of a fork. More...
Public Member Functions inherited from Stats::Group
	Group (Group *parent, const char *name=nullptr)
	Construct a new statistics group. More...
virtual	~Group ()
virtual void	resetStats ()
	Callback to reset stats. More...
virtual void	preDumpStats ()
	Callback before stats are dumped. More...
void	addStat (Stats::Info *info)
	Register a stat with this group. More...
const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...
const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...
void	addStatGroup (const char *name, Group *block)
	Add a stat block as a child of this block. More...
const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...
	Group ()=delete
	Group (const Group &)=delete
Group &	operator= (const Group &)=delete

Static Public Member Functions
static ExceptionLevel	tranTypeEL (CPSR cpsr, ArmTranslationType type)
	Determine the EL to use for the purpose of a translation given a specific translation type. More...
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...
static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...
Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...
static void	serializeAll (const std::string &cpt_dir)
static void	unserializeGlobals (CheckpointIn &cp)

Protected Member Functions
void	updateMiscReg (ThreadContext *tc, ArmTranslationType tranType=NormalTran)
Protected Member Functions inherited from BaseTLB
	BaseTLB (const Params *p)
Protected Member Functions inherited from Drainable
	Drainable ()
virtual	~Drainable ()
void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Attributes
TlbEntry *	table
int	size
bool	isStage2
bool	stage2Req
bool	stage2DescReq
uint64_t	_attr
bool	directToStage2
TableWalker *	tableWalker
TLB *	stage2Tlb
Stage2MMU *	stage2Mmu
TlbTestInterface *	test
Stats::Scalar	instHits
Stats::Scalar	instMisses
Stats::Scalar	readHits
Stats::Scalar	readMisses
Stats::Scalar	writeHits
Stats::Scalar	writeMisses
Stats::Scalar	inserts
Stats::Scalar	flushTlb
Stats::Scalar	flushTlbMva
Stats::Scalar	flushTlbMvaAsid
Stats::Scalar	flushTlbAsid
Stats::Scalar	flushedEntries
Stats::Scalar	alignFaults
Stats::Scalar	prefetchFaults
Stats::Scalar	domainFaults
Stats::Scalar	permsFaults
Stats::Formula	readAccesses
Stats::Formula	writeAccesses
Stats::Formula	instAccesses
Stats::Formula	hits
Stats::Formula	misses
Stats::Formula	accesses
ProbePoints::PMUUPtr	ppRefills
	PMU probe for TLB refills. More...
int	rangeMRU
CPSR	cpsr
bool	aarch64
ExceptionLevel	aarch64EL
SCTLR	sctlr
SCR	scr
bool	isPriv
bool	isSecure
bool	isHyp
TTBCR	ttbcr
uint16_t	asid
uint8_t	vmid
PRRR	prrr
NMRR	nmrr
HCR	hcr
uint32_t	dacr
bool	miscRegValid
ContextID	miscRegContext
ArmTranslationType	curTranType
bool	haveLPAE
bool	haveVirtualization
bool	haveLargeAsid64
AddrRange	m5opRange
Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...
Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Private Member Functions
void	_flushMva (Addr mva, uint64_t asn, bool secure_lookup, bool ignore_asn, ExceptionLevel target_el)
	Remove any entries that match both a va and asn. More...

Detailed Description

Definition at line 100 of file tlb.hh.

Member Enumeration Documentation

ArmFlags

enum ArmISA::TLB::ArmFlags

Enumerator
AlignmentMask
AlignByte
AlignHalfWord
AlignWord
AlignDoubleWord
AlignQuadWord
AlignOctWord
AllowUnaligned
UserMode

Definition at line 103 of file tlb.hh.

ArmTranslationType

enum ArmISA::TLB::ArmTranslationType

Enumerator
NormalTran
S1CTran
HypMode
S1S2NsTran
S1E0Tran
S1E1Tran
S1E2Tran
S1E3Tran
S12E0Tran
S12E1Tran

Definition at line 118 of file tlb.hh.

Constructor & Destructor Documentation

TLB() [1/2]

TLB::TLB

(

const ArmTLBParams *

p

)

Definition at line 73 of file tlb.cc.

References haveLargeAsid64, ArmISA::TableWalker::haveLargeAsid64(), haveLPAE, ArmISA::TableWalker::haveLPAE(), haveVirtualization, ArmISA::TableWalker::haveVirtualization(), m5opRange, System::m5opRange(), ArmISA::TableWalker::setTlb(), and tableWalker.

TLB() [2/2]

ArmISA::TLB::TLB	(	const Params *	p,
		int	_size,
		TableWalker *	_walker
	)

~TLB()

TLB::~TLB ( )

virtual

Definition at line 95 of file tlb.cc.

References table.

Member Function Documentation

_flushMva()

void TLB::_flushMva ( Addr  mva, uint64_t  asn, bool  secure_lookup, bool  ignore_asn, ExceptionLevel  target_el  )

private

Remove any entries that match both a va and asn.

Parameters

mva	virtual address to flush
asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world
ignore_asn	if the flush should ignore the asn

Definition at line 351 of file tlb.cc.

References DPRINTF, ArmISA::EL2, flushedEntries, lookup(), ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), ArmISA::te, ArmISA::TlbEntry::valid, and vmid.

Referenced by flushIpaVmid(), flushMva(), and flushMvaAsid().

checkPAN()

bool TLB::checkPAN	(	ThreadContext *	tc,
		uint8_t	ap,
		const RequestPtr &	req,
		Mode	mode
	)

Definition at line 988 of file tlb.cc.

References Request::CACHE_BLOCK_ZERO, cpsr, BaseTLB::Execute, ArmISA::MISCREG_ID_AA64MMFR1_EL1, and ThreadContext::readMiscReg().

Referenced by checkPermissions64().

checkPermissions()

Fault TLB::checkPermissions	(	TlbEntry *	te,
		const RequestPtr &	req,
		Mode	mode
	)

Definition at line 576 of file tlb.cc.

References alignFaults, ArmISA::ArmFault::AlignmentFault, AlignmentMask, ArmISA::TlbEntry::ap, dacr, ArmISA::TlbEntry::domain, domainFaults, ArmISA::ArmFault::DomainLL, DPRINTF, BaseTLB::Execute, ArmISA::TlbEntry::hap, hcr, isPriv, isSecure, isStage2, ArmISA::TlbEntry::longDescFormat, ArmISA::TlbEntry::lookupLevel, ArmISA::ArmFault::LpaeTran, ArmISA::mask, ArmISA::TlbEntry::mtype, ArmISA::TlbEntry::NoAccess, NoFault, ArmISA::TlbEntry::nonCacheable, ArmISA::TlbEntry::Normal, ArmISA::TlbEntry::ns, panic, ArmISA::ArmFault::PermissionLL, permsFaults, ArmISA::ArmFault::PrefetchUncacheable, ArmISA::TlbEntry::pxn, scr, sctlr, UserMode, MipsISA::vaddr, ArmISA::ArmFault::VmsaTran, BaseTLB::Write, and ArmISA::TlbEntry::xn.

Referenced by getResultTe(), and ArmISA::Stage2LookUp::getTe().

checkPermissions64()

Fault TLB::checkPermissions64	(	TlbEntry *	te,
		const RequestPtr &	req,
		Mode	mode,
		ThreadContext *	tc
	)

Definition at line 754 of file tlb.cc.

References aarch64, aarch64EL, alignFaults, ArmISA::ArmFault::AlignmentFault, AlignmentMask, ArmISA::TlbEntry::ap, checkPAN(), curTranType, ArmISA::TlbEntry::domain, DPRINTF, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, BaseTLB::Execute, ArmISA::TlbEntry::hap, ArmSystem::haveVirtualization(), hcr, isPriv, isStage2, ArmISA::TlbEntry::lookupLevel, ArmISA::ArmFault::LpaeTran, M5_FALLTHROUGH, ArmISA::mask, ArmISA::TlbEntry::mtype, ArmISA::TlbEntry::NoAccess, NoFault, ArmISA::TlbEntry::nonCacheable, ArmISA::TlbEntry::Normal, ArmISA::TlbEntry::ns, RiscvISA::perm, ArmISA::ArmFault::PermissionLL, permsFaults, ArmISA::ArmFault::PrefetchUncacheable, ArmISA::purifyTaggedAddr(), ArmISA::TlbEntry::pxn, MipsISA::r, scr, sctlr, ttbcr, updateMiscReg(), UserMode, MipsISA::vaddr, MipsISA::w, BaseTLB::Write, RiscvISA::x, and ArmISA::TlbEntry::xn.

Referenced by getResultTe(), and ArmISA::Stage2LookUp::getTe().

demapPage()

void ArmISA::TLB::demapPage ( Addr  vaddr, uint64_t  asn  )

inlineoverridevirtual

Implements BaseTLB.

Definition at line 305 of file tlb.hh.

References panic.

drainResume()

void TLB::drainResume ( )

overridevirtual

Resume execution after a successful drain.

Reimplemented from Drainable.

Definition at line 381 of file tlb.cc.

References miscRegValid.

finalizePhysical()

Fault TLB::finalizePhysical ( const RequestPtr &  req, ThreadContext *  tc, Mode  mode  ) const

overridevirtual

Do post-translation physical address finalization.

This method is used by some architectures that need post-translation massaging of physical addresses. For example, X86 uses this to remap physical addresses in the APIC range to a range of physical memory not normally available to real x86 implementations.

Parameters

req	Request to updated in-place.
tc	Thread context that created the request.
mode	Request type (read/write/execute).

Returns

A fault on failure, NoFault otherwise.

Implements BaseTLB.

Definition at line 133 of file tlb.cc.

References AddrRange::contains(), PseudoInst::decodeAddrOffset(), m5opRange, NoFault, BaseTLB::Read, Packet::setLE(), and AddrRange::start().

Referenced by translateMmuOn(), and translateSe().

flushAll()

void ArmISA::TLB::flushAll ( )

inlineoverridevirtual

Reset the entire TLB.

Used for CPU switching to prevent stale translations after multiple switches

Implements BaseTLB.

Definition at line 260 of file tlb.hh.

References ArmISA::domain, ArmISA::EL0, ArmISA::pa, and ArmISA::va.

flushAllNs()

void TLB::flushAllNs	(	ExceptionLevel	target_el,
		bool	ignore_el = false
	)

Remove all entries in the non secure world, depending on whether they were allocated in hyp mode or not.

Definition at line 276 of file tlb.cc.

References ArmISA::TlbEntry::checkELMatch(), DPRINTF, ArmISA::EL1, ArmISA::EL2, flushAllNs(), flushedEntries, flushTlb, ArmISA::TlbEntry::isHyp, isStage2, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), size, stage2Tlb, table, ArmISA::te, ArmISA::TlbEntry::valid, and RiscvISA::x.

Referenced by flushAllNs(), and ArmISA::TLBIALLN::operator()().

flushAllSecurity()

void TLB::flushAllSecurity	(	bool	secure_lookup,
		ExceptionLevel	target_el,
		bool	ignore_el = false
	)

Reset the entire TLB.

Parameters

secure_lookup

if the operation affects the secure world

Definition at line 244 of file tlb.cc.

References ArmISA::TlbEntry::checkELMatch(), DPRINTF, ArmISA::EL1, flushAllSecurity(), flushedEntries, flushTlb, isHyp, isStage2, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), size, stage2Tlb, table, ArmISA::te, ArmISA::TlbEntry::valid, ArmISA::TlbEntry::vmid, vmid, and RiscvISA::x.

Referenced by flushAllSecurity(), ArmISA::TLBIALL::operator()(), ArmISA::ITLBIALL::operator()(), and ArmISA::DTLBIALL::operator()().

flushAsid()

void TLB::flushAsid	(	uint64_t	asn,
		bool	secure_lookup,
		ExceptionLevel	target_el
	)

Remove any entries that match the asn.

Parameters

asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world

Definition at line 318 of file tlb.cc.

References ArmISA::TlbEntry::asid, ArmISA::TlbEntry::checkELMatch(), DPRINTF, flushedEntries, flushTlbAsid, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::print(), size, table, ArmISA::te, ArmISA::TlbEntry::valid, ArmISA::TlbEntry::vmid, vmid, and RiscvISA::x.

Referenced by ArmISA::TLBIASID::operator()(), ArmISA::ITLBIASID::operator()(), and ArmISA::DTLBIASID::operator()().

flushIpaVmid()

void TLB::flushIpaVmid	(	Addr	ipa,
		bool	secure_lookup,
		ExceptionLevel	target_el
	)

Invalidate all entries in the stage 2 TLB that match the given ipa and the current VMID.

Parameters

ipa	the address to invalidate
secure_lookup	if the operation affects the secure world

Definition at line 374 of file tlb.cc.

References _flushMva(), isStage2, and stage2Tlb.

Referenced by ArmISA::TLBIIPA::operator()().

flushMva()

void TLB::flushMva	(	Addr	mva,
		bool	secure_lookup,
		ExceptionLevel	target_el
	)

Remove all entries that match the va regardless of asn.

Parameters

mva	address to flush from cache
secure_lookup	if the operation affects the secure world

Definition at line 342 of file tlb.cc.

References _flushMva(), DPRINTF, and flushTlbMva.

Referenced by ArmISA::TLBIMVAA::operator()().

flushMvaAsid()

void TLB::flushMvaAsid	(	Addr	mva,
		uint64_t	asn,
		bool	secure_lookup,
		ExceptionLevel	target_el
	)

Remove any entries that match both a va and asn.

Parameters

mva	virtual address to flush
asn	contextid/asn to flush on match
secure_lookup	if the operation affects the secure world

Definition at line 307 of file tlb.cc.

References _flushMva(), DPRINTF, and flushTlbMvaAsid.

Referenced by ArmISA::TLBIMVA::operator()(), ArmISA::ITLBIMVA::operator()(), and ArmISA::DTLBIMVA::operator()().

getAttr()

uint64_t ArmISA::TLB::getAttr ( ) const

inline

Definition at line 343 of file tlb.hh.

Referenced by ArmISA::ISA::setMiscReg().

getResultTe()

Fault TLB::getResultTe	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		TlbEntry *	mergeTe
	)

Definition at line 1514 of file tlb.cc.

References aarch64, ArmISA::ArmFault::annotate(), checkPermissions(), checkPermissions64(), curTranType, DPRINTF, ArmISA::Stage2LookUp::getTe(), getTE(), ArmISA::Stage2LookUp::isComplete(), isSecure, isStage2, NoFault, ArmISA::ArmFault::OVA, ArmISA::ArmFault::S1PTW, ArmISA::Stage2LookUp::setSelfDelete(), stage2Req, and stage2Tlb.

Referenced by translateMmuOn().

getsize()

int ArmISA::TLB::getsize ( ) const

inline

Definition at line 224 of file tlb.hh.

References ArmISA::mode, ArmISA::te, and MipsISA::vaddr.

getTableWalker()

TableWalker* ArmISA::TLB::getTableWalker ( )

inline

Definition at line 220 of file tlb.hh.

References ArmISA::m.

getTableWalkerPort()

Port * TLB::getTableWalkerPort ( )

overridevirtual

Get the table walker port.

This is used for migrating port connections during a CPU takeOverFrom() call. For architectures that do not have a table walker, NULL is returned, hence the use of a pointer rather than a reference. For ARM this method will always return a valid port pointer.

Returns

A pointer to the walker master port

Reimplemented from BaseTLB.

Definition at line 1281 of file tlb.cc.

References ArmISA::Stage2MMU::getDMAPort(), and stage2Mmu.

getTE()

Fault TLB::getTE	(	TlbEntry **	te,
		const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool	timing,
		bool	functional,
		bool	is_secure,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1446 of file tlb.cc.

References aarch64, aarch64EL, asid, DPRINTF, ArmISA::EL1, BaseTLB::Execute, instHits, instMisses, isHyp, isStage2, lookup(), NoFault, prefetchFaults, ArmISA::ArmFault::PrefetchTLBMiss, printTlb(), ArmISA::purifyTaggedAddr(), readHits, readMisses, stage2DescReq, tableWalker, ttbcr, updateMiscReg(), MipsISA::vaddr, vmid, ArmISA::TableWalker::walk(), BaseTLB::Write, writeHits, and writeMisses.

Referenced by ArmISA::Stage2LookUp::finish(), getResultTe(), and ArmISA::Stage2LookUp::getTe().

init()

void TLB::init ( )

overridevirtual

setup all the back pointers

Reimplemented from SimObject.

Definition at line 101 of file tlb.cc.

References isStage2, stage2Mmu, ArmISA::Stage2MMU::stage2Tlb(), and stage2Tlb.

insert()

void TLB::insert	(	Addr	vaddr,
		TlbEntry &	pte
	)

Definition at line 200 of file tlb.cc.

References ArmISA::TlbEntry::ap, ArmISA::TlbEntry::asid, asid, ArmISA::TlbEntry::domain, DPRINTF, ArmISA::el, ArmISA::TlbEntry::global, ArmISA::i, inserts, ArmISA::TlbEntry::isHyp, isHyp, ArmISA::TlbEntry::N, ArmISA::TlbEntry::nonCacheable, ArmISA::TlbEntry::ns, ArmISA::ns, ArmISA::TlbEntry::nstid, MipsISA::pfn, ArmISA::TlbEntry::pfn, ppRefills, ArmISA::TlbEntry::size, size, table, ArmISA::TlbEntry::valid, ArmISA::TlbEntry::vmid, vmid, ArmISA::TlbEntry::vpn, and ArmISA::TlbEntry::xn.

Referenced by ArmISA::TableWalker::insertTableEntry().

invalidateMiscReg()

void ArmISA::TLB::invalidateMiscReg ( )

inline

Definition at line 442 of file tlb.hh.

Referenced by ArmISA::ISA::clear(), and ArmISA::ISA::setMiscReg().

lookup()

TlbEntry * TLB::lookup	(	Addr	vpn,
		uint16_t	asn,
		uint8_t	vmid,
		bool	hyp,
		bool	secure,
		bool	functional,
		bool	ignore_asn,
		ExceptionLevel	target_el
	)

Lookup an entry in the TLB.

Parameters

vpn	virtual address
asn	context id/address space id to use
vmid	The virtual machine ID used for stage 2 translation
secure	if the lookup is secure
hyp	if the lookup is done from hyp mode
functional	if the lookup should modify state
ignore_asn	if on lookup asn should be ignored

Returns

pointer to TLB entry if it exists

Definition at line 157 of file tlb.cc.

References ArmISA::TlbEntry::ap, ArmISA::TlbEntry::asid, DPRINTF, ArmISA::TlbEntry::el, ArmISA::TlbEntry::global, ArmISA::i, ArmISA::TlbEntry::ns, ArmISA::TlbEntry::nstid, ArmISA::TlbEntry::pAddr(), ArmISA::TlbEntry::pfn, rangeMRU, ArmISA::TlbEntry::size, size, table, and RiscvISA::x.

Referenced by _flushMva(), getTE(), ArmISA::TableWalker::processWalkWrapper(), and translateFunctional().

params()

const Params* ArmISA::TLB::params ( ) const

inline

Definition at line 438 of file tlb.hh.

printTlb()

void TLB::printTlb

(

)

const

Definition at line 230 of file tlb.cc.

References DPRINTF, ArmISA::TlbEntry::print(), size, table, ArmISA::te, ArmISA::TlbEntry::valid, and RiscvISA::x.

Referenced by getTE().

regProbePoints()

void TLB::regProbePoints ( )

overridevirtual

Register probe points for this object.

No probe points by default, so do nothing in base.

Reimplemented from SimObject.

Definition at line 530 of file tlb.cc.

References SimObject::getProbeManager(), and ppRefills.

regStats()

void TLB::regStats ( )

overridevirtual

Callback to set stat parameters.

This callback is typically used for complex stats (e.g., distributions) that need parameters in addition to a name and a description. Stat names and descriptions should typically be set from the constructor usingo from the constructor using the ADD_STAT macro.

Reimplemented from Stats::Group.

Definition at line 413 of file tlb.cc.

References accesses, alignFaults, Stats::DataWrap< Derived, InfoProxyType >::desc(), domainFaults, flushedEntries, flushTlb, flushTlbAsid, flushTlbMva, flushTlbMvaAsid, hits, instAccesses, instHits, instMisses, misses, SimObject::name(), Stats::DataWrap< Derived, InfoProxyType >::name(), permsFaults, prefetchFaults, readAccesses, readHits, readMisses, Stats::Group::regStats(), writeAccesses, writeHits, and writeMisses.

setAttr()

void ArmISA::TLB::setAttr ( uint64_t  attr )

inline

Accessor functions for memory attributes for last accessed TLB entry.

Definition at line 337 of file tlb.hh.

References ArmISA::attr.

Referenced by translateMmuOff(), and translateMmuOn().

setMMU()

void TLB::setMMU	(	Stage2MMU *	m,
		MasterID	master_id
	)

Definition at line 108 of file tlb.cc.

References ArmISA::m, ArmISA::TableWalker::setMMU(), stage2Mmu, and tableWalker.

Referenced by ArmISA::Stage2MMU::Stage2MMU().

setTestInterface()

void TLB::setTestInterface

(

SimObject *

ti

)

Definition at line 1586 of file tlb.cc.

References fatal_if, SimObject::name(), and MipsISA::ti.

takeOverFrom()

void TLB::takeOverFrom ( BaseTLB *  otlb )

overridevirtual

Take over from an old tlb context.

Implements BaseTLB.

Definition at line 389 of file tlb.cc.

References _attr, directToStage2, haveLPAE, isStage2, panic, stage2DescReq, stage2Req, stage2Tlb, and takeOverFrom().

Referenced by takeOverFrom().

testTranslation()

Fault TLB::testTranslation	(	const RequestPtr &	req,
		Mode	mode,
		TlbEntry::DomainType	domain
	)

Definition at line 1598 of file tlb.cc.

References isPriv, and NoFault.

Referenced by translateMmuOff(), and translateMmuOn().

testWalk()

Fault TLB::testWalk	(	Addr	pa,
		Addr	size,
		Addr	va,
		bool	is_secure,
		Mode	mode,
		TlbEntry::DomainType	domain,
		LookupLevel	lookup_level
	)

Definition at line 1610 of file tlb.cc.

References isPriv, and NoFault.

Referenced by ArmISA::TableWalker::testWalk().

translateAtomic() [1/2]

Fault TLB::translateAtomic	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1194 of file tlb.cc.

References directToStage2, FullSystem, stage2Tlb, translateAtomic(), translateFs(), translateSe(), and updateMiscReg().

Referenced by ArmISA::Stage2MMU::readDataUntimed(), Trace::TarmacParserRecord::readMemNoEffect(), and translateAtomic().

translateAtomic() [2/2]

Fault ArmISA::TLB::translateAtomic ( const RequestPtr &  req, ThreadContext *  tc, Mode  mode  )

inlineoverridevirtual

Implements BaseTLB.

Definition at line 362 of file tlb.hh.

translateComplete()

Fault TLB::translateComplete	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		TLB::ArmTranslationType	tranType,
		bool	callFromS2
	)

Definition at line 1253 of file tlb.cc.

References DPRINTF, BaseTLB::Translation::finish(), FullSystem, BaseTLB::Translation::markDelayed(), NoFault, stage2Req, translateFs(), and translateSe().

Referenced by ArmISA::Stage2LookUp::finish(), and translateTiming().

translateFs()

Fault TLB::translateFs	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing,
		TLB::ArmTranslationType	tranType,
		bool	functional = false
	)

Definition at line 1128 of file tlb.cc.

References aarch64, aarch64EL, alignFaults, ArmISA::ArmFault::AlignmentFault, AlignmentMask, AllowUnaligned, asid, DPRINTF, BaseTLB::Execute, hcr, isPriv, isSecure, isStage2, ArmISA::longDescFormatInUse(), ArmISA::ArmFault::LpaeTran, ArmISA::mask, ArmISA::TlbEntry::NoAccess, ArmISA::purifyTaggedAddr(), S1S2NsTran, scr, sctlr, Request::STRICT_ORDER, translateMmuOff(), translateMmuOn(), ttbcr, Request::UNCACHEABLE, updateMiscReg(), UserMode, MipsISA::vaddr, ArmISA::ArmFault::VmsaTran, and BaseTLB::Write.

Referenced by translateAtomic(), translateComplete(), and translateFunctional().

translateFunctional() [1/3]

bool TLB::translateFunctional	(	ThreadContext *	tc,
		Addr	vaddr,
		Addr &	paddr
	)

Do a functional lookup on the TLB (for debugging) and don't modify any internal state.

Parameters

tc	thread context to get the context id from
vaddr	virtual address to translate
pa	returned physical address

Returns

if the translation was successful

Definition at line 115 of file tlb.cc.

References aarch64, aarch64EL, asid, directToStage2, ArmISA::e, ArmISA::EL1, isHyp, isSecure, lookup(), ArmISA::TlbEntry::pAddr(), stage2Tlb, translateFunctional(), updateMiscReg(), and vmid.

Referenced by ArmISA::Stage2MMU::readDataUntimed(), ArmISA::ISA::setMiscReg(), Trace::TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(), Trace::TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(), and translateFunctional().

translateFunctional() [2/3]

Fault TLB::translateFunctional	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		TLB::ArmTranslationType	tranType
	)

Do a functional lookup on the TLB (for checker cpu) that behaves like a normal lookup without modifying any page table state.

Definition at line 1215 of file tlb.cc.

References directToStage2, FullSystem, stage2Tlb, translateFs(), translateFunctional(), translateSe(), and updateMiscReg().

translateFunctional() [3/3]

Fault ArmISA::TLB::translateFunctional ( const RequestPtr &  req, ThreadContext *  tc, Mode  mode  )

inlineoverridevirtual

Reimplemented from BaseTLB.

Definition at line 328 of file tlb.hh.

translateMmuOff()

Fault TLB::translateMmuOff	(	ThreadContext *	tc,
		const RequestPtr &	req,
		Mode	mode,
		TLB::ArmTranslationType	tranType,
		Addr	vaddr,
		bool	long_desc_format
	)

Definition at line 1008 of file tlb.cc.

References ArmISA::TlbEntry::attributes, DPRINTF, BaseTLB::Execute, hcr, ArmISA::TlbEntry::innerAttrs, isHyp, isSecure, isStage2, ArmISA::TlbEntry::mtype, nmrr, ArmISA::TlbEntry::NoAccess, ArmISA::TlbEntry::Normal, ArmISA::TlbEntry::ns, ArmISA::TlbEntry::outerAttrs, ArmISA::TlbEntry::outerShareable, prrr, S1CTran, sctlr, Request::SECURE, setAttr(), ArmISA::TlbEntry::setAttributes(), ArmISA::TlbEntry::shareable, Request::STRICT_ORDER, ArmISA::TlbEntry::StronglyOrdered, testTranslation(), and Request::UNCACHEABLE.

Referenced by translateFs().

translateMmuOn()

Fault TLB::translateMmuOn	(	ThreadContext *	tc,
		const RequestPtr &	req,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing,
		bool	functional,
		Addr	vaddr,
		ArmFault::TranMethod	tranMethod
	)

Definition at line 1057 of file tlb.cc.

References alignFaults, ArmISA::ArmFault::AlignmentFault, AlignmentMask, ArmISA::TlbEntry::attributes, ArmISA::TlbEntry::domain, DPRINTF, BaseTLB::Execute, finalizePhysical(), getResultTe(), ArmISA::TlbEntry::innerAttrs, isSecure, isStage2, ArmISA::mask, ArmISA::TlbEntry::mtype, ArmISA::TlbEntry::NoAccess, NoFault, ArmISA::TlbEntry::nonCacheable, ArmISA::TlbEntry::Normal, ArmISA::TlbEntry::ns, ArmISA::TlbEntry::outerAttrs, ArmISA::pa, ArmISA::TlbEntry::pAddr(), Request::SECURE, setAttr(), ArmISA::TlbEntry::shareable, Request::STRICT_ORDER, ArmISA::te, testTranslation(), Request::UNCACHEABLE, and BaseTLB::Write.

Referenced by translateFs().

translateSe()

Fault TLB::translateSe	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Mode	mode,
		Translation *	translation,
		bool &	delay,
		bool	timing
	)

Definition at line 536 of file tlb.cc.

References aarch64, aarch64EL, ArmISA::ArmFault::AlignmentFault, AlignmentMask, AllowUnaligned, BaseTLB::Execute, finalizePhysical(), ThreadContext::getProcessPtr(), isStage2, ArmISA::mask, ArmISA::TlbEntry::NoAccess, MipsISA::p, Process::pTable, ArmISA::purifyTaggedAddr(), sctlr, EmulationPageTable::translate(), ttbcr, updateMiscReg(), MipsISA::vaddr, ArmISA::ArmFault::VmsaTran, and BaseTLB::Write.

Referenced by translateAtomic(), translateComplete(), and translateFunctional().

translateTiming() [1/2]

void TLB::translateTiming	(	const RequestPtr &	req,
		ThreadContext *	tc,
		Translation *	translation,
		Mode	mode,
		TLB::ArmTranslationType	tranType
	)

Definition at line 1236 of file tlb.cc.

References directToStage2, isStage2, stage2Tlb, translateComplete(), translateTiming(), and updateMiscReg().

Referenced by ArmISA::TableWalker::doL1DescriptorWrapper(), ArmISA::TableWalker::doL2DescriptorWrapper(), ArmISA::TableWalker::doLongDescriptorWrapper(), ArmISA::TableWalker::processWalkWrapper(), ArmISA::Stage2MMU::Stage2Translation::translateTiming(), and translateTiming().

translateTiming() [2/2]

void ArmISA::TLB::translateTiming ( const RequestPtr &  req, ThreadContext *  tc, Translation *  translation, Mode  mode  )

inlineoverridevirtual

Implements BaseTLB.

Definition at line 372 of file tlb.hh.

tranTypeEL()

ExceptionLevel TLB::tranTypeEL ( CPSR  cpsr, ArmTranslationType  type  )

static

Determine the EL to use for the purpose of a translation given a specific translation type.

If the translation type doesn't specify an EL, we use the current EL.

Definition at line 1417 of file tlb.cc.

References ArmISA::currEL(), ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, HypMode, NormalTran, panic, S12E0Tran, S12E1Tran, S1CTran, S1E0Tran, S1E1Tran, S1E2Tran, S1E3Tran, and S1S2NsTran.

Referenced by updateMiscReg(), and ArmISA::TableWalker::walk().

trickBoxCheck()

Fault ArmISA::TLB::trickBoxCheck	(	const RequestPtr &	req,
		Mode	mode,
		TlbEntry::DomainType	domain
	)

updateMiscReg()

void TLB::updateMiscReg ( ThreadContext *  tc, ArmTranslationType  tranType = NormalTran  )

protected

Definition at line 1287 of file tlb.cc.

References aarch64, aarch64EL, asid, bits(), ThreadContext::contextId(), cpsr, curTranType, dacr, directToStage2, DPRINTF, ArmISA::EL0, ArmISA::EL1, ArmISA::EL2, ArmISA::EL3, ArmISA::ELIs64(), haveLargeAsid64, haveVirtualization, hcr, HypMode, ArmISA::inSecureState(), isHyp, isPriv, isSecure, isStage2, ArmISA::longDescFormatInUse(), ArmISA::MISCREG_CONTEXTIDR, ArmISA::MISCREG_CPSR, ArmISA::MISCREG_DACR, ArmISA::MISCREG_HCR, ArmISA::MISCREG_HCR_EL2, ArmISA::MISCREG_HSCTLR, ArmISA::MISCREG_NMRR, ArmISA::MISCREG_PRRR, ArmISA::MISCREG_SCR, ArmISA::MISCREG_SCR_EL3, ArmISA::MISCREG_SCTLR, ArmISA::MISCREG_SCTLR_EL1, ArmISA::MISCREG_SCTLR_EL2, ArmISA::MISCREG_SCTLR_EL3, ArmISA::MISCREG_TCR_EL1, ArmISA::MISCREG_TCR_EL2, ArmISA::MISCREG_TCR_EL3, ArmISA::MISCREG_TTBCR, ArmISA::MISCREG_TTBR0, ArmISA::MISCREG_TTBR0_EL1, ArmISA::MISCREG_TTBR1, ArmISA::MISCREG_TTBR1_EL1, ArmISA::MISCREG_VTTBR, ArmISA::MISCREG_VTTBR_EL2, miscRegContext, miscRegValid, ArmISA::MODE_HYP, ArmISA::MODE_USER, nmrr, prrr, ThreadContext::readMiscReg(), S1CTran, S1E1Tran, S1S2NsTran, scr, sctlr, ArmISA::snsBankedIndex(), stage2DescReq, stage2Req, tranTypeEL(), ttbcr, and vmid.

Referenced by checkPermissions64(), getTE(), translateAtomic(), translateFs(), translateFunctional(), translateSe(), and translateTiming().

walkTrickBoxCheck()

Fault ArmISA::TLB::walkTrickBoxCheck	(	Addr	pa,
		bool	is_secure,
		Addr	va,
		Addr	sz,
		bool	is_exec,
		bool	is_write,
		TlbEntry::DomainType	domain,
		LookupLevel	lookup_level
	)

Member Data Documentation

_attr

uint64_t ArmISA::TLB::_attr

protected

Definition at line 153 of file tlb.hh.

Referenced by takeOverFrom().

aarch64

bool ArmISA::TLB::aarch64

protected

Definition at line 408 of file tlb.hh.

Referenced by checkPermissions64(), getResultTe(), getTE(), translateFs(), translateFunctional(), translateSe(), and updateMiscReg().

aarch64EL

ExceptionLevel ArmISA::TLB::aarch64EL

protected

Definition at line 409 of file tlb.hh.

Referenced by checkPermissions64(), getTE(), translateFs(), translateFunctional(), translateSe(), and updateMiscReg().

accesses

Stats::Formula ArmISA::TLB::accesses

protected

Definition at line 186 of file tlb.hh.

Referenced by regStats().

alignFaults

Stats::Scalar ArmISA::TLB::alignFaults

mutableprotected

Definition at line 176 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), regStats(), translateFs(), and translateMmuOn().

asid

uint16_t ArmISA::TLB::asid

protected

Definition at line 416 of file tlb.hh.

Referenced by getTE(), insert(), translateFs(), translateFunctional(), and updateMiscReg().

cpsr

CPSR ArmISA::TLB::cpsr

protected

Definition at line 407 of file tlb.hh.

Referenced by checkPAN(), and updateMiscReg().

curTranType

ArmTranslationType ArmISA::TLB::curTranType

protected

Definition at line 424 of file tlb.hh.

Referenced by checkPermissions64(), getResultTe(), and updateMiscReg().

dacr

uint32_t ArmISA::TLB::dacr

protected

Definition at line 421 of file tlb.hh.

Referenced by checkPermissions(), and updateMiscReg().

directToStage2

bool ArmISA::TLB::directToStage2

protected

Definition at line 154 of file tlb.hh.

Referenced by takeOverFrom(), translateAtomic(), translateFunctional(), translateTiming(), and updateMiscReg().

domainFaults

Stats::Scalar ArmISA::TLB::domainFaults

mutableprotected

Definition at line 178 of file tlb.hh.

Referenced by checkPermissions(), and regStats().

flushedEntries

Stats::Scalar ArmISA::TLB::flushedEntries

mutableprotected

Definition at line 175 of file tlb.hh.

Referenced by _flushMva(), flushAllNs(), flushAllSecurity(), flushAsid(), and regStats().

flushTlb

Stats::Scalar ArmISA::TLB::flushTlb

mutableprotected

Definition at line 171 of file tlb.hh.

Referenced by flushAllNs(), flushAllSecurity(), and regStats().

flushTlbAsid

Stats::Scalar ArmISA::TLB::flushTlbAsid

mutableprotected

Definition at line 174 of file tlb.hh.

Referenced by flushAsid(), and regStats().

flushTlbMva

Stats::Scalar ArmISA::TLB::flushTlbMva

mutableprotected

Definition at line 172 of file tlb.hh.

Referenced by flushMva(), and regStats().

flushTlbMvaAsid

Stats::Scalar ArmISA::TLB::flushTlbMvaAsid

mutableprotected

Definition at line 173 of file tlb.hh.

Referenced by flushMvaAsid(), and regStats().

haveLargeAsid64

bool ArmISA::TLB::haveLargeAsid64

protected

Definition at line 429 of file tlb.hh.

Referenced by TLB(), and updateMiscReg().

haveLPAE

bool ArmISA::TLB::haveLPAE

protected

Definition at line 427 of file tlb.hh.

Referenced by takeOverFrom(), and TLB().

haveVirtualization

bool ArmISA::TLB::haveVirtualization

protected

Definition at line 428 of file tlb.hh.

Referenced by TLB(), and updateMiscReg().

hcr

HCR ArmISA::TLB::hcr

protected

Definition at line 420 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), translateFs(), translateMmuOff(), and updateMiscReg().

hits

Stats::Formula ArmISA::TLB::hits

protected

Definition at line 184 of file tlb.hh.

Referenced by regStats().

inserts

Stats::Scalar ArmISA::TLB::inserts

mutableprotected

Definition at line 170 of file tlb.hh.

Referenced by insert().

instAccesses

Stats::Formula ArmISA::TLB::instAccesses

protected

Definition at line 183 of file tlb.hh.

Referenced by regStats().

instHits

Stats::Scalar ArmISA::TLB::instHits

mutableprotected

Definition at line 164 of file tlb.hh.

Referenced by getTE(), and regStats().

instMisses

Stats::Scalar ArmISA::TLB::instMisses

mutableprotected

Definition at line 165 of file tlb.hh.

Referenced by getTE(), and regStats().

isHyp

bool ArmISA::TLB::isHyp

protected

Definition at line 414 of file tlb.hh.

Referenced by flushAllSecurity(), getTE(), insert(), translateFunctional(), translateMmuOff(), and updateMiscReg().

isPriv

bool ArmISA::TLB::isPriv

protected

Definition at line 412 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), testTranslation(), testWalk(), translateFs(), and updateMiscReg().

isSecure

bool ArmISA::TLB::isSecure

protected

Definition at line 413 of file tlb.hh.

Referenced by checkPermissions(), getResultTe(), translateFs(), translateFunctional(), translateMmuOff(), translateMmuOn(), and updateMiscReg().

isStage2

bool ArmISA::TLB::isStage2

protected

Definition at line 147 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), flushAllNs(), flushAllSecurity(), flushIpaVmid(), getResultTe(), getTE(), init(), takeOverFrom(), translateFs(), translateMmuOff(), translateMmuOn(), translateSe(), translateTiming(), and updateMiscReg().

m5opRange

AddrRange ArmISA::TLB::m5opRange

protected

Definition at line 431 of file tlb.hh.

Referenced by finalizePhysical(), and TLB().

miscRegContext

ContextID ArmISA::TLB::miscRegContext

protected

Definition at line 423 of file tlb.hh.

Referenced by updateMiscReg().

miscRegValid

bool ArmISA::TLB::miscRegValid

protected

Definition at line 422 of file tlb.hh.

Referenced by drainResume(), and updateMiscReg().

misses

Stats::Formula ArmISA::TLB::misses

protected

Definition at line 185 of file tlb.hh.

Referenced by regStats().

nmrr

NMRR ArmISA::TLB::nmrr

protected

Definition at line 419 of file tlb.hh.

Referenced by translateMmuOff(), and updateMiscReg().

permsFaults

Stats::Scalar ArmISA::TLB::permsFaults

mutableprotected

Definition at line 179 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), and regStats().

ppRefills

ProbePoints::PMUUPtr ArmISA::TLB::ppRefills

protected

PMU probe for TLB refills.

Definition at line 189 of file tlb.hh.

Referenced by insert(), and regProbePoints().

prefetchFaults

Stats::Scalar ArmISA::TLB::prefetchFaults

mutableprotected

Definition at line 177 of file tlb.hh.

Referenced by getTE(), and regStats().

prrr

PRRR ArmISA::TLB::prrr

protected

Definition at line 418 of file tlb.hh.

Referenced by translateMmuOff(), and updateMiscReg().

rangeMRU

int ArmISA::TLB::rangeMRU

protected

Definition at line 191 of file tlb.hh.

Referenced by lookup().

readAccesses

Stats::Formula ArmISA::TLB::readAccesses

protected

Definition at line 181 of file tlb.hh.

Referenced by regStats().

readHits

Stats::Scalar ArmISA::TLB::readHits

mutableprotected

Definition at line 166 of file tlb.hh.

Referenced by getTE(), and regStats().

readMisses

Stats::Scalar ArmISA::TLB::readMisses

mutableprotected

Definition at line 167 of file tlb.hh.

Referenced by getTE(), and regStats().

scr

SCR ArmISA::TLB::scr

protected

Definition at line 411 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), translateFs(), and updateMiscReg().

sctlr

SCTLR ArmISA::TLB::sctlr

protected

Definition at line 410 of file tlb.hh.

Referenced by checkPermissions(), checkPermissions64(), translateFs(), translateMmuOff(), translateSe(), and updateMiscReg().

size

int ArmISA::TLB::size

protected

Definition at line 146 of file tlb.hh.

Referenced by flushAllNs(), flushAllSecurity(), flushAsid(), insert(), lookup(), and printTlb().

stage2DescReq

bool ArmISA::TLB::stage2DescReq

protected

Definition at line 152 of file tlb.hh.

Referenced by getTE(), takeOverFrom(), and updateMiscReg().

stage2Mmu

Stage2MMU* ArmISA::TLB::stage2Mmu

protected

Definition at line 159 of file tlb.hh.

Referenced by getTableWalkerPort(), init(), and setMMU().

stage2Req

bool ArmISA::TLB::stage2Req

protected

Definition at line 148 of file tlb.hh.

Referenced by getResultTe(), takeOverFrom(), translateComplete(), and updateMiscReg().

stage2Tlb

TLB* ArmISA::TLB::stage2Tlb

protected

Definition at line 158 of file tlb.hh.

Referenced by flushAllNs(), flushAllSecurity(), flushIpaVmid(), getResultTe(), init(), takeOverFrom(), translateAtomic(), translateFunctional(), and translateTiming().

table

TlbEntry* ArmISA::TLB::table

protected

Definition at line 145 of file tlb.hh.

Referenced by flushAllNs(), flushAllSecurity(), flushAsid(), insert(), lookup(), printTlb(), and ~TLB().

tableWalker

TableWalker* ArmISA::TLB::tableWalker

protected

Definition at line 157 of file tlb.hh.

Referenced by getTE(), setMMU(), and TLB().

test

TlbTestInterface* ArmISA::TLB::test

protected

Definition at line 161 of file tlb.hh.

ttbcr

TTBCR ArmISA::TLB::ttbcr

protected

Definition at line 415 of file tlb.hh.

Referenced by checkPermissions64(), getTE(), translateFs(), translateSe(), and updateMiscReg().

vmid

uint8_t ArmISA::TLB::vmid

protected

Definition at line 417 of file tlb.hh.

Referenced by _flushMva(), flushAllSecurity(), flushAsid(), getTE(), insert(), translateFunctional(), and updateMiscReg().

writeAccesses

Stats::Formula ArmISA::TLB::writeAccesses

protected

Definition at line 182 of file tlb.hh.

Referenced by regStats().

writeHits

Stats::Scalar ArmISA::TLB::writeHits

mutableprotected

Definition at line 168 of file tlb.hh.

Referenced by getTE(), and regStats().

writeMisses

Stats::Scalar ArmISA::TLB::writeMisses

mutableprotected

Definition at line 169 of file tlb.hh.

Referenced by getTE(), and regStats().

---

The documentation for this class was generated from the following files:

• arch/arm/tlb.hh
• arch/arm/tlb.cc