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stage2_lookup.hh
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37 
38 #ifndef __ARCH_ARM_STAGE2_LOOKUP_HH__
39 #define __ARCH_ARM_STAGE2_LOOKUP_HH__
40 
41 #include <list>
42 
43 #include "arch/arm/system.hh"
44 #include "arch/arm/table_walker.hh"
45 #include "arch/arm/tlb.hh"
46 #include "mem/request.hh"
47 
48 class ThreadContext;
49 
50 namespace ArmISA {
51 class Translation;
52 class TLB;
53 
54 
56 {
57  private:
62  TLB::Translation *transState;
64  bool timing;
65  bool functional;
70  bool complete;
71  bool selfDelete;
72 
73  public:
74  Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req,
75  TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
76  bool _functional, TLB::ArmTranslationType _tranType) :
77  stage1Tlb(s1Tlb), stage2Tlb(s2Tlb), stage1Te(s1Te), s1Req(_req),
78  transState(_transState), mode(_mode), timing(_timing),
79  functional(_functional), tranType(_tranType), stage2Te(nullptr),
80  fault(NoFault), complete(false), selfDelete(false)
81  {
82  req = std::make_shared<Request>();
83  req->setVirt(s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
84  s1Req->getFlags(), s1Req->masterId(), 0);
85  }
86 
87  Fault getTe(ThreadContext *tc, TlbEntry *destTe);
88 
89  void mergeTe(const RequestPtr &req, BaseTLB::Mode mode);
90 
91  void setSelfDelete() { selfDelete = true; }
92 
93  bool isComplete() const { return complete; }
94 
95  void markDelayed() {}
96 
97  void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
98  BaseTLB::Mode mode);
99 };
100 
101 
102 } // namespace ArmISA
103 
104 #endif //__ARCH_ARM_STAGE2_LOOKUP_HH__
105 
decltype(nullptr) constexpr NoFault
Definition: types.hh:243
Declaration of a request, the overall memory request consisting of the parts of the request that are ...
std::shared_ptr< Request > RequestPtr
Definition: request.hh:81
BaseTLB::Mode mode
Definition: ccregs.hh:41
ThreadContext is the external interface to all thread state for anything outside of the CPU...
Fault getTe(ThreadContext *tc, TlbEntry *destTe)
void markDelayed()
Signal that the translation has been delayed due to a hw page table walk.
Addr pAddr(Addr va) const
Definition: pagetable.hh:229
ArmTranslationType
Definition: tlb.hh:118
TLB::ArmTranslationType tranType
bool isComplete() const
Mode
Definition: tlb.hh:57
Stage2LookUp(TLB *s1Tlb, TLB *s2Tlb, TlbEntry s1Te, const RequestPtr &_req, TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing, bool _functional, TLB::ArmTranslationType _tranType)
void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
void mergeTe(const RequestPtr &req, BaseTLB::Mode mode)
TLB::Translation * transState
std::shared_ptr< FaultBase > Fault
Definition: types.hh:238

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