a9scu.cc

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#include "dev/arm/a9scu.hh"

#include "base/intmath.hh"
#include "base/trace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"

A9SCU::A9SCU(Params *p)
    : BasicPioDevice(p, 0x60)
{
}

Tick
A9SCU::read(PacketPtr pkt)
{
    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
    assert(pkt->getSize() == 4);
    Addr daddr = pkt->getAddr() - pioAddr;

    switch(daddr) {
      case Control:
        pkt->setLE(1); // SCU already enabled
        break;
      case Config:
        /* Without making a completely new SCU, we can use the core count field
         * as 4 bits and inform the OS of up to 16 CPUs.  Although the core
         * count is technically bits [1:0] only, bits [3:2] are SBZ for future
         * expansion like this.
         */
        if (sys->numContexts() > 4) {
            warn_once("A9SCU with >4 CPUs is unsupported\n");
            if (sys->numContexts() > 15)
                fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts());
        }
        int smp_bits, core_cnt;
        smp_bits = (1 << sys->numContexts()) - 1;
        core_cnt = sys->numContexts() - 1;
        pkt->setLE(smp_bits << 4 | core_cnt);
        break;
      default:
        // Only configuration register is implemented
        panic("Tried to read SCU at offset %#x\n", daddr);
        break;
    }
    pkt->makeAtomicResponse();
    return pioDelay;

}

Tick
A9SCU::write(PacketPtr pkt)
{
    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);

    Addr daddr = pkt->getAddr() - pioAddr;
    switch (daddr) {
      default:
        // Nothing implemented at this point
        warn("Tried to write SCU at offset %#x\n", daddr);
        break;
    }
    pkt->makeAtomicResponse();
    return pioDelay;
}

A9SCU *
A9SCUParams::create()
{
    return new A9SCU(this);
}