gem5  v20.0.0.3
system.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2002-2006 The Regents of The University of Michigan
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include "arch/arm/system.hh"
42 
43 #include <iostream>
44 
45 #include "arch/arm/fs_workload.hh"
46 #include "arch/arm/semihosting.hh"
48 #include "base/loader/symtab.hh"
49 #include "cpu/thread_context.hh"
51 #include "dev/arm/gic_v2.hh"
52 #include "mem/physical.hh"
53 
54 using namespace std;
55 using namespace Linux;
56 
58  : System(p),
59  _haveSecurity(p->have_security),
60  _haveLPAE(p->have_lpae),
61  _haveVirtualization(p->have_virtualization),
62  _haveCrypto(p->have_crypto),
63  _genericTimer(nullptr),
64  _gic(nullptr),
65  _pwrCtrl(nullptr),
66  _highestELIs64(p->highest_el_is_64),
67  _physAddrRange64(p->phys_addr_range_64),
68  _haveLargeAsid64(p->have_large_asid_64),
69  _haveSVE(p->have_sve),
70  _sveVL(p->sve_vl),
71  _haveLSE(p->have_lse),
72  _havePAN(p->have_pan),
73  semihosting(p->semihosting),
74  multiProc(p->multi_proc)
75 {
76  if (p->auto_reset_addr) {
78  } else {
79  _resetAddr = p->reset_addr;
81  "Workload entry point %#x and reset address %#x are different",
83  }
84 
85  bool wl_is_64 = (workload->getArch() == Loader::Arm64);
86  if (wl_is_64 != _highestELIs64) {
87  warn("Highest ARM exception-level set to AArch%d but the workload "
88  "is for AArch%d. Assuming you wanted these to match.",
89  _highestELIs64 ? 64 : 32, wl_is_64 ? 64 : 32);
90  _highestELIs64 = wl_is_64;
91  }
92 
93  if (_highestELIs64 && (
94  _physAddrRange64 < 32 ||
95  _physAddrRange64 > 48 ||
96  (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
97  fatal("Invalid physical address range (%d)\n", _physAddrRange64);
98  }
99 }
100 
101 bool
103 {
104  return FullSystem? getArmSystem(tc)->haveSecurity() : false;
105 }
106 
107 bool
109 {
110  return FullSystem? getArmSystem(tc)->haveLPAE() : false;
111 }
112 
113 bool
115 {
116  return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
117 }
118 
119 bool
121 {
122  return FullSystem? getArmSystem(tc)->highestELIs64() : true;
123 }
124 
127 {
128  return FullSystem? getArmSystem(tc)->highestEL() : EL1;
129 }
130 
131 bool
133 {
134  switch (el) {
135  case EL0:
136  case EL1:
137  return true;
138  case EL2:
139  return haveVirtualization(tc);
140  case EL3:
141  return haveSecurity(tc);
142  default:
143  warn("Unimplemented Exception Level\n");
144  return false;
145  }
146 }
147 
148 Addr
150 {
151  return getArmSystem(tc)->resetAddr();
152 }
153 
154 uint8_t
156 {
157  return getArmSystem(tc)->physAddrRange();
158 }
159 
160 Addr
162 {
163  return getArmSystem(tc)->physAddrMask();
164 }
165 
166 bool
168 {
169  return getArmSystem(tc)->haveLargeAsid64();
170 }
171 
172 bool
174 {
175  return FullSystem && getArmSystem(tc)->haveSemihosting();
176 }
177 
178 bool
180 {
181  return getArmSystem(tc)->semihosting->call64(tc, gem5_ops);
182 }
183 
184 bool
186 {
187  return getArmSystem(tc)->semihosting->call32(tc, gem5_ops);
188 }
189 
190 bool
192 {
193  if (ArmISA::inAArch64(tc))
194  return callSemihosting64(tc, gem5_ops);
195  else
196  return callSemihosting32(tc, gem5_ops);
197 }
198 
199 void
201 {
202  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
203  pwr_ctrl->setStandByWfi(tc);
204 }
205 
206 void
208 {
209  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
210  pwr_ctrl->clearStandByWfi(tc);
211 }
212 
213 bool
215 {
216  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
217  return pwr_ctrl->setWakeRequest(tc);
218  else
219  return true;
220 }
221 
222 void
224 {
225  if (FVPBasePwrCtrl *pwr_ctrl = getArmSystem(tc)->getPowerController())
226  pwr_ctrl->clearWakeRequest(tc);
227 }
228 
229 ArmSystem *
230 ArmSystemParams::create()
231 {
232  return new ArmSystem(this);
233 }
const uint8_t _physAddrRange64
Supported physical address range in bits if the highest implemented exception level is 64 bits (ARMv8...
Definition: system.hh:108
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:171
Addr physAddrMask() const
Returns the physical address mask.
Definition: system.hh:242
bool haveSecurity() const
Returns true if this system implements the Security Extensions.
Definition: system.hh:150
bool call64(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch64 code.
Definition: semihosting.cc:163
static void callClearWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST deassertion.
Definition: system.cc:223
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8) ...
Definition: system.hh:193
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
Definition: system.hh:72
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
static bool callSetWakeRequest(ThreadContext *tc)
Notify the power controller of WAKEREQUEST assertion.
Definition: system.cc:214
ThreadContext is the external interface to all thread state for anything outside of the CPU...
ExceptionLevel
Definition: types.hh:583
static bool haveEL(ThreadContext *tc, ExceptionLevel el)
Return true if the system implements a specific exception level.
Definition: system.cc:132
ArmSystem(Params *p)
Definition: system.cc:57
bool call32(ThreadContext *tc, bool gem5_ops)
Perform an Arm Semihosting call from aarch32 code.
Definition: semihosting.cc:189
Bitfield< 3, 2 > el
bool _highestELIs64
True if the register width of the highest implemented exception level is 64 bits (ARMv8) ...
Definition: system.hh:102
virtual Loader::Arch getArch() const =0
#define warn_if(cond,...)
Conditional warning macro that checks the supplied condition and only prints a warning if the conditi...
Definition: logging.hh:224
static ArmSystem * getArmSystem(ThreadContext *tc)
Returns a valid ArmSystem pointer if using ARM ISA, it fails otherwise.
Definition: system.hh:252
Workload * workload
OS kernel.
Definition: system.hh:213
FVPBasePwrCtrl * getPowerController() const
Get a pointer to the system&#39;s power controller.
Definition: system.hh:189
bool haveVirtualization() const
Returns true if this system implements the virtualization Extensions.
Definition: system.hh:159
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:140
static void callSetStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI assertion.
Definition: system.cc:200
static void callClearStandByWfi(ThreadContext *tc)
Make a call to notify the power controller of STANDBYWFI deassertion.
Definition: system.cc:207
virtual Addr getEntry() const =0
This class implements the base power controller for FVP-based platforms.
uint8_t physAddrRange() const
Returns the supported physical address range in bits.
Definition: system.hh:232
ExceptionLevel highestEL() const
Returns the highest implemented exception level.
Definition: system.hh:197
ArmSemihosting *const semihosting
True if the Semihosting interface is enabled.
Definition: system.hh:134
ArmSystemParams Params
Definition: system.hh:137
Implementation of a GICv2.
static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from either aarch64 or aarch32.
Definition: system.cc:191
bool inAArch64(ThreadContext *tc)
Definition: utility.cc:190
#define warn(...)
Definition: logging.hh:208
bool haveLargeAsid64() const
Returns true if ASID is 16 bits in AArch64 (ARMv8)
Definition: system.hh:212
Addr _resetAddr
Reset address (ARMv8)
Definition: system.hh:96
bool haveSemihosting() const
Is Arm Semihosting support enabled?
Definition: system.hh:245
Bitfield< 0 > p
Addr resetAddr() const
Returns the reset address if the highest implemented exception level is 64 bits (ARMv8) ...
Definition: system.hh:208
static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch32.
Definition: system.cc:185
static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false)
Make a Semihosting call from aarch64.
Definition: system.cc:179
bool haveLPAE() const
Returns true if this system implements the Large Physical Address Extension.
Definition: system.hh:154

Generated on Fri Jul 3 2020 15:42:40 for gem5 by doxygen 1.8.13