dramsim2.hh

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/*
 * Copyright (c) 2013 ARM Limited
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 *
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 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
 *
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 * met: redistributions of source code must retain the above copyright
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 * redistributions in binary form must reproduce the above copyright
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#ifndef __MEM_DRAMSIM2_HH__
#define __MEM_DRAMSIM2_HH__

#include <queue>
#include <unordered_map>

#include "mem/abstract_mem.hh"
#include "mem/dramsim2_wrapper.hh"
#include "mem/qport.hh"
#include "params/DRAMSim2.hh"

class DRAMSim2 : public AbstractMemory
{
  private:

    class MemoryPort : public SlavePort
    {

      private:

        DRAMSim2& memory;

      public:

        MemoryPort(const std::string& _name, DRAMSim2& _memory);

      protected:

        Tick recvAtomic(PacketPtr pkt);

        void recvFunctional(PacketPtr pkt);

        bool recvTimingReq(PacketPtr pkt);

        void recvRespRetry();

        AddrRangeList getAddrRanges() const;

    };

    MemoryPort port;

    DRAMSim2Wrapper wrapper;

    bool retryReq;

    bool retryResp;

    Tick startTick;

    std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads;
    std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites;

    unsigned int nbrOutstandingReads;
    unsigned int nbrOutstandingWrites;

    std::deque<PacketPtr> responseQueue;

    unsigned int nbrOutstanding() const;

    void accessAndRespond(PacketPtr pkt);

    void sendResponse();

    EventFunctionWrapper sendResponseEvent;

    void tick();

    EventFunctionWrapper tickEvent;

    std::unique_ptr<Packet> pendingDelete;

  public:

    typedef DRAMSim2Params Params;
    DRAMSim2(const Params *p);

    void readComplete(unsigned id, uint64_t addr, uint64_t cycle);

    void writeComplete(unsigned id, uint64_t addr, uint64_t cycle);

    DrainState drain() override;

    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID) override;

    void init() override;
    void startup() override;

  protected:

    Tick recvAtomic(PacketPtr pkt);
    void recvFunctional(PacketPtr pkt);
    bool recvTimingReq(PacketPtr pkt);
    void recvRespRetry();

};

#endif // __MEM_DRAMSIM2_HH__