gem5  v20.1.0.0
abstract_mem.cc
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40 
41 #include "mem/abstract_mem.hh"
42 
43 #include <vector>
44 
45 #include "arch/locked_mem.hh"
48 #include "cpu/base.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/LLSC.hh"
51 #include "debug/MemoryAccess.hh"
52 #include "mem/packet_access.hh"
53 #include "sim/system.hh"
54 
55 using namespace std;
56 
58  ClockedObject(p), range(params()->range), pmemAddr(NULL),
59  backdoor(params()->range, nullptr,
60  (MemBackdoor::Flags)(MemBackdoor::Readable |
61  MemBackdoor::Writeable)),
62  confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
63  kvmMap(p->kvm_map), _system(NULL),
64  stats(*this)
65 {
66  panic_if(!range.valid() || !range.size(),
67  "Memory range %s must be valid with non-zero size.",
68  range.to_string());
69 }
70 
71 void
73 {
75 
76  const auto &file = params()->image_file;
77  if (file == "")
78  return;
79 
80  auto *object = Loader::createObjectFile(file, true);
81  fatal_if(!object, "%s: Could not load %s.", name(), file);
82 
83  Loader::debugSymbolTable.insert(*object->symtab().globals());
84  Loader::MemoryImage image = object->buildImage();
85 
86  AddrRange image_range(image.minAddr(), image.maxAddr());
87  if (!range.contains(image_range.start())) {
88  warn("%s: Moving image from %s to memory address range %s.",
89  name(), image_range.to_string(), range.to_string());
90  image = image.offset(range.start());
91  image_range = AddrRange(image.minAddr(), image.maxAddr());
92  }
93  panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't fit.",
94  name(), file);
95 
96  PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); },
97  system()->cacheLineSize());
98 
99  panic_if(!image.write(proxy), "%s: Unable to write image.");
100 }
101 
102 void
104 {
105  // If there was an existing backdoor, let everybody know it's going away.
106  if (backdoor.ptr())
108 
109  // The back door can't handle interleaved memory.
110  backdoor.ptr(range.interleaved() ? nullptr : pmem_addr);
111 
112  pmemAddr = pmem_addr;
113 }
114 
116  : Stats::Group(&_mem), mem(_mem),
117  bytesRead(this, "bytes_read",
118  "Number of bytes read from this memory"),
119  bytesInstRead(this, "bytes_inst_read",
120  "Number of instructions bytes read from this memory"),
121  bytesWritten(this, "bytes_written",
122  "Number of bytes written to this memory"),
123  numReads(this, "num_reads",
124  "Number of read requests responded to by this memory"),
125  numWrites(this, "num_writes",
126  "Number of write requests responded to by this memory"),
127  numOther(this, "num_other",
128  "Number of other requests responded to by this memory"),
129  bwRead(this, "bw_read",
130  "Total read bandwidth from this memory (bytes/s)"),
131  bwInstRead(this, "bw_inst_read",
132  "Instruction read bandwidth from this memory (bytes/s)"),
133  bwWrite(this, "bw_write",
134  "Write bandwidth from this memory (bytes/s)"),
135  bwTotal(this, "bw_total",
136  "Total bandwidth to/from this memory (bytes/s)")
137 {
138 }
139 
140 void
142 {
143  using namespace Stats;
144 
146 
147  System *sys = mem.system();
148  assert(sys);
149  const auto max_requestors = sys->maxRequestors();
150 
151  bytesRead
152  .init(max_requestors)
153  .flags(total | nozero | nonan)
154  ;
155  for (int i = 0; i < max_requestors; i++) {
156  bytesRead.subname(i, sys->getRequestorName(i));
157  }
158 
159  bytesInstRead
160  .init(max_requestors)
161  .flags(total | nozero | nonan)
162  ;
163  for (int i = 0; i < max_requestors; i++) {
164  bytesInstRead.subname(i, sys->getRequestorName(i));
165  }
166 
167  bytesWritten
168  .init(max_requestors)
169  .flags(total | nozero | nonan)
170  ;
171  for (int i = 0; i < max_requestors; i++) {
172  bytesWritten.subname(i, sys->getRequestorName(i));
173  }
174 
175  numReads
176  .init(max_requestors)
177  .flags(total | nozero | nonan)
178  ;
179  for (int i = 0; i < max_requestors; i++) {
180  numReads.subname(i, sys->getRequestorName(i));
181  }
182 
183  numWrites
184  .init(max_requestors)
185  .flags(total | nozero | nonan)
186  ;
187  for (int i = 0; i < max_requestors; i++) {
188  numWrites.subname(i, sys->getRequestorName(i));
189  }
190 
191  numOther
192  .init(max_requestors)
193  .flags(total | nozero | nonan)
194  ;
195  for (int i = 0; i < max_requestors; i++) {
196  numOther.subname(i, sys->getRequestorName(i));
197  }
198 
199  bwRead
200  .precision(0)
201  .prereq(bytesRead)
202  .flags(total | nozero | nonan)
203  ;
204  for (int i = 0; i < max_requestors; i++) {
205  bwRead.subname(i, sys->getRequestorName(i));
206  }
207 
208  bwInstRead
209  .precision(0)
210  .prereq(bytesInstRead)
211  .flags(total | nozero | nonan)
212  ;
213  for (int i = 0; i < max_requestors; i++) {
214  bwInstRead.subname(i, sys->getRequestorName(i));
215  }
216 
217  bwWrite
218  .precision(0)
219  .prereq(bytesWritten)
220  .flags(total | nozero | nonan)
221  ;
222  for (int i = 0; i < max_requestors; i++) {
223  bwWrite.subname(i, sys->getRequestorName(i));
224  }
225 
226  bwTotal
227  .precision(0)
228  .prereq(bwTotal)
229  .flags(total | nozero | nonan)
230  ;
231  for (int i = 0; i < max_requestors; i++) {
232  bwTotal.subname(i, sys->getRequestorName(i));
233  }
234 
235  bwRead = bytesRead / simSeconds;
236  bwInstRead = bytesInstRead / simSeconds;
237  bwWrite = bytesWritten / simSeconds;
238  bwTotal = (bytesRead + bytesWritten) / simSeconds;
239 }
240 
241 AddrRange
243 {
244  return range;
245 }
246 
247 // Add load-locked to tracking list. Should only be called if the
248 // operation is a load and the LLSC flag is set.
249 void
251 {
252  const RequestPtr &req = pkt->req;
253  Addr paddr = LockedAddr::mask(req->getPaddr());
254 
255  // first we check if we already have a locked addr for this
256  // xc. Since each xc only gets one, we just update the
257  // existing record with the new address.
259 
260  for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
261  if (i->matchesContext(req)) {
262  DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
263  req->contextId(), paddr);
264  i->addr = paddr;
265  return;
266  }
267  }
268 
269  // no record for this xc: need to allocate a new one
270  DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
271  req->contextId(), paddr);
272  lockedAddrList.push_front(LockedAddr(req));
273 }
274 
275 
276 // Called on *writes* only... both regular stores and
277 // store-conditional operations. Check for conventional stores which
278 // conflict with locked addresses, and for success/failure of store
279 // conditionals.
280 bool
282 {
283  const RequestPtr &req = pkt->req;
284  Addr paddr = LockedAddr::mask(req->getPaddr());
285  bool isLLSC = pkt->isLLSC();
286 
287  // Initialize return value. Non-conditional stores always
288  // succeed. Assume conditional stores will fail until proven
289  // otherwise.
290  bool allowStore = !isLLSC;
291 
292  // Iterate over list. Note that there could be multiple matching records,
293  // as more than one context could have done a load locked to this location.
294  // Only remove records when we succeed in finding a record for (xc, addr);
295  // then, remove all records with this address. Failed store-conditionals do
296  // not blow unrelated reservations.
298 
299  if (isLLSC) {
300  while (i != lockedAddrList.end()) {
301  if (i->addr == paddr && i->matchesContext(req)) {
302  // it's a store conditional, and as far as the memory system can
303  // tell, the requesting context's lock is still valid.
304  DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
305  req->contextId(), paddr);
306  allowStore = true;
307  break;
308  }
309  // If we didn't find a match, keep searching! Someone else may well
310  // have a reservation on this line here but we may find ours in just
311  // a little while.
312  i++;
313  }
314  req->setExtraData(allowStore ? 1 : 0);
315  }
316  // LLSCs that succeeded AND non-LLSC stores both fall into here:
317  if (allowStore) {
318  // We write address paddr. However, there may be several entries with a
319  // reservation on this address (for other contextIds) and they must all
320  // be removed.
321  i = lockedAddrList.begin();
322  while (i != lockedAddrList.end()) {
323  if (i->addr == paddr) {
324  DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
325  i->contextId, paddr);
326  ContextID owner_cid = i->contextId;
327  assert(owner_cid != InvalidContextID);
328  ContextID requestor_cid = req->hasContextId() ?
329  req->contextId() :
331  if (owner_cid != requestor_cid) {
332  ThreadContext* ctx = system()->threads[owner_cid];
334  }
335  i = lockedAddrList.erase(i);
336  } else {
337  i++;
338  }
339  }
340  }
341 
342  return allowStore;
343 }
344 
345 #if TRACING_ON
346 static inline void
347 tracePacket(System *sys, const char *label, PacketPtr pkt)
348 {
349  int size = pkt->getSize();
350 #if THE_ISA != NULL_ISA
351  if (size == 1 || size == 2 || size == 4 || size == 8) {
352  ByteOrder byte_order = sys->getGuestByteOrder();
353  DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data "
354  "%#x %c\n", label, sys->getRequestorName(pkt->req->
355  requestorId()), size, pkt->getAddr(),
356  size, pkt->getAddr(), pkt->getUintX(byte_order),
357  pkt->req->isUncacheable() ? 'U' : 'C');
358  return;
359  }
360 #endif
361  DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
362  label, sys->getRequestorName(pkt->req->requestorId()),
363  size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
364  DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
365 }
366 
367 # define TRACE_PACKET(A) tracePacket(system(), A, pkt)
368 #else
369 # define TRACE_PACKET(A)
370 #endif
371 
372 void
374 {
375  if (pkt->cacheResponding()) {
376  DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n",
377  pkt->getAddr());
378  return;
379  }
380 
381  if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) {
382  DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n",
383  pkt->getAddr());
384  return;
385  }
386 
387  assert(pkt->getAddrRange().isSubset(range));
388 
389  uint8_t *host_addr = toHostAddr(pkt->getAddr());
390 
391  if (pkt->cmd == MemCmd::SwapReq) {
392  if (pkt->isAtomicOp()) {
393  if (pmemAddr) {
394  pkt->setData(host_addr);
395  (*(pkt->getAtomicOp()))(host_addr);
396  }
397  } else {
398  std::vector<uint8_t> overwrite_val(pkt->getSize());
399  uint64_t condition_val64;
400  uint32_t condition_val32;
401 
402  panic_if(!pmemAddr, "Swap only works if there is real memory " \
403  "(i.e. null=False)");
404 
405  bool overwrite_mem = true;
406  // keep a copy of our possible write value, and copy what is at the
407  // memory address into the packet
408  pkt->writeData(&overwrite_val[0]);
409  pkt->setData(host_addr);
410 
411  if (pkt->req->isCondSwap()) {
412  if (pkt->getSize() == sizeof(uint64_t)) {
413  condition_val64 = pkt->req->getExtraData();
414  overwrite_mem = !std::memcmp(&condition_val64, host_addr,
415  sizeof(uint64_t));
416  } else if (pkt->getSize() == sizeof(uint32_t)) {
417  condition_val32 = (uint32_t)pkt->req->getExtraData();
418  overwrite_mem = !std::memcmp(&condition_val32, host_addr,
419  sizeof(uint32_t));
420  } else
421  panic("Invalid size for conditional read/write\n");
422  }
423 
424  if (overwrite_mem)
425  std::memcpy(host_addr, &overwrite_val[0], pkt->getSize());
426 
427  assert(!pkt->req->isInstFetch());
428  TRACE_PACKET("Read/Write");
429  stats.numOther[pkt->req->requestorId()]++;
430  }
431  } else if (pkt->isRead()) {
432  assert(!pkt->isWrite());
433  if (pkt->isLLSC()) {
434  assert(!pkt->fromCache());
435  // if the packet is not coming from a cache then we have
436  // to do the LL/SC tracking here
437  trackLoadLocked(pkt);
438  }
439  if (pmemAddr) {
440  pkt->setData(host_addr);
441  }
442  TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
443  stats.numReads[pkt->req->requestorId()]++;
444  stats.bytesRead[pkt->req->requestorId()] += pkt->getSize();
445  if (pkt->req->isInstFetch())
446  stats.bytesInstRead[pkt->req->requestorId()] += pkt->getSize();
447  } else if (pkt->isInvalidate() || pkt->isClean()) {
448  assert(!pkt->isWrite());
449  // in a fastmem system invalidating and/or cleaning packets
450  // can be seen due to cache maintenance requests
451 
452  // no need to do anything
453  } else if (pkt->isWrite()) {
454  if (writeOK(pkt)) {
455  if (pmemAddr) {
456  pkt->writeData(host_addr);
457  DPRINTF(MemoryAccess, "%s write due to %s\n",
458  __func__, pkt->print());
459  }
460  assert(!pkt->req->isInstFetch());
461  TRACE_PACKET("Write");
462  stats.numWrites[pkt->req->requestorId()]++;
463  stats.bytesWritten[pkt->req->requestorId()] += pkt->getSize();
464  }
465  } else {
466  panic("Unexpected packet %s", pkt->print());
467  }
468 
469  if (pkt->needsResponse()) {
470  pkt->makeResponse();
471  }
472 }
473 
474 void
476 {
477  assert(pkt->getAddrRange().isSubset(range));
478 
479  uint8_t *host_addr = toHostAddr(pkt->getAddr());
480 
481  if (pkt->isRead()) {
482  if (pmemAddr) {
483  pkt->setData(host_addr);
484  }
485  TRACE_PACKET("Read");
486  pkt->makeResponse();
487  } else if (pkt->isWrite()) {
488  if (pmemAddr) {
489  pkt->writeData(host_addr);
490  }
491  TRACE_PACKET("Write");
492  pkt->makeResponse();
493  } else if (pkt->isPrint()) {
494  Packet::PrintReqState *prs =
495  dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
496  assert(prs);
497  // Need to call printLabels() explicitly since we're not going
498  // through printObj().
499  prs->printLabels();
500  // Right now we just print the single byte at the specified address.
501  ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *host_addr);
502  } else {
503  panic("AbstractMemory: unimplemented functional command %s",
504  pkt->cmdString());
505  }
506 }
AbstractMemory::MemStats::bytesRead
Stats::Vector bytesRead
Number of total bytes read from this memory.
Definition: abstract_mem.hh:175
Stats::Group::regStats
virtual void regStats()
Callback to set stat parameters.
Definition: group.cc:64
AbstractMemory::checkLockedAddrList
bool checkLockedAddrList(PacketPtr pkt)
Definition: abstract_mem.cc:281
AbstractMemory::toHostAddr
uint8_t * toHostAddr(Addr addr) const
Transform a gem5 address space address into its physical counterpart in the host address space.
Definition: abstract_mem.hh:275
Loader::MemoryImage::offset
MemoryImage & offset(Addr by)
Definition: memory_image.hh:121
MemCmd::WritebackClean
@ WritebackClean
Definition: packet.hh:89
warn
#define warn(...)
Definition: logging.hh:239
Packet::getAddrRange
AddrRange getAddrRange() const
Get address range to which this packet belongs.
Definition: packet.cc:241
MemBackdoor
Definition: backdoor.hh:38
AbstractMemory::getAddrRange
AddrRange getAddrRange() const
Get the address range.
Definition: abstract_mem.cc:242
system.hh
Packet::cacheResponding
bool cacheResponding() const
Definition: packet.hh:619
Loader::MemoryImage::write
bool write(const PortProxy &proxy) const
Definition: memory_image.cc:50
SimObject::initState
virtual void initState()
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: sim_object.cc:91
Packet::getAddr
Addr getAddr() const
Definition: packet.hh:754
Packet::writeData
void writeData(uint8_t *p) const
Copy data from the packet to the memory at the provided pointer.
Definition: packet.hh:1254
abstract_mem.hh
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
AddrRange::interleaved
bool interleaved() const
Determine if the range is interleaved or not.
Definition: addr_range.hh:257
TRACE_PACKET
#define TRACE_PACKET(A)
Definition: abstract_mem.cc:369
Flags
Definition: flags.hh:33
AbstractMemory::setBackingStore
void setBackingStore(uint8_t *pmem_addr)
Set the host memory backing store to be used by this memory controller.
Definition: abstract_mem.cc:103
System::getGuestByteOrder
ByteOrder getGuestByteOrder() const
Get the guest byte order.
Definition: system.hh:388
LockedAddr
Locked address class that represents a physical address and a context id.
Definition: abstract_mem.hh:62
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:231
Packet::isRead
bool isRead() const
Definition: packet.hh:556
Packet::fromCache
bool fromCache() const
Definition: packet.hh:574
MemCmd::CleanEvict
@ CleanEvict
Definition: packet.hh:91
Loader::createObjectFile
ObjectFile * createObjectFile(const std::string &fname, bool raw)
Definition: object_file.cc:61
Packet::isAtomicOp
bool isAtomicOp() const
Definition: packet.hh:793
AddrRange::contains
bool contains(const Addr &a) const
Determine if the range contains an address.
Definition: addr_range.hh:435
Packet::isInvalidate
bool isInvalidate() const
Definition: packet.hh:571
RequestPtr
std::shared_ptr< Request > RequestPtr
Definition: request.hh:82
Packet::req
RequestPtr req
A pointer to the original request.
Definition: packet.hh:340
Packet::isLLSC
bool isLLSC() const
Definition: packet.hh:582
std::vector< uint8_t >
InvalidContextID
const ContextID InvalidContextID
Definition: types.hh:232
Packet::getSize
unsigned getSize() const
Definition: packet.hh:764
Packet::print
void print(std::ostream &o, int verbosity=0, const std::string &prefix="") const
Definition: packet.cc:389
MemBackdoor::invalidate
void invalidate()
Definition: backdoor.hh:109
Loader::MemoryImage::maxAddr
Addr maxAddr() const
Definition: memory_image.hh:131
AbstractMemory::functionalAccess
void functionalAccess(PacketPtr pkt)
Perform an untimed memory read or write without changing anything but the memory itself.
Definition: abstract_mem.cc:475
Loader::MemoryImage
Definition: memory_image.hh:48
Packet::setData
void setData(const uint8_t *p)
Copy data into the packet from the provided pointer.
Definition: packet.hh:1225
ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:231
AbstractMemory
An abstract memory represents a contiguous block of physical memory, with an associated address range...
Definition: abstract_mem.hh:104
AbstractMemory::stats
AbstractMemory::MemStats stats
AbstractMemory::AbstractMemory
AbstractMemory(const AbstractMemory &)
Loader::debugSymbolTable
SymbolTable debugSymbolTable
Global unified debugging symbol table (for target).
Definition: symtab.cc:47
MemCmd::SwapReq
@ SwapReq
Definition: packet.hh:111
AbstractMemory::access
void access(PacketPtr pkt)
Perform an untimed memory access and update all the state (e.g.
Definition: abstract_mem.cc:373
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
AbstractMemory::trackLoadLocked
void trackLoadLocked(PacketPtr pkt)
Definition: abstract_mem.cc:250
AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:68
AbstractMemory::MemStats::numWrites
Stats::Vector numWrites
Number of write requests.
Definition: abstract_mem.hh:183
AbstractMemory::size
uint64_t size() const
Get the memory size.
Definition: abstract_mem.hh:285
Packet::getUintX
uint64_t getUintX(ByteOrder endian) const
Get the data in the packet byte swapped from the specified endianness and zero-extended to 64 bits.
Definition: packet.cc:350
System
Definition: system.hh:73
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
simSeconds
Stats::Formula simSeconds
Definition: stat_control.cc:61
Packet::cmdString
const std::string & cmdString() const
Return the string name of the cmd field (for debugging and tracing).
Definition: packet.hh:551
MemBackdoor::ptr
uint8_t * ptr() const
Definition: backdoor.hh:58
Packet::needsResponse
bool needsResponse() const
Definition: packet.hh:570
AddrRange::valid
bool valid() const
Determine if the range is valid.
Definition: addr_range.hh:307
AbstractMemory::MemStats::numReads
Stats::Vector numReads
Number of read requests.
Definition: abstract_mem.hh:181
Packet::PrintReqState::os
std::ostream & os
Definition: packet.hh:462
Packet::getAtomicOp
AtomicOpFunctor * getAtomicOp() const
Accessor function to atomic op.
Definition: packet.hh:792
AbstractMemory::params
const Params * params() const
Definition: abstract_mem.hh:255
Packet::PrintReqState::curPrefix
const std::string & curPrefix()
Returns the current line prefix.
Definition: packet.hh:471
AbstractMemory::MemStats::bytesInstRead
Stats::Vector bytesInstRead
Number of instruction bytes read from this memory.
Definition: abstract_mem.hh:177
AbstractMemory::MemStats::MemStats
MemStats(AbstractMemory &mem)
Definition: abstract_mem.cc:115
Packet::PrintReqState
Object used to maintain state of a PrintReq.
Definition: packet.hh:442
ArmISA::globalClearExclusive
void globalClearExclusive(XC *xc)
Definition: locked_mem.hh:150
AbstractMemory::pmemAddr
uint8_t * pmemAddr
Definition: abstract_mem.hh:112
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Packet::makeResponse
void makeResponse()
Take a request packet and modify it in place to be suitable for returning as a response to that reque...
Definition: packet.hh:1004
DDUMP
#define DDUMP(x, data, count)
DPRINTF is a debugging trace facility that allows one to selectively enable tracing statements.
Definition: trace.hh:233
packet_access.hh
LockedAddr::mask
static Addr mask(Addr paddr)
Definition: abstract_mem.hh:78
Stats::nozero
const FlagsType nozero
Don't print if this is zero.
Definition: info.hh:57
AbstractMemory::range
AddrRange range
Definition: abstract_mem.hh:109
Loader::MemoryImage::minAddr
Addr minAddr() const
Definition: memory_image.hh:140
SimObject::name
virtual const std::string name() const
Definition: sim_object.hh:133
Packet::cmd
MemCmd cmd
The command field of the packet.
Definition: packet.hh:335
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:197
System::threads
Threads threads
Definition: system.hh:309
PortProxy
This object is a proxy for a port or other object which implements the functional response protocol,...
Definition: port_proxy.hh:80
AddrRange::start
Addr start() const
Get the start address of the range.
Definition: addr_range.hh:314
base.hh
System::maxRequestors
RequestorID maxRequestors()
Get the number of requestors registered in the system.
Definition: system.hh:503
AbstractMemory::lockedAddrList
std::list< LockedAddr > lockedAddrList
Definition: abstract_mem.hh:126
AddrRange::to_string
std::string to_string() const
Get a string representation of the range.
Definition: addr_range.hh:330
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
Packet::PrintReqState::printLabels
void printLabels()
Print all of the pending unprinted labels on the stack.
Definition: packet.cc:474
Packet::isClean
bool isClean() const
Definition: packet.hh:573
AbstractMemory::writeOK
bool writeOK(PacketPtr pkt)
Definition: abstract_mem.hh:146
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:127
Packet::isWrite
bool isWrite() const
Definition: packet.hh:557
mem
bool_vector8 mem[]
Definition: reset_stim.h:43
System::getRequestorName
std::string getRequestorName(RequestorID requestor_id)
Get the name of an object for a given request id.
Definition: system.cc:651
Stats
Definition: statistics.cc:61
AbstractMemory::Params
AbstractMemoryParams Params
Definition: abstract_mem.hh:207
AddrRange::isSubset
bool isSubset(const AddrRange &r) const
Determine if this range is a subset of another range, i.e.
Definition: addr_range.hh:410
Loader::SymbolTable::insert
bool insert(const Symbol &symbol)
Definition: symtab.cc:58
Packet::senderState
SenderState * senderState
This packet's sender state.
Definition: packet.hh:508
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
Packet::isPrint
bool isPrint() const
Definition: packet.hh:584
std::list
STL list class.
Definition: stl.hh:51
AbstractMemory::backdoor
MemBackdoor backdoor
Definition: abstract_mem.hh:115
System::cacheLineSize
unsigned int cacheLineSize() const
Get the cache line size of the system.
Definition: system.hh:307
AbstractMemory::system
System * system() const
read the system pointer Implemented for completeness with the setter
Definition: abstract_mem.hh:244
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:219
AbstractMemory::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: abstract_mem.cc:72
Stats::total
const FlagsType total
Print the total.
Definition: info.hh:49
AddrRange::size
Addr size() const
Get the size of the address range.
Definition: addr_range.hh:297
AbstractMemory::MemStats::bytesWritten
Stats::Vector bytesWritten
Number of bytes written to this memory.
Definition: abstract_mem.hh:179
object_file.hh
Packet::getConstPtr
const T * getConstPtr() const
Definition: packet.hh:1166
memory_image.hh
thread_context.hh
Stats::nonan
const FlagsType nonan
Don't print if this is NAN.
Definition: info.hh:59
AbstractMemory::MemStats::numOther
Stats::Vector numOther
Number of other requests.
Definition: abstract_mem.hh:185
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
AbstractMemory::MemStats::regStats
void regStats() override
Callback to set stat parameters.
Definition: abstract_mem.cc:141

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