gem5  v20.1.0.0
process.cc
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1 /*
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28 
29 #include "arch/sparc/process.hh"
30 
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/handlers.hh"
33 #include "arch/sparc/isa_traits.hh"
34 #include "arch/sparc/registers.hh"
35 #include "arch/sparc/types.hh"
38 #include "base/logging.hh"
39 #include "cpu/thread_context.hh"
40 #include "debug/Stack.hh"
41 #include "mem/page_table.hh"
42 #include "params/Process.hh"
43 #include "sim/aux_vector.hh"
44 #include "sim/process_impl.hh"
45 #include "sim/syscall_return.hh"
46 #include "sim/system.hh"
47 
48 using namespace std;
49 using namespace SparcISA;
50 
53 };
54 
55 SparcProcess::SparcProcess(ProcessParams *params,
56  ::Loader::ObjectFile *objFile, Addr _StackBias)
57  : Process(params,
58  new EmulationPageTable(params->name, params->pid, PageBytes),
59  objFile),
60  StackBias(_StackBias)
61 {
62  fatal_if(params->useArchPT, "Arch page tables not implemented.");
63  // Initialize these to 0s
64  fillStart = 0;
65  spillStart = 0;
66 }
67 
68 void
70 {
71  PCState pc = tc->pcState();
72  switch (trapNum) {
73  case 0x01: // Software breakpoint
74  warn("Software breakpoint encountered at pc %#x.\n", pc.pc());
75  break;
76  case 0x02: // Division by zero
77  warn("Software signaled a division by zero at pc %#x.\n", pc.pc());
78  break;
79  case 0x03: // Flush window trap
80  flushWindows(tc);
81  break;
82  case 0x04: // Clean windows
83  warn("Ignoring process request for clean register "
84  "windows at pc %#x.\n", pc.pc());
85  break;
86  case 0x05: // Range check
87  warn("Software signaled a range check at pc %#x.\n", pc.pc());
88  break;
89  case 0x06: // Fix alignment
90  warn("Ignoring process request for os assisted unaligned accesses "
91  "at pc %#x.\n", pc.pc());
92  break;
93  case 0x07: // Integer overflow
94  warn("Software signaled an integer overflow at pc %#x.\n", pc.pc());
95  break;
96  case 0x32: // Get integer condition codes
97  warn("Ignoring process request to get the integer condition codes "
98  "at pc %#x.\n", pc.pc());
99  break;
100  case 0x33: // Set integer condition codes
101  warn("Ignoring process request to set the integer condition codes "
102  "at pc %#x.\n", pc.pc());
103  break;
104  default:
105  panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
106  }
107 }
108 
109 void
111 {
113 
115  // From the SPARC ABI
116 
117  // Setup default FP state
119 
121 
122  /*
123  * Register window management registers
124  */
125 
126  // No windows contain info from other programs
127  tc->setIntReg(INTREG_OTHERWIN, 0);
128  // There are no windows to pop
130  // All windows are available to save into
132  // All windows are "clean"
134  // Start with register window 0
135  tc->setMiscReg(MISCREG_CWP, 0);
136  // Always use spill and fill traps 0
137  tc->setIntReg(INTREG_WSTATE, 0);
138  // Set the trap level to 0
140  // Set the ASI register to something fixed
142 
143  // Set the MMU Primary Context Register to hold the process' pid
145 
146  /*
147  * T1 specific registers
148  */
149  // Turn on the icache, dcache, dtb translation, and itb translation.
151 }
152 
153 void
155 {
157 
159  // The process runs in user mode with 32 bit addresses
160  PSTATE pstate = 0;
161  pstate.ie = 1;
162  pstate.am = 1;
163  tc->setMiscReg(MISCREG_PSTATE, pstate);
164 
165  argsInit(32 / 8, PageBytes);
166 }
167 
168 void
170 {
172 
174  // The process runs in user mode
175  PSTATE pstate = 0;
176  pstate.ie = 1;
177  tc->setMiscReg(MISCREG_PSTATE, pstate);
178 
179  argsInit(sizeof(RegVal), PageBytes);
180 }
181 
182 template<class IntType>
183 void
185 {
186  int intSize = sizeof(IntType);
187 
189 
190  string filename;
191  if (argv.size() < 1)
192  filename = "";
193  else
194  filename = argv[0];
195 
196  // Even for a 32 bit process, the ABI says we still need to
197  // maintain double word alignment of the stack pointer.
198  uint64_t align = 16;
199 
200  enum hardwareCaps
201  {
202  M5_HWCAP_SPARC_FLUSH = 1,
203  M5_HWCAP_SPARC_STBAR = 2,
204  M5_HWCAP_SPARC_SWAP = 4,
205  M5_HWCAP_SPARC_MULDIV = 8,
206  M5_HWCAP_SPARC_V9 = 16,
207  // This one should technically only be set
208  // if there is a cheetah or cheetah_plus tlb,
209  // but we'll use it all the time
210  M5_HWCAP_SPARC_ULTRA3 = 32
211  };
212 
213  const int64_t hwcap =
214  M5_HWCAP_SPARC_FLUSH |
215  M5_HWCAP_SPARC_STBAR |
216  M5_HWCAP_SPARC_SWAP |
217  M5_HWCAP_SPARC_MULDIV |
218  M5_HWCAP_SPARC_V9 |
219  M5_HWCAP_SPARC_ULTRA3;
220 
221  // Setup the auxilliary vectors. These will already have endian conversion.
222  // Auxilliary vectors are loaded only for elf formatted executables.
223  auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
224  if (elfObject) {
225  // Bits which describe the system hardware capabilities
226  auxv.emplace_back(M5_AT_HWCAP, hwcap);
227  // The system page size
228  auxv.emplace_back(M5_AT_PAGESZ, SparcISA::PageBytes);
229  // Defined to be 100 in the kernel source.
230  // Frequency at which times() increments
231  auxv.emplace_back(M5_AT_CLKTCK, 100);
232  // For statically linked executables, this is the virtual address of
233  // the program header tables if they appear in the executable image
234  auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
235  // This is the size of a program header entry from the elf file.
236  auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
237  // This is the number of program headers from the original elf file.
238  auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
239  // This is the base address of the ELF interpreter; it should be
240  // zero for static executables or contain the base address for
241  // dynamic executables.
242  auxv.emplace_back(M5_AT_BASE, getBias());
243  // This is hardwired to 0 in the elf loading code in the kernel
244  auxv.emplace_back(M5_AT_FLAGS, 0);
245  // The entry point to the program
246  auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
247  // Different user and group IDs
248  auxv.emplace_back(M5_AT_UID, uid());
249  auxv.emplace_back(M5_AT_EUID, euid());
250  auxv.emplace_back(M5_AT_GID, gid());
251  auxv.emplace_back(M5_AT_EGID, egid());
252  // Whether to enable "secure mode" in the executable
253  auxv.emplace_back(M5_AT_SECURE, 0);
254  // The address of 16 "random" bytes.
255  auxv.emplace_back(M5_AT_RANDOM, 0);
256  }
257 
258  // Figure out how big the initial stack needs to be
259 
260  // The unaccounted for 8 byte 0 at the top of the stack
261  int sentry_size = 8;
262 
263  // This is the name of the file which is present on the initial stack
264  // It's purpose is to let the user space linker examine the original file.
265  int file_name_size = filename.size() + 1;
266 
267  const int numRandomBytes = 16;
268  int aux_data_size = numRandomBytes;
269 
270  int env_data_size = 0;
271  for (int i = 0; i < envp.size(); ++i) {
272  env_data_size += envp[i].size() + 1;
273  }
274  int arg_data_size = 0;
275  for (int i = 0; i < argv.size(); ++i) {
276  arg_data_size += argv[i].size() + 1;
277  }
278 
279  // The info_block.
280  int base_info_block_size =
281  sentry_size + file_name_size + env_data_size + arg_data_size;
282 
283  int info_block_size = roundUp(base_info_block_size, align);
284 
285  int info_block_padding = info_block_size - base_info_block_size;
286 
287  // Each auxilliary vector is two words
288  int aux_array_size = intSize * 2 * (auxv.size() + 1);
289 
290  int envp_array_size = intSize * (envp.size() + 1);
291  int argv_array_size = intSize * (argv.size() + 1);
292 
293  int argc_size = intSize;
294  int window_save_size = intSize * 16;
295 
296  // Figure out the size of the contents of the actual initial frame
297  int frame_size =
298  aux_array_size +
299  envp_array_size +
300  argv_array_size +
301  argc_size +
302  window_save_size;
303 
304  // There needs to be padding after the auxiliary vector data so that the
305  // very bottom of the stack is aligned properly.
306  int aligned_partial_size = roundUp(frame_size, align);
307  int aux_padding = aligned_partial_size - frame_size;
308 
309  int space_needed =
310  info_block_size +
311  aux_data_size +
312  aux_padding +
313  frame_size;
314 
315  memState->setStackMin(memState->getStackBase() - space_needed);
316  memState->setStackMin(roundDown(memState->getStackMin(), align));
317  memState->setStackSize(memState->getStackBase() - memState->getStackMin());
318 
319  // Allocate space for the stack
320  memState->mapRegion(roundDown(memState->getStackMin(), pageSize),
321  roundUp(memState->getStackSize(), pageSize), "stack");
322 
323  // map out initial stack contents
324  IntType sentry_base = memState->getStackBase() - sentry_size;
325  IntType file_name_base = sentry_base - file_name_size;
326  IntType env_data_base = file_name_base - env_data_size;
327  IntType arg_data_base = env_data_base - arg_data_size;
328  IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
329  IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
330  IntType envp_array_base = auxv_array_base - envp_array_size;
331  IntType argv_array_base = envp_array_base - argv_array_size;
332  IntType argc_base = argv_array_base - argc_size;
333 #if TRACING_ON
334  IntType window_save_base = argc_base - window_save_size;
335 #endif
336 
337  DPRINTF(Stack, "The addresses of items on the initial stack:\n");
338  DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base);
339  DPRINTF(Stack, "filename = %s\n", filename);
340  DPRINTF(Stack, "%#x - file name\n", file_name_base);
341  DPRINTF(Stack, "%#x - env data\n", env_data_base);
342  DPRINTF(Stack, "%#x - arg data\n", arg_data_base);
343  DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base);
344  DPRINTF(Stack, "%#x - envp array\n", envp_array_base);
345  DPRINTF(Stack, "%#x - argv array\n", argv_array_base);
346  DPRINTF(Stack, "%#x - argc \n", argc_base);
347  DPRINTF(Stack, "%#x - window save\n", window_save_base);
348  DPRINTF(Stack, "%#x - stack min\n", memState->getStackMin());
349 
350  assert(window_save_base == memState->getStackMin());
351 
352  // write contents to stack
353 
354  // figure out argc
355  IntType argc = argv.size();
356  IntType guestArgc = htobe(argc);
357 
358  // Write out the sentry void *
359  uint64_t sentry_NULL = 0;
360  initVirtMem->writeBlob(sentry_base, &sentry_NULL, sentry_size);
361 
362  // Write the file name
363  initVirtMem->writeString(file_name_base, filename.c_str());
364 
365  // Fix up the aux vectors which point to data.
366  for (auto &aux: auxv) {
367  if (aux.type == M5_AT_RANDOM)
368  aux.val = aux_data_base;
369  }
370 
371  // Copy the aux stuff
372  Addr auxv_array_end = auxv_array_base;
373  for (const auto &aux: auxv) {
374  initVirtMem->write(auxv_array_end, aux, GuestByteOrder);
375  auxv_array_end += sizeof(aux);
376  }
377 
378  // Write out the terminating zeroed auxilliary vector
379  const AuxVector<IntType> zero(0, 0);
380  initVirtMem->write(auxv_array_end, zero);
381  auxv_array_end += sizeof(zero);
382 
383  copyStringArray(envp, envp_array_base, env_data_base,
384  ByteOrder::big, *initVirtMem);
385  copyStringArray(argv, argv_array_base, arg_data_base,
386  ByteOrder::big, *initVirtMem);
387 
388  initVirtMem->writeBlob(argc_base, &guestArgc, intSize);
389 
390  // Set up space for the trap handlers into the processes address space.
391  // Since the stack grows down and there is reserved address space abov
392  // it, we can put stuff above it and stay out of the way.
393  fillStart = memState->getStackBase();
395 
397  // Set up the thread context to start running the process
398  // assert(NumArgumentRegs >= 2);
399  // tc->setIntReg(ArgumentReg[0], argc);
400  // tc->setIntReg(ArgumentReg[1], argv_array_base);
401  tc->setIntReg(StackPointerReg, memState->getStackMin() - StackBias);
402 
403  // %g1 is a pointer to a function that should be run at exit. Since we
404  // don't have anything like that, it should be set to 0.
405  tc->setIntReg(1, 0);
406 
407  tc->pcState(getStartPC());
408 
409  // Align the "stack_min" to a page boundary.
410  memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
411 }
412 
413 void
414 Sparc64Process::argsInit(int intSize, int pageSize)
415 {
416  SparcProcess::argsInit<uint64_t>(pageSize);
417 
418  // Stuff the trap handlers into the process address space
419  initVirtMem->writeBlob(fillStart,
420  fillHandler64, sizeof(MachInst) * numFillInsts);
421  initVirtMem->writeBlob(spillStart,
423 }
424 
425 void
426 Sparc32Process::argsInit(int intSize, int pageSize)
427 {
428  SparcProcess::argsInit<uint32_t>(pageSize);
429 
430  // Stuff the trap handlers into the process address space
431  initVirtMem->writeBlob(fillStart,
432  fillHandler32, sizeof(MachInst) * numFillInsts);
433  initVirtMem->writeBlob(spillStart,
435 }
436 
438 {
439  RegVal Cansave = tc->readIntReg(INTREG_CANSAVE);
440  RegVal Canrestore = tc->readIntReg(INTREG_CANRESTORE);
441  RegVal Otherwin = tc->readIntReg(INTREG_OTHERWIN);
442  RegVal CWP = tc->readMiscReg(MISCREG_CWP);
443  RegVal origCWP = CWP;
444  CWP = (CWP + Cansave + 2) % NWindows;
445  while (NWindows - 2 - Cansave != 0) {
446  if (Otherwin) {
447  panic("Otherwin non-zero.\n");
448  } else {
449  tc->setMiscReg(MISCREG_CWP, CWP);
450  // Do the stores
452  for (int index = 16; index < 32; index++) {
453  uint32_t regVal = tc->readIntReg(index);
454  regVal = htobe(regVal);
455  if (!tc->getVirtProxy().tryWriteBlob(
456  sp + (index - 16) * 4, (uint8_t *)&regVal, 4)) {
457  warn("Failed to save register to the stack when "
458  "flushing windows.\n");
459  }
460  }
461  Canrestore--;
462  Cansave++;
463  CWP = (CWP + 1) % NWindows;
464  }
465  }
466  tc->setIntReg(INTREG_CANSAVE, Cansave);
467  tc->setIntReg(INTREG_CANRESTORE, Canrestore);
468  tc->setMiscReg(MISCREG_CWP, origCWP);
469 }
470 
471 void
473 {
474  RegVal Cansave = tc->readIntReg(INTREG_CANSAVE);
475  RegVal Canrestore = tc->readIntReg(INTREG_CANRESTORE);
476  RegVal Otherwin = tc->readIntReg(INTREG_OTHERWIN);
477  RegVal CWP = tc->readMiscReg(MISCREG_CWP);
478  RegVal origCWP = CWP;
479  CWP = (CWP + Cansave + 2) % NWindows;
480  while (NWindows - 2 - Cansave != 0) {
481  if (Otherwin) {
482  panic("Otherwin non-zero.\n");
483  } else {
484  tc->setMiscReg(MISCREG_CWP, CWP);
485  // Do the stores
487  for (int index = 16; index < 32; index++) {
488  RegVal regVal = tc->readIntReg(index);
489  regVal = htobe(regVal);
490  if (!tc->getVirtProxy().tryWriteBlob(
491  sp + 2047 + (index - 16) * 8, (uint8_t *)&regVal, 8)) {
492  warn("Failed to save register to the stack when "
493  "flushing windows.\n");
494  }
495  }
496  Canrestore--;
497  Cansave++;
498  CWP = (CWP + 1) % NWindows;
499  }
500  }
501  tc->setIntReg(INTREG_CANSAVE, Cansave);
502  tc->setIntReg(INTREG_CANRESTORE, Canrestore);
503  tc->setMiscReg(MISCREG_CWP, origCWP);
504 }
SparcISA::MachInst
uint32_t MachInst
Definition: types.hh:38
SparcISA::MISCREG_PSTATE
@ MISCREG_PSTATE
Definition: miscregs.hh:62
SparcISA::INTREG_O0
@ INTREG_O0
Definition: registers.hh:67
roundDown
T roundDown(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:150
warn
#define warn(...)
Definition: logging.hh:239
process.hh
system.hh
SparcProcess::SyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: process.hh:73
Process::envp
std::vector< std::string > envp
Definition: process.hh:217
SparcISA::fillHandler64
const MachInst fillHandler64[numFillInsts]
Definition: handlers.hh:43
MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:44
Process::gid
uint64_t gid()
Definition: process.hh:82
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
Process
Definition: process.hh:65
M5_AT_UID
@ M5_AT_UID
Definition: aux_vector.hh:69
Sparc64Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:169
handlers.hh
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
Sparc32Process::flushWindows
void flushWindows(ThreadContext *tc) override
Definition: process.cc:437
Process::argv
std::vector< std::string > argv
Definition: process.hh:216
ThreadContext::setIntReg
virtual void setIntReg(RegIndex reg_idx, RegVal val)=0
SparcISA::spillHandler32
const MachInst spillHandler32[numSpillInsts]
Definition: handlers.hh:151
SparcISA::INTREG_CLEANWIN
@ INTREG_CLEANWIN
Definition: registers.hh:83
M5_AT_PAGESZ
@ M5_AT_PAGESZ
Definition: aux_vector.hh:64
M5_AT_SECURE
@ M5_AT_SECURE
Definition: aux_vector.hh:76
M5_AT_PHENT
@ M5_AT_PHENT
Definition: aux_vector.hh:62
SparcISA::INTREG_O3
@ INTREG_O3
Definition: registers.hh:67
ArmISA::GuestByteOrder
const ByteOrder GuestByteOrder
Definition: isa_traits.hh:49
GenericISA::DelaySlotUPCState
Definition: types.hh:391
process_impl.hh
M5_AT_EUID
@ M5_AT_EUID
Definition: aux_vector.hh:70
SparcISA::MISCREG_FSR
@ MISCREG_FSR
Floating Point Status Register.
Definition: miscregs.hh:83
std::vector< int >
SparcISA::INTREG_OTHERWIN
@ INTREG_OTHERWIN
Definition: registers.hh:84
SparcISA::ASI_PRIMARY
@ ASI_PRIMARY
Definition: asi.hh:163
Process::initVirtMem
std::unique_ptr< SETranslatingPortProxy > initVirtMem
Definition: process.hh:177
SparcISA::INTREG_CANSAVE
@ INTREG_CANSAVE
Definition: registers.hh:81
SparcISA::NWindows
const int NWindows
Definition: sparc_traits.hh:41
SparcISA::INTREG_O4
@ INTREG_O4
Definition: registers.hh:68
Process::egid
uint64_t egid()
Definition: process.hh:83
Loader::ElfObject
Definition: elf_object.hh:59
sc_dt::align
void align(const scfx_rep &lhs, const scfx_rep &rhs, int &new_wp, int &len_mant, scfx_mant_ref &lhs_mant, scfx_mant_ref &rhs_mant)
Definition: scfx_rep.cc:2083
SparcProcess::StackBias
const Addr StackBias
Definition: process.hh:48
SparcISA::spillHandler64
const MachInst spillHandler64[numSpillInsts]
Definition: handlers.hh:115
SparcISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:40
PortProxy::tryWriteBlob
virtual bool tryWriteBlob(Addr addr, const void *p, int size) const
Write size bytes from p to address.
Definition: port_proxy.hh:152
M5_AT_ENTRY
@ M5_AT_ENTRY
Definition: aux_vector.hh:67
SparcISA
Definition: asi.cc:31
M5_AT_BASE
@ M5_AT_BASE
Definition: aux_vector.hh:65
Loader::ObjectFile
Definition: object_file.hh:70
M5_AT_PHNUM
@ M5_AT_PHNUM
Definition: aux_vector.hh:63
elf_object.hh
AuxVector
Definition: aux_vector.hh:38
SparcISA::INTREG_O5
@ INTREG_O5
Definition: registers.hh:68
SparcISA::MISCREG_TICK
@ MISCREG_TICK
Definition: miscregs.hh:43
Loader::ObjectFile::entryPoint
Addr entryPoint() const
Definition: object_file.hh:108
syscall_return.hh
SparcISA::INTREG_O1
@ INTREG_O1
Definition: registers.hh:67
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
EmulationPageTable
Definition: page_table.hh:48
SparcISA::MISCREG_TL
@ MISCREG_TL
Definition: miscregs.hh:63
SparcProcess::spillStart
Addr spillStart
Definition: process.hh:51
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
SparcProcess::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:110
asi.hh
MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:240
SparcProcess::flushWindows
virtual void flushWindows(ThreadContext *tc)=0
isa_traits.hh
M5_AT_FLAGS
@ M5_AT_FLAGS
Definition: aux_vector.hh:66
SparcISA::numSpillInsts
const int numSpillInsts
Definition: handlers.hh:41
SparcISA::MISCREG_MMU_LSU_CTRL
@ MISCREG_MMU_LSU_CTRL
Definition: miscregs.hh:89
SparcISA::INTREG_CANRESTORE
@ INTREG_CANRESTORE
Definition: registers.hh:82
M5_AT_RANDOM
@ M5_AT_RANDOM
Definition: aux_vector.hh:78
types.hh
ArmISA::sp
Bitfield< 0 > sp
Definition: miscregs_types.hh:71
SparcProcess::fillStart
Addr fillStart
Definition: process.hh:51
Sparc64Process::argsInit
void argsInit(int intSize, int pageSize)
Definition: process.cc:414
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
Process::objFile
::Loader::ObjectFile * objFile
Definition: process.hh:213
Process::getBias
Addr getBias()
Definition: process.cc:468
SparcISA::numFillInsts
const int numFillInsts
Definition: handlers.hh:40
SimObject::params
const Params * params() const
Definition: sim_object.hh:119
name
const std::string & name()
Definition: trace.cc:50
Process::contextIds
std::vector< ContextID > contextIds
Definition: process.hh:160
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
Sparc32Process::argsInit
void argsInit(int intSize, int pageSize)
Definition: process.cc:426
ThreadContext::getVirtProxy
virtual PortProxy & getVirtProxy()=0
SparcProcess::argsInit
void argsInit(int pageSize)
Definition: process.cc:184
M5_AT_GID
@ M5_AT_GID
Definition: aux_vector.hh:71
System::threads
Threads threads
Definition: system.hh:309
ArmISA::PageBytes
const Addr PageBytes
Definition: isa_traits.hh:52
aux_vector.hh
SparcISA::MISCREG_ASI
@ MISCREG_ASI
Ancillary State Registers.
Definition: miscregs.hh:42
ArmISA::StackPointerReg
const int StackPointerReg
Definition: registers.hh:114
std
Overload hash function for BasicBlockRange type.
Definition: vec_reg.hh:587
SparcProcess::SparcProcess
SparcProcess(ProcessParams *params, ::Loader::ObjectFile *objFile, Addr _StackBias)
Definition: process.cc:55
Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:290
roundUp
T roundUp(const T &val, const U &align)
This function is used to align addresses in memory.
Definition: intmath.hh:131
Process::_pid
uint64_t _pid
Definition: process.hh:268
htobe
T htobe(T value)
Definition: byteswap.hh:142
ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
ThreadContext::setMiscReg
virtual void setMiscReg(RegIndex misc_reg, RegVal val)=0
SparcISA::INTREG_O2
@ INTREG_O2
Definition: registers.hh:67
SparcISA::fillHandler32
const MachInst fillHandler32[numFillInsts]
Definition: handlers.hh:79
logging.hh
Process::euid
uint64_t euid()
Definition: process.hh:81
Process::getStartPC
Addr getStartPC()
Definition: process.cc:476
Sparc32Process::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: process.cc:154
registers.hh
SparcISA::INTREG_WSTATE
@ INTREG_WSTATE
Definition: registers.hh:85
Sparc64Process::flushWindows
void flushWindows(ThreadContext *tc) override
Definition: process.cc:472
M5_AT_HWCAP
@ M5_AT_HWCAP
Definition: aux_vector.hh:74
ThreadContext::setMiscRegNoEffect
virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val)=0
Process::system
System * system
Definition: process.hh:163
SparcISA::MISCREG_MMU_P_CONTEXT
@ MISCREG_MMU_P_CONTEXT
MMU Internal Registers.
Definition: miscregs.hh:86
Process::uid
uint64_t uid()
Definition: process.hh:80
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
fatal_if
#define fatal_if(cond,...)
Conditional fatal macro that checks the supplied condition and only causes a fatal error if the condi...
Definition: logging.hh:219
M5_AT_CLKTCK
@ M5_AT_CLKTCK
Definition: aux_vector.hh:75
page_table.hh
copyStringArray
void copyStringArray(std::vector< std::string > &strings, AddrType array_ptr, AddrType data_ptr, const ByteOrder bo, PortProxy &memProxy)
Definition: process_impl.hh:40
M5_AT_EGID
@ M5_AT_EGID
Definition: aux_vector.hh:72
object_file.hh
SparcProcess::handleTrap
virtual void handleTrap(int trapNum, ThreadContext *tc)
Definition: process.cc:69
thread_context.hh
Process::memState
std::shared_ptr< MemState > memState
Definition: process.hh:279
RegVal
uint64_t RegVal
Definition: types.hh:168
M5_AT_PHDR
@ M5_AT_PHDR
Definition: aux_vector.hh:61
SparcISA::MISCREG_CWP
@ MISCREG_CWP
Definition: miscregs.hh:65
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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