#include <dramsim3.hh>

Inheritance diagram for DRAMsim3:

Classes
class	MemoryPort
	The memory port has to deal with its own flow control to avoid having unbounded storage that is implicitly created in the port itself. More...

Public Types
typedef DRAMsim3Params	Params

Public Types inherited from AbstractMemory
typedef AbstractMemoryParams	Params

Public Types inherited from ClockedObject
typedef ClockedObjectParams	Params
	Parameters of ClockedObject. More...

Public Types inherited from SimObject
typedef SimObjectParams	Params

Public Member Functions
	DRAMsim3 (const Params *p)

void	readComplete (unsigned id, uint64_t addr)
	Read completion callback. More...

void	writeComplete (unsigned id, uint64_t addr)
	Write completion callback. More...

DrainState	drain () override
	Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight. More...

virtual Port &	getPort (const std::string &if_name, PortID idx=InvalidPortID) override
	Get a port with a given name and index. More...

void	init () override
	init() is called after all C++ SimObjects have been created and all ports are connected. More...

void	startup () override
	startup() is the final initialization call before simulation. More...

void	resetStats () override
	Callback to reset stats. More...

Public Member Functions inherited from AbstractMemory
	AbstractMemory (const Params *p)

virtual	~AbstractMemory ()

void	initState () override
	initState() is called on each SimObject when not restoring from a checkpoint. More...

bool	isNull () const
	See if this is a null memory that should never store data and always return zero. More...

void	setBackingStore (uint8_t *pmem_addr)
	Set the host memory backing store to be used by this memory controller. More...

const std::list< LockedAddr > &	getLockedAddrList () const
	Get the list of locked addresses to allow checkpointing. More...

void	addLockedAddr (LockedAddr addr)
	Add a locked address to allow for checkpointing. More...

System *	system () const
	read the system pointer Implemented for completeness with the setter More...

void	system (System *sys)
	Set the system pointer on this memory This can't be done via a python parameter because the system needs pointers to all the memories and the reverse would create a cycle in the object graph. More...

const Params *	params () const

AddrRange	getAddrRange () const
	Get the address range. More...

uint8_t *	toHostAddr (Addr addr) const
	Transform a gem5 address space address into its physical counterpart in the host address space. More...

uint64_t	size () const
	Get the memory size. More...

Addr	start () const
	Get the start address. More...

bool	isConfReported () const
	Should this memory be passed to the kernel and part of the OS physical memory layout. More...

bool	isInAddrMap () const
	Some memories are used as shadow memories or should for other reasons not be part of the global address map. More...

bool	isKvmMap () const
	When shadow memories are in use, KVM may want to make one or the other, but cannot map both into the guest address space. More...

void	access (PacketPtr pkt)
	Perform an untimed memory access and update all the state (e.g. More...

void	functionalAccess (PacketPtr pkt)
	Perform an untimed memory read or write without changing anything but the memory itself. More...

Public Member Functions inherited from ClockedObject
	ClockedObject (const ClockedObjectParams *p)

const Params *	params () const

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from SimObject
const Params *	params () const

	SimObject (const Params *_params)

virtual	~SimObject ()

virtual const std::string	name () const

virtual void	loadState (CheckpointIn &cp)
	loadState() is called on each SimObject when restoring from a checkpoint. More...

virtual void	regProbePoints ()
	Register probe points for this object. More...

virtual void	regProbeListeners ()
	Register probe listeners for this object. More...

ProbeManager *	getProbeManager ()
	Get the probe manager for this object. More...

DrainState	drain () override
	Provide a default implementation of the drain interface for objects that don't need draining. More...

virtual void	memWriteback ()
	Write back dirty buffers to memory using functional writes. More...

virtual void	memInvalidate ()
	Invalidate the contents of memory buffers. More...

void	serialize (CheckpointOut &cp) const override
	Serialize an object. More...

void	unserialize (CheckpointIn &cp) override
	Unserialize an object. More...

Public Member Functions inherited from EventManager
EventQueue *	eventQueue () const

void	schedule (Event &event, Tick when)

void	deschedule (Event &event)

void	reschedule (Event &event, Tick when, bool always=false)

void	schedule (Event *event, Tick when)

void	deschedule (Event *event)

void	reschedule (Event *event, Tick when, bool always=false)

void	wakeupEventQueue (Tick when=(Tick) -1)
	This function is not needed by the usual gem5 event loop but may be necessary in derived EventQueues which host gem5 on other schedulers. More...

void	setCurTick (Tick newVal)

	EventManager (EventManager &em)
	Event manger manages events in the event queue. More...

	EventManager (EventManager *em)

	EventManager (EventQueue *eq)

Public Member Functions inherited from Serializable
	Serializable ()

virtual	~Serializable ()

void	serializeSection (CheckpointOut &cp, const char *name) const
	Serialize an object into a new section. More...

void	serializeSection (CheckpointOut &cp, const std::string &name) const

void	unserializeSection (CheckpointIn &cp, const char *name)
	Unserialize an a child object. More...

void	unserializeSection (CheckpointIn &cp, const std::string &name)

Public Member Functions inherited from Drainable
DrainState	drainState () const
	Return the current drain state of an object. More...

virtual void	notifyFork ()
	Notify a child process of a fork. More...

Public Member Functions inherited from Stats::Group
	Group (Group parent, const char name=nullptr)
	Construct a new statistics group. More...

virtual	~Group ()

virtual void	regStats ()
	Callback to set stat parameters. More...

virtual void	preDumpStats ()
	Callback before stats are dumped. More...

void	addStat (Stats::Info *info)
	Register a stat with this group. More...

const std::map< std::string, Group * > &	getStatGroups () const
	Get all child groups associated with this object. More...

const std::vector< Info * > &	getStats () const
	Get all stats associated with this object. More...

void	addStatGroup (const char name, Group block)
	Add a stat block as a child of this block. More...

const Info *	resolveStat (std::string name) const
	Resolve a stat by its name within this group. More...

	Group ()=delete

	Group (const Group &)=delete

Group &	operator= (const Group &)=delete

Public Member Functions inherited from Clocked
void	updateClockPeriod ()
	Update the tick to the current tick. More...

Tick	clockEdge (Cycles cycles=Cycles(0)) const
	Determine the tick when a cycle begins, by default the current one, but the argument also enables the caller to determine a future cycle. More...

Cycles	curCycle () const
	Determine the current cycle, corresponding to a tick aligned to a clock edge. More...

Tick	nextCycle () const
	Based on the clock of the object, determine the start tick of the first cycle that is at least one cycle in the future. More...

uint64_t	frequency () const

Tick	clockPeriod () const

double	voltage () const

Cycles	ticksToCycles (Tick t) const

Tick	cyclesToTicks (Cycles c) const

Protected Member Functions
Tick	recvAtomic (PacketPtr pkt)

void	recvFunctional (PacketPtr pkt)

bool	recvTimingReq (PacketPtr pkt)

void	recvRespRetry ()

Protected Member Functions inherited from AbstractMemory
bool	checkLockedAddrList (PacketPtr pkt)

void	trackLoadLocked (PacketPtr pkt)

bool	writeOK (PacketPtr pkt)

Protected Member Functions inherited from Drainable
	Drainable ()

virtual	~Drainable ()

virtual void	drainResume ()
	Resume execution after a successful drain. More...

void	signalDrainDone () const
	Signal that an object is drained. More...

Protected Member Functions inherited from Clocked
	Clocked (ClockDomain &clk_domain)
	Create a clocked object and set the clock domain based on the parameters. More...

	Clocked (Clocked &)=delete

Clocked &	operator= (Clocked &)=delete

virtual	~Clocked ()
	Virtual destructor due to inheritance. More...

void	resetClock () const
	Reset the object's clock using the current global tick value. More...

virtual void	clockPeriodUpdated ()
	A hook subclasses can implement so they can do any extra work that's needed when the clock rate is changed. More...

Private Member Functions
unsigned int	nbrOutstanding () const

void	accessAndRespond (PacketPtr pkt)
	When a packet is ready, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor. More...

void	sendResponse ()

void	tick ()
	Progress the controller one clock cycle. More...

Private Attributes
MemoryPort	port

std::function< void(uint64_t)>	read_cb
	Callback functions. More...

std::function< void(uint64_t)>	write_cb

DRAMsim3Wrapper	wrapper
	The actual DRAMsim3 wrapper. More...

bool	retryReq
	Is the connected port waiting for a retry from us. More...

bool	retryResp
	Are we waiting for a retry for sending a response. More...

Tick	startTick
	Keep track of when the wrapper is started. More...

std::unordered_map< Addr, std::queue< PacketPtr > >	outstandingReads
	Keep track of what packets are outstanding per address, and do so separately for reads and writes. More...

std::unordered_map< Addr, std::queue< PacketPtr > >	outstandingWrites

unsigned int	nbrOutstandingReads
	Count the number of outstanding transactions so that we can block any further requests until there is space in DRAMsim3 and the sending queue we need to buffer the response packets. More...

unsigned int	nbrOutstandingWrites

std::deque< PacketPtr >	responseQueue
	Queue to hold response packets until we can send them back. More...

EventFunctionWrapper	sendResponseEvent
	Event to schedule sending of responses. More...

EventFunctionWrapper	tickEvent
	Event to schedule clock ticks. More...

std::unique_ptr< Packet >	pendingDelete
	Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call. More...

Additional Inherited Members
Static Public Member Functions inherited from SimObject
static void	serializeAll (CheckpointOut &cp)
	Serialize all SimObjects in the system. More...

static SimObject *	find (const char *name)
	Find the SimObject with the given name and return a pointer to it. More...

Static Public Member Functions inherited from Serializable
static const std::string &	currentSection ()
	Gets the fully-qualified name of the active section. More...

static void	serializeAll (const std::string &cpt_dir)
	Serializes all the SimObjects. More...

static void	unserializeGlobals (CheckpointIn &cp)

Public Attributes inherited from ClockedObject
PowerState *	powerState

Protected Attributes inherited from AbstractMemory
AddrRange	range

uint8_t *	pmemAddr

MemBackdoor	backdoor

const bool	confTableReported

const bool	inAddrMap

const bool	kvmMap

std::list< LockedAddr >	lockedAddrList

System *	_system
	Pointer to the System object. More...

AbstractMemory::MemStats	stats

Protected Attributes inherited from SimObject
const SimObjectParams *	_params
	Cached copy of the object parameters. More...

Protected Attributes inherited from EventManager
EventQueue *	eventq
	A pointer to this object's event queue. More...

Detailed Description

Definition at line 55 of file dramsim3.hh.

Member Typedef Documentation

◆ Params

typedef DRAMsim3Params DRAMsim3::Params

Definition at line 178 of file dramsim3.hh.

Constructor & Destructor Documentation

◆ DRAMsim3()

DRAMsim3::DRAMsim3 ( const Params * p )

Definition at line 48 of file dramsim3.cc.

References sendResponse().

Member Function Documentation

◆ accessAndRespond()

void DRAMsim3::accessAndRespond ( PacketPtr pkt )

private

When a packet is ready, use the "access()" method in AbstractMemory to actually create the response packet, and send it back to the outside world requestor.

Parameters

pkt	The packet from the outside world

Definition at line 251 of file dramsim3.cc.

References AbstractMemory::access(), curTick(), DPRINTF, Packet::getAddr(), Packet::headerDelay, Packet::isResponse(), Packet::needsResponse(), Packet::payloadDelay, pendingDelete, responseQueue, retryResp, EventManager::schedule(), Event::scheduled(), and sendResponseEvent.

Referenced by readComplete(), and recvTimingReq().

◆ drain()

DrainState DRAMsim3::drain ( )

overridevirtual

Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are partially executed or are partially in flight.

Draining is mostly used before forking and creating a check point.

This function notifies an object that it needs to drain its state.

If the object does not need further simulation to drain internal buffers, it returns DrainState::Drained and automatically switches to the Drained state. If the object needs more simulation, it returns DrainState::Draining and automatically enters the Draining state. Other return values are invalid.

Note: An object that has entered the Drained state can be disturbed by other objects in the system and consequently stop being drained. These perturbations are not visible in the drain state. The simulator therefore repeats the draining process until all objects return DrainState::Drained on the first call to drain().

Returns: DrainState::Drained if the object is drained at this point in time, DrainState::Draining if it needs further simulation.

Implements Drainable.

Definition at line 346 of file dramsim3.cc.

References Drained, Draining, and nbrOutstanding().

◆ getPort()

Port & DRAMsim3::getPort	(	const std::string &	if_name,
		PortID	idx = `InvalidPortID`
	)

overridevirtual

Get a port with a given name and index.

This is used at binding time and returns a reference to a protocol-agnostic port.

gem5 has a request and response port interface. All memory objects are connected together via ports. These ports provide a rigid interface between these memory objects. These ports implement three different memory system modes: timing, atomic, and functional. The most important mode is the timing mode and here timing mode is used for conducting cycle-level timing experiments. The other modes are only used in special circumstances and should not be used to conduct cycle-level timing experiments. The other modes are only used in special circumstances. These ports allow SimObjects to communicate with each other.

Parameters

if_name	Port name
idx	Index in the case of a VectorPort

Returns: A reference to the given port

Reimplemented from SimObject.

Definition at line 336 of file dramsim3.cc.

References SimObject::getPort(), and port.

◆ init()

void DRAMsim3::init ( )

overridevirtual

init() is called after all C++ SimObjects have been created and all ports are connected.

Initializations that are independent of unserialization but rely on a fully instantiated and connected SimObject graph should be done here.

Reimplemented from SimObject.

Definition at line 71 of file dramsim3.cc.

References DRAMsim3Wrapper::burstSize(), fatal, SimObject::init(), Port::isConnected(), SimObject::name(), port, ResponsePort::sendRangeChange(), AbstractMemory::system(), and wrapper.

◆ nbrOutstanding()

unsigned int DRAMsim3::nbrOutstanding ( ) const

private

Definition at line 131 of file dramsim3.cc.

References nbrOutstandingReads, nbrOutstandingWrites, and responseQueue.

Referenced by drain(), recvTimingReq(), sendResponse(), tick(), and writeComplete().

◆ readComplete()

void DRAMsim3::readComplete	(	unsigned	id,
		uint64_t	addr
	)

Read completion callback.

Parameters

id	Channel id of the responder
addr	Address of the request
cycle	Internal cycle count of DRAMsim3

Definition at line 287 of file dramsim3.cc.

References accessAndRespond(), addr, DPRINTF, nbrOutstandingReads, outstandingReads, and MipsISA::p.

◆ recvAtomic()

Tick DRAMsim3::recvAtomic ( PacketPtr pkt )

protected

Definition at line 155 of file dramsim3.cc.

References AbstractMemory::access(), and Packet::cacheResponding().

◆ recvFunctional()

void DRAMsim3::recvFunctional ( PacketPtr pkt )

protected

Definition at line 164 of file dramsim3.cc.

References AbstractMemory::functionalAccess(), ArmISA::i, SimObject::name(), Packet::popLabel(), Packet::pushLabel(), responseQueue, and Packet::trySatisfyFunctional().

◆ recvRespRetry()

void DRAMsim3::recvRespRetry ( )

protected

Definition at line 241 of file dramsim3.cc.

References DPRINTF, retryResp, and sendResponse().

◆ recvTimingReq()

bool DRAMsim3::recvTimingReq ( PacketPtr pkt )

protected

Definition at line 178 of file dramsim3.cc.

References accessAndRespond(), Packet::cacheResponding(), DRAMsim3Wrapper::canAccept(), DPRINTF, DRAMsim3Wrapper::enqueue(), Packet::getAddr(), Packet::isRead(), Packet::isWrite(), nbrOutstanding(), nbrOutstandingReads, nbrOutstandingWrites, outstandingReads, outstandingWrites, pendingDelete, DRAMsim3Wrapper::queueSize(), retryReq, and wrapper.

◆ resetStats()

void DRAMsim3::resetStats ( )

overridevirtual

Callback to reset stats.

Reimplemented from Stats::Group.

Definition at line 96 of file dramsim3.cc.

References DRAMsim3Wrapper::resetStats(), and wrapper.

◆ sendResponse()

void DRAMsim3::sendResponse ( )

private

Definition at line 101 of file dramsim3.cc.

References curTick(), DPRINTF, nbrOutstanding(), nbrOutstandingReads, nbrOutstandingWrites, port, responseQueue, retryResp, EventManager::schedule(), Event::scheduled(), sendResponseEvent, ResponsePort::sendTimingResp(), and Drainable::signalDrainDone().

Referenced by DRAMsim3(), and recvRespRetry().

◆ startup()

void DRAMsim3::startup ( )

overridevirtual

startup() is the final initialization call before simulation.

All state is initialized (including unserialized state, if any, such as the curTick() value), so this is the appropriate place to schedule initial event(s) for objects that need them.

Reimplemented from SimObject.

Definition at line 87 of file dramsim3.cc.

References Clocked::clockEdge(), curTick(), EventManager::schedule(), startTick, and tickEvent.

◆ tick()

void DRAMsim3::tick ( )

private

Progress the controller one clock cycle.

Definition at line 137 of file dramsim3.cc.

References DRAMsim3Wrapper::clockPeriod(), curTick(), nbrOutstanding(), SimClock::Int::ns, port, DRAMsim3Wrapper::queueSize(), retryReq, EventManager::schedule(), ResponsePort::sendRetryReq(), AbstractMemory::system(), DRAMsim3Wrapper::tick(), tickEvent, and wrapper.

◆ writeComplete()

void DRAMsim3::writeComplete	(	unsigned	id,
		uint64_t	addr
	)

Write completion callback.

Parameters

id	Channel id of the responder
addr	Address of the request
cycle	Internal cycle count of DRAMsim3

Definition at line 313 of file dramsim3.cc.

References addr, DPRINTF, nbrOutstanding(), nbrOutstandingWrites, outstandingWrites, MipsISA::p, and Drainable::signalDrainDone().

Member Data Documentation

◆ nbrOutstandingReads

unsigned int DRAMsim3::nbrOutstandingReads

private

Count the number of outstanding transactions so that we can block any further requests until there is space in DRAMsim3 and the sending queue we need to buffer the response packets.

Definition at line 131 of file dramsim3.hh.

Referenced by nbrOutstanding(), readComplete(), recvTimingReq(), and sendResponse().

◆ nbrOutstandingWrites

unsigned int DRAMsim3::nbrOutstandingWrites

private

Definition at line 132 of file dramsim3.hh.

Referenced by nbrOutstanding(), recvTimingReq(), sendResponse(), and writeComplete().

◆ outstandingReads

std::unordered_map<Addr, std::queue<PacketPtr> > DRAMsim3::outstandingReads

private

Keep track of what packets are outstanding per address, and do so separately for reads and writes.

This is done so that we can return the right packet on completion from DRAMSim.

Definition at line 123 of file dramsim3.hh.

Referenced by readComplete(), and recvTimingReq().

◆ outstandingWrites

std::unordered_map<Addr, std::queue<PacketPtr> > DRAMsim3::outstandingWrites

private

Definition at line 124 of file dramsim3.hh.

Referenced by recvTimingReq(), and writeComplete().

◆ pendingDelete

std::unique_ptr<Packet> DRAMsim3::pendingDelete

private

Upstream caches need this packet until true is returned, so hold it for deletion until a subsequent call.

Definition at line 174 of file dramsim3.hh.

Referenced by accessAndRespond(), and recvTimingReq().

◆ port

MemoryPort DRAMsim3::port

private

Definition at line 89 of file dramsim3.hh.

Referenced by getPort(), init(), sendResponse(), and tick().

◆ read_cb

std::function<void(uint64_t)> DRAMsim3::read_cb

private

Callback functions.

Definition at line 94 of file dramsim3.hh.

◆ responseQueue

std::deque<PacketPtr> DRAMsim3::responseQueue

private

Queue to hold response packets until we can send them back.

This is needed as DRAMsim3 unconditionally passes responses back without any flow control.

Definition at line 139 of file dramsim3.hh.

Referenced by accessAndRespond(), nbrOutstanding(), recvFunctional(), and sendResponse().

◆ retryReq

bool DRAMsim3::retryReq

private

Is the connected port waiting for a retry from us.

Definition at line 105 of file dramsim3.hh.

Referenced by recvTimingReq(), and tick().

◆ retryResp

bool DRAMsim3::retryResp

private

Are we waiting for a retry for sending a response.

Definition at line 110 of file dramsim3.hh.

Referenced by accessAndRespond(), recvRespRetry(), and sendResponse().

◆ sendResponseEvent

EventFunctionWrapper DRAMsim3::sendResponseEvent

private

Event to schedule sending of responses.

Definition at line 158 of file dramsim3.hh.

Referenced by accessAndRespond(), and sendResponse().

◆ startTick

Tick DRAMsim3::startTick

private

Keep track of when the wrapper is started.

Definition at line 115 of file dramsim3.hh.

Referenced by startup().

◆ tickEvent

EventFunctionWrapper DRAMsim3::tickEvent

private

Event to schedule clock ticks.

Definition at line 168 of file dramsim3.hh.

Referenced by startup(), and tick().

◆ wrapper

DRAMsim3Wrapper DRAMsim3::wrapper

private

The actual DRAMsim3 wrapper.

Definition at line 100 of file dramsim3.hh.

Referenced by init(), recvTimingReq(), resetStats(), and tick().

◆ write_cb

std::function<void(uint64_t)> DRAMsim3::write_cb

private

Definition at line 95 of file dramsim3.hh.

The documentation for this class was generated from the following files:

mem/dramsim3.hh
mem/dramsim3.cc

Classes

Public Types

Public Member Functions

Protected Member Functions

Private Member Functions

Private Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ Params

Constructor & Destructor Documentation

◆ DRAMsim3()

Member Function Documentation

◆ accessAndRespond()

◆ drain()

◆ getPort()

◆ init()

◆ nbrOutstanding()

◆ readComplete()

◆ recvAtomic()

◆ recvFunctional()

◆ recvRespRetry()

◆ recvTimingReq()

◆ resetStats()

◆ sendResponse()

◆ startup()

◆ tick()

◆ writeComplete()

Member Data Documentation

◆ nbrOutstandingReads

◆ nbrOutstandingWrites

◆ outstandingReads

◆ outstandingWrites

◆ pendingDelete

◆ port

◆ read_cb

◆ responseQueue

◆ retryReq

◆ retryResp

◆ sendResponseEvent

◆ startTick

◆ tickEvent

◆ wrapper

◆ write_cb