gem5  v20.1.0.0
thread_context.cc
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41 
42 #include "cpu/thread_context.hh"
43 
45 #include "base/logging.hh"
46 #include "base/trace.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/base.hh"
49 #include "debug/Context.hh"
50 #include "debug/Quiesce.hh"
51 #include "params/BaseCPU.hh"
52 #include "sim/full_system.hh"
53 
54 void
56 {
57  DPRINTF(Context, "Comparing thread contexts\n");
58 
59  // First loop through the integer registers.
60  for (int i = 0; i < TheISA::NumIntRegs; ++i) {
61  RegVal t1 = one->readIntReg(i);
62  RegVal t2 = two->readIntReg(i);
63  if (t1 != t2)
64  panic("Int reg idx %d doesn't match, one: %#x, two: %#x",
65  i, t1, t2);
66  }
67 
68  // Then loop through the floating point registers.
69  for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
70  RegVal t1 = one->readFloatReg(i);
71  RegVal t2 = two->readFloatReg(i);
72  if (t1 != t2)
73  panic("Float reg idx %d doesn't match, one: %#x, two: %#x",
74  i, t1, t2);
75  }
76 
77  // Then loop through the vector registers.
78  for (int i = 0; i < TheISA::NumVecRegs; ++i) {
79  RegId rid(VecRegClass, i);
80  const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
81  const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
82  if (t1 != t2)
83  panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
84  i, t1, t2);
85  }
86 
87  // Then loop through the predicate registers.
88  for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
89  RegId rid(VecPredRegClass, i);
90  const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
92  if (t1 != t2)
93  panic("Pred reg idx %d doesn't match, one: %#x, two: %#x",
94  i, t1, t2);
95  }
96 
97  for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
98  RegVal t1 = one->readMiscRegNoEffect(i);
100  if (t1 != t2)
101  panic("Misc reg idx %d doesn't match, one: %#x, two: %#x",
102  i, t1, t2);
103  }
104 
105  // loop through the Condition Code registers.
106  for (int i = 0; i < TheISA::NumCCRegs; ++i) {
107  RegVal t1 = one->readCCReg(i);
108  RegVal t2 = two->readCCReg(i);
109  if (t1 != t2)
110  panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
111  i, t1, t2);
112  }
113  if (!(one->pcState() == two->pcState()))
114  panic("PC state doesn't match.");
115  int id1 = one->cpuId();
116  int id2 = two->cpuId();
117  if (id1 != id2)
118  panic("CPU ids don't match, one: %d, two: %d", id1, id2);
119 
120  const ContextID cid1 = one->contextId();
121  const ContextID cid2 = two->contextId();
122  if (cid1 != cid2)
123  panic("Context ids don't match, one: %d, two: %d", id1, id2);
124 
125 
126 }
127 
128 void
130 {
132 }
133 
134 
135 void
137 {
139 }
140 
141 void
143 {
144  using namespace TheISA;
145 
146  RegVal floatRegs[NumFloatRegs];
147  for (int i = 0; i < NumFloatRegs; ++i)
148  floatRegs[i] = tc.readFloatRegFlat(i);
149  // This is a bit ugly, but needed to maintain backwards
150  // compatibility.
151  arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
152 
154  for (int i = 0; i < NumVecRegs; ++i) {
155  vecRegs[i] = tc.readVecRegFlat(i);
156  }
157  SERIALIZE_CONTAINER(vecRegs);
158 
160  for (int i = 0; i < NumVecPredRegs; ++i) {
161  vecPredRegs[i] = tc.readVecPredRegFlat(i);
162  }
163  SERIALIZE_CONTAINER(vecPredRegs);
164 
165  RegVal intRegs[NumIntRegs];
166  for (int i = 0; i < NumIntRegs; ++i)
167  intRegs[i] = tc.readIntRegFlat(i);
168  SERIALIZE_ARRAY(intRegs, NumIntRegs);
169 
170  if (NumCCRegs) {
171  RegVal ccRegs[NumCCRegs];
172  for (int i = 0; i < NumCCRegs; ++i)
173  ccRegs[i] = tc.readCCRegFlat(i);
174  SERIALIZE_ARRAY(ccRegs, NumCCRegs);
175  }
176 
177  tc.pcState().serialize(cp);
178 
179  // thread_num and cpu_id are deterministic from the config
180 }
181 
182 void
184 {
185  using namespace TheISA;
186 
187  RegVal floatRegs[NumFloatRegs];
188  // This is a bit ugly, but needed to maintain backwards
189  // compatibility.
190  arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
191  for (int i = 0; i < NumFloatRegs; ++i)
192  tc.setFloatRegFlat(i, floatRegs[i]);
193 
195  UNSERIALIZE_CONTAINER(vecRegs);
196  for (int i = 0; i < NumVecRegs; ++i) {
197  tc.setVecRegFlat(i, vecRegs[i]);
198  }
199 
201  UNSERIALIZE_CONTAINER(vecPredRegs);
202  for (int i = 0; i < NumVecPredRegs; ++i) {
203  tc.setVecPredRegFlat(i, vecPredRegs[i]);
204  }
205 
206  RegVal intRegs[NumIntRegs];
207  UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
208  for (int i = 0; i < NumIntRegs; ++i)
209  tc.setIntRegFlat(i, intRegs[i]);
210 
211  if (NumCCRegs) {
212  RegVal ccRegs[NumCCRegs];
213  UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
214  for (int i = 0; i < NumCCRegs; ++i)
215  tc.setCCRegFlat(i, ccRegs[i]);
216  }
217 
218  PCState pcState;
219  pcState.unserialize(cp);
220  tc.pcState(pcState);
221 
222  // thread_num and cpu_id are deterministic from the config
223 }
224 
225 void
227 {
228  assert(ntc.getProcessPtr() == otc.getProcessPtr());
229 
230  ntc.setStatus(otc.status());
231  ntc.copyArchRegs(&otc);
232  ntc.setContextId(otc.contextId());
233  ntc.setThreadId(otc.threadId());
234 
235  if (FullSystem)
236  assert(ntc.getSystemPtr() == otc.getSystemPtr());
237 
239 }
ThreadContext::readVecPredReg
virtual const VecPredRegContainer & readVecPredReg(const RegId &reg) const =0
ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
ThreadContext::readIntRegFlat
virtual RegVal readIntRegFlat(RegIndex idx) const =0
Flat register interfaces.
ThreadContext::setVecPredRegFlat
virtual void setVecPredRegFlat(RegIndex idx, const VecPredRegContainer &val)=0
ThreadContext::setContextId
virtual void setContextId(ContextID id)=0
ThreadContext::readVecRegFlat
virtual const VecRegContainer & readVecRegFlat(RegIndex idx) const =0
ArmISA::VecRegContainer
VecReg::Container VecRegContainer
Definition: registers.hh:71
ArmISA::t2
Bitfield< 2 > t2
Definition: miscregs_types.hh:228
ThreadContext::quiesce
void quiesce()
Quiesce thread context.
Definition: thread_context.cc:129
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
UNSERIALIZE_CONTAINER
#define UNSERIALIZE_CONTAINER(member)
Definition: serialize.hh:856
ContextID
int ContextID
Globally unique thread context ID.
Definition: types.hh:231
TheISA
Definition: decode_cache.hh:37
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: registers.hh:77
serialize
void serialize(const ThreadContext &tc, CheckpointOut &cp)
Thread context serialization helpers.
Definition: thread_context.cc:142
std::vector
STL vector class.
Definition: stl.hh:37
FullSystem
bool FullSystem
The FullSystem variable can be used to determine the current mode of simulation.
Definition: root.cc:132
ThreadContext::getProcessPtr
virtual Process * getProcessPtr()=0
ThreadContext::setFloatRegFlat
virtual void setFloatRegFlat(RegIndex idx, RegVal val)=0
ThreadContext::threadId
virtual int threadId() const =0
unserialize
void unserialize(ThreadContext &tc, CheckpointIn &cp)
Definition: thread_context.cc:183
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
ThreadContext::readVecPredRegFlat
virtual const VecPredRegContainer & readVecPredRegFlat(RegIndex idx) const =0
ThreadContext::readFloatReg
virtual RegVal readFloatReg(RegIndex reg_idx) const =0
cp
Definition: cprintf.cc:40
ThreadContext::readCCRegFlat
virtual RegVal readCCRegFlat(RegIndex idx) const =0
ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
Ps2::one
Bitfield< 3 > one
Definition: types.hh:110
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
ThreadContext::setIntRegFlat
virtual void setIntRegFlat(RegIndex idx, RegVal val)=0
ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:115
System::Threads::quiesceTick
void quiesceTick(ContextID id, Tick when)
Definition: system.cc:190
System::Threads::quiesce
void quiesce(ContextID id)
Definition: system.cc:179
ThreadContext::readVecReg
virtual const VecRegContainer & readVecReg(const RegId &reg) const =0
ThreadContext::cpuId
virtual int cpuId() const =0
ArmISA::NumVecPredRegs
const int NumVecPredRegs
Definition: registers.hh:98
ThreadContext::contextId
virtual ContextID contextId() const =0
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:832
ArmISA::NumFloatRegs
const int NumFloatRegs
Definition: registers.hh:83
ThreadContext::readFloatRegFlat
virtual RegVal readFloatRegFlat(RegIndex idx) const =0
VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:59
vec_pred_reg.hh
ThreadContext::status
virtual Status status() const =0
ArmISA::NumIntRegs
const int NumIntRegs
Definition: registers.hh:82
arrayParamOut
void arrayParamOut(CheckpointOut &cp, const std::string &name, const CircleBuf< T > &param)
Definition: circlebuf.hh:174
ThreadContext::setStatus
virtual void setStatus(Status new_status)=0
ThreadContext::quiesceTick
void quiesceTick(Tick resume)
Quiesce, suspend, and schedule activate at resume.
Definition: thread_context.cc:136
full_system.hh
ThreadContext::pcState
virtual TheISA::PCState pcState() const =0
ThreadContext::readCCReg
virtual RegVal readCCReg(RegIndex reg_idx) const =0
System::threads
Threads threads
Definition: system.hh:309
VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:56
ThreadContext::compare
static void compare(ThreadContext *one, ThreadContext *two)
function to compare two thread contexts (for debugging)
Definition: thread_context.cc:55
ArmISA::NumCCRegs
const int NumCCRegs
Definition: registers.hh:84
ThreadContext::setCCRegFlat
virtual void setCCRegFlat(RegIndex idx, RegVal val)=0
base.hh
UNSERIALIZE_ARRAY
#define UNSERIALIZE_ARRAY(member, size)
Definition: serialize.hh:840
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
SERIALIZE_CONTAINER
#define SERIALIZE_CONTAINER(member)
Definition: serialize.hh:848
logging.hh
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
ArmISA::t1
Bitfield< 1 > t1
Definition: miscregs_types.hh:229
arrayParamIn
void arrayParamIn(CheckpointIn &cp, const std::string &name, CircleBuf< T > &param)
Definition: circlebuf.hh:184
trace.hh
takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:226
ThreadContext::copyArchRegs
virtual void copyArchRegs(ThreadContext *tc)=0
ArmISA::NumVecRegs
const int NumVecRegs
Definition: registers.hh:97
ThreadContext::setThreadId
virtual void setThreadId(int id)=0
ThreadContext::setVecRegFlat
virtual void setVecRegFlat(RegIndex idx, const VecRegContainer &val)=0
ThreadContext::readIntReg
virtual RegVal readIntReg(RegIndex reg_idx) const =0
CheckpointIn
Definition: serialize.hh:67
ArmISA::NumMiscRegs
const int NumMiscRegs
Definition: registers.hh:85
thread_context.hh
RegVal
uint64_t RegVal
Definition: types.hh:168
ThreadContext::getSystemPtr
virtual System * getSystemPtr()=0
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171

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