gem5  v20.1.0.0
i8254xGBe.hh
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1 /*
2  * Copyright (c) 2006 The Regents of The University of Michigan
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are
7  * met: redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer;
9  * redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution;
12  * neither the name of the copyright holders nor the names of its
13  * contributors may be used to endorse or promote products derived from
14  * this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 /* @file
30  * Device model for Intel's 8254x line of gigabit ethernet controllers.
31  */
32 
33 #ifndef __DEV_NET_I8254XGBE_HH__
34 #define __DEV_NET_I8254XGBE_HH__
35 
36 #include <deque>
37 #include <string>
38 
39 #include "base/inet.hh"
40 #include "debug/EthernetDesc.hh"
41 #include "debug/EthernetIntr.hh"
42 #include "dev/net/etherdevice.hh"
43 #include "dev/net/etherint.hh"
44 #include "dev/net/etherpkt.hh"
46 #include "dev/net/pktfifo.hh"
47 #include "dev/pci/device.hh"
48 #include "params/IGbE.hh"
49 #include "sim/eventq.hh"
50 
51 class IGbEInt;
52 
53 class IGbE : public EtherDevice
54 {
55  private:
57 
58  // device registers
60 
61  // eeprom data, status and control bits
63  uint8_t eeOpcode, eeAddr;
65 
66  // packet fifos
69 
70  // Packet that we are currently putting into the txFifo
72 
73  // Should to Rx/Tx State machine tick?
74  bool inTick;
75  bool rxTick;
76  bool txTick;
77  bool txFifoTick;
78 
80 
81  // Number of bytes copied from current RX packet
82  unsigned pktOffset;
83 
84  // Delays in managaging descriptors
88 
89  // Event and function to deal with RDTR timer expiring
90  void rdtrProcess() {
92  DPRINTF(EthernetIntr,
93  "Posting RXT interrupt because RDTR timer expired\n");
95  }
96 
98 
99  // Event and function to deal with RADV timer expiring
100  void radvProcess() {
102  DPRINTF(EthernetIntr,
103  "Posting RXT interrupt because RADV timer expired\n");
105  }
106 
108 
109  // Event and function to deal with TADV timer expiring
110  void tadvProcess() {
112  DPRINTF(EthernetIntr,
113  "Posting TXDW interrupt because TADV timer expired\n");
115  }
116 
118 
119  // Event and function to deal with TIDV timer expiring
120  void tidvProcess() {
122  DPRINTF(EthernetIntr,
123  "Posting TXDW interrupt because TIDV timer expired\n");
125  }
127 
128  // Main event to tick the device
129  void tick();
131 
132 
133  uint64_t macAddr;
134 
135  void rxStateMachine();
136  void txStateMachine();
137  void txWire();
138 
144  void postInterrupt(iGbReg::IntTypes t, bool now = false);
145 
149  void chkInterrupt();
150 
153  void delayIntEvent();
154  void cpuPostInt();
155  // Event to moderate interrupts
157 
160  void cpuClearInt();
161 
162  Tick intClock() { return SimClock::Int::ns * 1024; }
163 
166  void restartClock();
167 
171  void checkDrain();
172 
173  template<class T>
174  class DescCache : public Serializable
175  {
176  protected:
177  virtual Addr descBase() const = 0;
178  virtual long descHead() const = 0;
179  virtual long descTail() const = 0;
180  virtual long descLen() const = 0;
181  virtual void updateHead(long h) = 0;
182  virtual void enableSm() = 0;
183  virtual void actionAfterWb() {}
184  virtual void fetchAfterWb() = 0;
185 
189 
191  T *wbBuf;
192 
193  // Pointer to the device we cache for
195 
196  // Name of this descriptor cache
197  std::string _name;
198 
199  // How far we've cached
200  int cachePnt;
201 
202  // The size of the descriptor cache
203  int size;
204 
205  // How many descriptors we are currently fetching
207 
208  // How many descriptors we are currently writing back
209  int wbOut;
210 
211  // if the we wrote back to the end of the descriptor ring and are going
212  // to have to wrap and write more
213  bool moreToWb;
214 
215  // What the alignment is of the next descriptor writeback
217 
220 
222  Addr pciToDma(Addr a) { return igbe->pciToDma(a); }
223 
224  public:
228 
229  DescCache(IGbE *i, const std::string n, int s);
230  virtual ~DescCache();
231 
232  std::string name() { return _name; }
233 
238  void areaChanged();
239 
240  void writeback(Addr aMask);
241  void writeback1();
243 
247  void fetchDescriptors();
248  void fetchDescriptors1();
250 
253  void fetchComplete();
255 
258  void wbComplete();
260 
261  /* Return the number of descriptors left in the ring, so the device has
262  * a way to figure out if it needs to interrupt.
263  */
264  unsigned
265  descLeft() const
266  {
267  unsigned left = unusedCache.size();
268  if (cachePnt > descTail())
269  left += (descLen() - cachePnt + descTail());
270  else
271  left += (descTail() - cachePnt);
272 
273  return left;
274  }
275 
276  /* Return the number of descriptors used and not written back.
277  */
278  unsigned descUsed() const { return usedCache.size(); }
279 
280  /* Return the number of cache unused descriptors we have. */
281  unsigned descUnused() const { return unusedCache.size(); }
282 
283  /* Get into a state where the descriptor address/head/etc colud be
284  * changed */
285  void reset();
286 
287 
288  void serialize(CheckpointOut &cp) const override;
289  void unserialize(CheckpointIn &cp) override;
290 
291  virtual bool hasOutstandingEvents() {
292  return wbEvent.scheduled() || fetchEvent.scheduled();
293  }
294 
295  };
296 
297 
298  class RxDescCache : public DescCache<iGbReg::RxDesc>
299  {
300  protected:
301  Addr descBase() const override { return igbe->regs.rdba(); }
302  long descHead() const override { return igbe->regs.rdh(); }
303  long descLen() const override { return igbe->regs.rdlen() >> 4; }
304  long descTail() const override { return igbe->regs.rdt(); }
305  void updateHead(long h) override { igbe->regs.rdh(h); }
306  void enableSm() override;
307  void fetchAfterWb() override {
310  }
311 
312  bool pktDone;
313 
316 
319  unsigned bytesCopied;
320 
321  public:
322  RxDescCache(IGbE *i, std::string n, int s);
323 
331  int writePacket(EthPacketPtr packet, int pkt_offset);
332 
335  void pktComplete();
336 
340  bool packetDone();
341 
343 
344  // Event to handle issuing header and data write at the same time
345  // and only callking pktComplete() when both are completed
346  void pktSplitDone();
349 
350  bool hasOutstandingEvents() override;
351 
352  void serialize(CheckpointOut &cp) const override;
353  void unserialize(CheckpointIn &cp) override;
354  };
355  friend class RxDescCache;
356 
358 
359  class TxDescCache : public DescCache<iGbReg::TxDesc>
360  {
361  protected:
362  Addr descBase() const override { return igbe->regs.tdba(); }
363  long descHead() const override { return igbe->regs.tdh(); }
364  long descTail() const override { return igbe->regs.tdt(); }
365  long descLen() const override { return igbe->regs.tdlen() >> 4; }
366  void updateHead(long h) override { igbe->regs.tdh(h); }
367  void enableSm() override;
368  void actionAfterWb() override;
369  void fetchAfterWb() override {
372  }
373 
374 
375 
376  bool pktDone;
377  bool isTcp;
382  uint32_t descEnd;
383 
384 
385  // tso variables
386  bool useTso;
395  uint8_t tsoHeader[256];
398  int tsoPkts;
399 
400  public:
401  TxDescCache(IGbE *i, std::string n, int s);
402 
407  unsigned getPacketSize(EthPacketPtr p);
409  void processContextDesc();
410 
414  unsigned
415  descInBlock(unsigned num_desc)
416  {
417  return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
418  }
419 
424  bool packetAvailable();
425 
429  bool packetWaiting() { return pktWaiting; }
430 
437  bool packetMultiDesc() { return pktMultiDesc;}
438 
441  void pktComplete();
443 
444  void headerComplete();
446 
447 
449  DPRINTF(EthernetDesc,
450  "Completion writeback Addr: %#x enabled: %d\n",
451  a, enabled);
454  }
455 
456  bool hasOutstandingEvents() override;
457 
458  void nullCallback() {
459  DPRINTF(EthernetDesc, "Completion writeback complete\n");
460  }
462 
463  void serialize(CheckpointOut &cp) const override;
464  void unserialize(CheckpointIn &cp) override;
465  };
466 
467  friend class TxDescCache;
468 
470 
471  public:
472  typedef IGbEParams Params;
473  const Params *
474  params() const {
475  return dynamic_cast<const Params *>(_params);
476  }
477 
478  IGbE(const Params *params);
479  ~IGbE();
480  void init() override;
481 
482  Port &getPort(const std::string &if_name,
483  PortID idx=InvalidPortID) override;
484 
486 
487  Tick read(PacketPtr pkt) override;
488  Tick write(PacketPtr pkt) override;
489 
490  Tick writeConfig(PacketPtr pkt) override;
491 
492  bool ethRxPkt(EthPacketPtr packet);
493  void ethTxDone();
494 
495  void serialize(CheckpointOut &cp) const override;
496  void unserialize(CheckpointIn &cp) override;
497 
498  DrainState drain() override;
499  void drainResume() override;
500 
501 };
502 
503 class IGbEInt : public EtherInt
504 {
505  private:
507 
508  public:
509  IGbEInt(const std::string &name, IGbE *d)
510  : EtherInt(name), dev(d)
511  { }
512 
513  virtual bool recvPacket(EthPacketPtr pkt) { return dev->ethRxPkt(pkt); }
514  virtual void sendDone() { dev->ethTxDone(); }
515 };
516 
517 #endif //__DEV_NET_I8254XGBE_HH__
IGbE::TxDescCache::completionAddress
Addr completionAddress
Definition: i8254xGBe.hh:380
IGbE::TxDescCache::descLen
long descLen() const override
Definition: i8254xGBe.hh:365
IGbE::DescCache::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:1108
IGbEInt::recvPacket
virtual bool recvPacket(EthPacketPtr pkt)
Definition: i8254xGBe.hh:513
IGbE::TxDescCache::descTail
long descTail() const override
Definition: i8254xGBe.hh:364
IGbE::txFifoTick
bool txFifoTick
Definition: i8254xGBe.hh:77
IGbE::DescCache::wbAlignment
Addr wbAlignment
Definition: i8254xGBe.hh:216
Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:460
IGbE::TxDescCache::isTcp
bool isTcp
Definition: i8254xGBe.hh:377
IGbE::DescCache::fetchDescriptors
void fetchDescriptors()
Fetch a chunk of descriptors into the descriptor cache.
Definition: i8254xGBe.cc:926
IGbEInt::IGbEInt
IGbEInt(const std::string &name, IGbE *d)
Definition: i8254xGBe.hh:509
IGbE::DescCache::moreToWb
bool moreToWb
Definition: i8254xGBe.hh:213
SimClock::Int::ns
Tick ns
nanosecond
Definition: core.cc:65
IGbE::DescCache::descLen
virtual long descLen() const =0
IGbE::DescCache::name
std::string name()
Definition: i8254xGBe.hh:232
IGbE::postInterrupt
void postInterrupt(iGbReg::IntTypes t, bool now=false)
Write an interrupt into the interrupt pending register and check mask and interrupt limit timer befor...
Definition: i8254xGBe.cc:692
IGbE::DescCache::annSmFetch
std::string annSmFetch
Annotate sm.
Definition: i8254xGBe.hh:226
IGbE::fetchDelay
Tick fetchDelay
Definition: i8254xGBe.hh:85
PacketFifo
Definition: pktfifo.hh:76
iGbReg::Regs
Definition: i8254xGBe_defs.hh:297
IGbE::txFifo
PacketFifo txFifo
Definition: i8254xGBe.hh:68
DrainState::Running
@ Running
Running normally.
IGbE::txReadDelay
Tick txReadDelay
Definition: i8254xGBe.hh:87
IGbE::DescCache::fetchComplete
void fetchComplete()
Called by event when dma to read descriptors is completed.
Definition: i8254xGBe.cc:985
IGbE::write
Tick write(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8254xGBe.cc:355
IGbE::DescCache::pktPtr
EthPacketPtr pktPtr
The packet that is currently being dmad to memory if any.
Definition: i8254xGBe.hh:219
IGbE::DescCache::size
int size
Definition: i8254xGBe.hh:203
InvalidPortID
const PortID InvalidPortID
Definition: types.hh:238
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
IGbE::RxDescCache
Definition: i8254xGBe.hh:298
IGbE::DescCache::wbOut
int wbOut
Definition: i8254xGBe.hh:209
IGbE::Params
IGbEParams Params
Definition: i8254xGBe.hh:472
IGbE::DescCache::actionAfterWb
virtual void actionAfterWb()
Definition: i8254xGBe.hh:183
IGbE::TxDescCache::actionAfterWb
void actionAfterWb() override
Definition: i8254xGBe.cc:1901
IGbE::txTick
bool txTick
Definition: i8254xGBe.hh:76
IGbE::TxDescCache::tsoHeaderLen
Addr tsoHeaderLen
Definition: i8254xGBe.hh:387
IGbE::TxDescCache::tsoCopyBytes
Addr tsoCopyBytes
Definition: i8254xGBe.hh:397
IGbE::TxDescCache::headerEvent
EventFunctionWrapper headerEvent
Definition: i8254xGBe.hh:445
EtherInt
Definition: etherint.hh:47
Serializable
Basic support for object serialization.
Definition: serialize.hh:172
IGbE::TxDescCache::tsoLoadedHeader
bool tsoLoadedHeader
Definition: i8254xGBe.hh:393
IGbE::DescCache::wbEvent
EventFunctionWrapper wbEvent
Definition: i8254xGBe.hh:259
IGbE::TxDescCache::packetAvailable
bool packetAvailable()
Ask if the packet has been transfered so the state machine can give it to the fifo.
Definition: i8254xGBe.cc:1975
IGbE::TxDescCache::tsoPkts
int tsoPkts
Definition: i8254xGBe.hh:398
iGbReg::Regs::tdlen
TDLEN tdlen
Definition: i8254xGBe_defs.hh:620
IGbE::TxDescCache::tsoTotalLen
Addr tsoTotalLen
Definition: i8254xGBe.hh:389
IGbE::tick
void tick()
Definition: i8254xGBe.cc:2318
IGbE::TxDescCache::packetWaiting
bool packetWaiting()
Ask if we are still waiting for the packet to be transfered.
Definition: i8254xGBe.hh:429
IGbE::ethRxPkt
bool ethRxPkt(EthPacketPtr packet)
Definition: i8254xGBe.cc:2154
IGbE::regs
iGbReg::Regs regs
Definition: i8254xGBe.hh:59
etherint.hh
IGbE::DescCache::fetchDescriptors1
void fetchDescriptors1()
Definition: i8254xGBe.cc:965
IGbE::ethTxDone
void ethTxDone()
Definition: i8254xGBe.cc:2346
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
IGbE::TxDescCache::nullEvent
EventFunctionWrapper nullEvent
Definition: i8254xGBe.hh:461
IGbE::IGbE
IGbE(const Params *params)
Definition: i8254xGBe.cc:58
IGbE::lastInterrupt
Tick lastInterrupt
Definition: i8254xGBe.hh:485
PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:237
IGbE::DescCache::wbBuf
T * wbBuf
Definition: i8254xGBe.hh:191
IGbE::RxDescCache::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:1486
IGbE::TxDescCache::completionEnabled
bool completionEnabled
Definition: i8254xGBe.hh:381
IGbE::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:2412
IGbE::DescCache::annUnusedDescQ
std::string annUnusedDescQ
Definition: i8254xGBe.hh:226
IGbE::DescCache::descUnused
unsigned descUnused() const
Definition: i8254xGBe.hh:281
IGbEInt
Definition: i8254xGBe.hh:503
IGbE::rdtrEvent
EventFunctionWrapper rdtrEvent
Definition: i8254xGBe.hh:97
DmaDevice::cacheBlockSize
unsigned int cacheBlockSize() const
Definition: dma_device.hh:205
IGbE::RxDescCache::pktDataEvent
EventFunctionWrapper pktDataEvent
Definition: i8254xGBe.hh:348
IGbE::TxDescCache::completionWriteback
void completionWriteback(Addr a, bool enabled)
Definition: i8254xGBe.hh:448
IGbE::RxDescCache::hasOutstandingEvents
bool hasOutstandingEvents() override
Definition: i8254xGBe.cc:1468
iGbReg::IT_TXDW
@ IT_TXDW
Definition: i8254xGBe_defs.hh:172
IGbE::RxDescCache::pktDone
bool pktDone
Definition: i8254xGBe.hh:312
IGbE::drain
DrainState drain() override
Draining is the process of clearing out the states of SimObjects.These are the SimObjects that are pa...
Definition: i8254xGBe.cc:2012
IGbE::RxDescCache::descLen
long descLen() const override
Definition: i8254xGBe.hh:303
IGbE::params
const Params * params() const
Definition: i8254xGBe.hh:474
IGbE::tidvEvent
EventFunctionWrapper tidvEvent
Definition: i8254xGBe.hh:126
IGbE::inTick
bool inTick
Definition: i8254xGBe.hh:74
IGbE::eeDataBits
int eeDataBits
Definition: i8254xGBe.hh:62
IGbE::init
void init() override
init() is called after all C++ SimObjects have been created and all ports are connected.
Definition: i8254xGBe.cc:134
IGbE::DescCache::fetchDelayEvent
EventFunctionWrapper fetchDelayEvent
Definition: i8254xGBe.hh:249
iGbReg::Regs::rdt
RDT rdt
Definition: i8254xGBe_defs.hh:577
IGbE::eeAddrBits
int eeAddrBits
Definition: i8254xGBe.hh:62
device.hh
IGbE::DescCache::descHead
virtual long descHead() const =0
IGbE::TxDescCache
Definition: i8254xGBe.hh:359
IGbE::rxDescCache
RxDescCache rxDescCache
Definition: i8254xGBe.hh:357
IGbE::read
Tick read(PacketPtr pkt) override
Pure virtual function that the device must implement.
Definition: i8254xGBe.cc:167
IGbE::RxDescCache::RxDescCache
RxDescCache(IGbE *i, std::string n, int s)
Definition: i8254xGBe.cc:1147
IGbE::TxDescCache::descBase
Addr descBase() const override
Definition: i8254xGBe.hh:362
iGbReg::IntTypes
IntTypes
Definition: i8254xGBe_defs.hh:169
IGbE::TxDescCache::pktWaiting
bool pktWaiting
Definition: i8254xGBe.hh:378
EventFunctionWrapper
Definition: eventq.hh:1101
IGbE::TxDescCache::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe.cc:1917
IGbE::TxDescCache::enableSm
void enableSm() override
Definition: i8254xGBe.cc:1985
IGbE::cpuClearInt
void cpuClearInt()
Clear the interupt line to the cpu.
Definition: i8254xGBe.cc:776
IGbE::DescCache::descLeft
unsigned descLeft() const
Definition: i8254xGBe.hh:265
IGbE::TxDescCache::fetchAfterWb
void fetchAfterWb() override
Definition: i8254xGBe.hh:369
DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:71
ArmISA::n
Bitfield< 31 > n
Definition: miscregs_types.hh:450
IGbE::DescCache::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe.cc:1073
IGbE::fetchCompDelay
Tick fetchCompDelay
Definition: i8254xGBe.hh:86
IGbE::DescCache::pciToDma
Addr pciToDma(Addr a)
Shortcut for DMA address translation.
Definition: i8254xGBe.hh:222
IGbE::txDescCache
TxDescCache txDescCache
Definition: i8254xGBe.hh:469
IGbE::TxDescCache::getPacketData
void getPacketData(EthPacketPtr p)
Definition: i8254xGBe.cc:1658
IGbE::TxDescCache::hasOutstandingEvents
bool hasOutstandingEvents() override
Definition: i8254xGBe.cc:1994
IGbE::DescCache::igbe
IGbE * igbe
Definition: i8254xGBe.hh:194
iGbReg::Regs::rdba
RDBA rdba
Definition: i8254xGBe_defs.hh:548
IGbE::RxDescCache::bytesCopied
unsigned bytesCopied
Bytes of packet that have been copied, so we know when to set EOP.
Definition: i8254xGBe.hh:319
IGbE::radvProcess
void radvProcess()
Definition: i8254xGBe.hh:100
IGbE::cpuPostInt
void cpuPostInt()
Definition: i8254xGBe.cc:732
cp
Definition: cprintf.cc:40
IGbE::intClock
Tick intClock()
Definition: i8254xGBe.hh:162
IGbE::rdtrProcess
void rdtrProcess()
Definition: i8254xGBe.hh:90
IGbE::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe.cc:2361
Stats::enabled
bool enabled()
Definition: statistics.cc:545
IGbE::TxDescCache::pktComplete
void pktComplete()
Called by event when dma to write packet is completed.
Definition: i8254xGBe.cc:1706
ArmISA::a
Bitfield< 8 > a
Definition: miscregs_types.hh:62
IGbE::DescCache::annUsedDescQ
std::string annUsedDescQ
Definition: i8254xGBe.hh:227
IGbE::RxDescCache::pktSplitDone
void pktSplitDone()
Definition: i8254xGBe.cc:1164
IGbE::TxDescCache::updateHead
void updateHead(long h) override
Definition: i8254xGBe.hh:366
IGbE::txStateMachine
void txStateMachine()
Definition: i8254xGBe.cc:2064
IGbE::tadvEvent
EventFunctionWrapper tadvEvent
Definition: i8254xGBe.hh:117
IGbE::writeConfig
Tick writeConfig(PacketPtr pkt) override
Write to the PCI config space data that is stored locally.
Definition: i8254xGBe.cc:148
IGbE::TxDescCache::useTso
bool useTso
Definition: i8254xGBe.hh:386
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:234
IGbE::flash
uint16_t flash[iGbReg::EEPROM_SIZE]
Definition: i8254xGBe.hh:64
iGbReg::Regs::rdh
RDH rdh
Definition: i8254xGBe_defs.hh:571
IGbE::txPacket
EthPacketPtr txPacket
Definition: i8254xGBe.hh:71
ArmISA::d
Bitfield< 9 > d
Definition: miscregs_types.hh:60
IGbE::DescCache::enableSm
virtual void enableSm()=0
IGbE::RxDescCache::descHead
long descHead() const override
Definition: i8254xGBe.hh:302
IGbE::DescCache::descBase
virtual Addr descBase() const =0
iGbReg::Regs::tdt
TDT tdt
Definition: i8254xGBe_defs.hh:640
Port
Ports are used to interface objects to each other.
Definition: port.hh:56
IGbE::RxDescCache::pktHdrEvent
EventFunctionWrapper pktHdrEvent
Definition: i8254xGBe.hh:347
IGbE::DescCache::unusedCache
CacheType unusedCache
Definition: i8254xGBe.hh:188
IGbEInt::sendDone
virtual void sendDone()
Definition: i8254xGBe.hh:514
IGbE::DescCache::DescCache
DescCache(IGbE *i, const std::string n, int s)
Definition: i8254xGBe.cc:822
IGbE::rxTick
bool rxTick
Definition: i8254xGBe.hh:75
IGbE::DescCache::wbComplete
void wbComplete()
Called by event when dma to writeback descriptors is completed.
Definition: i8254xGBe.cc:1015
IGbE::DescCache::writeback
void writeback(Addr aMask)
Definition: i8254xGBe.cc:854
IGbE::TxDescCache::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: i8254xGBe.cc:1946
IGbE::DescCache::descTail
virtual long descTail() const =0
IGbE
Definition: i8254xGBe.hh:53
IGbE::DescCache::wbDelayEvent
EventFunctionWrapper wbDelayEvent
Definition: i8254xGBe.hh:242
IGbE::RxDescCache::updateHead
void updateHead(long h) override
Definition: i8254xGBe.hh:305
IGbE::TxDescCache::descInBlock
unsigned descInBlock(unsigned num_desc)
Return the number of dsecriptors in a cache block for threshold operations.
Definition: i8254xGBe.hh:415
IGbEInt::dev
IGbE * dev
Definition: i8254xGBe.hh:506
IGbE::TxDescCache::pktMultiDesc
bool pktMultiDesc
Definition: i8254xGBe.hh:379
IGbE::RxDescCache::descTail
long descTail() const override
Definition: i8254xGBe.hh:304
iGbReg::IT_RXT
@ IT_RXT
Definition: i8254xGBe_defs.hh:178
IGbE::RxDescCache::packetDone
bool packetDone()
Check if the dma on the packet has completed and RX state machine can continue.
Definition: i8254xGBe.cc:1458
IGbE::DescCache
Definition: i8254xGBe.hh:174
IGbE::DescCache::annUsedCacheQ
std::string annUsedCacheQ
Definition: i8254xGBe.hh:226
IGbE::etherInt
IGbEInt * etherInt
Definition: i8254xGBe.hh:56
IGbE::rxStateMachine
void rxStateMachine()
Definition: i8254xGBe.cc:2186
IGbE::macAddr
uint64_t macAddr
Definition: i8254xGBe.hh:133
Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:142
IGbE::tidvProcess
void tidvProcess()
Definition: i8254xGBe.hh:120
IGbE::DescCache::fetchBuf
T * fetchBuf
Definition: i8254xGBe.hh:190
IGbE::TxDescCache::TxDescCache
TxDescCache(IGbE *i, std::string n, int s)
Definition: i8254xGBe.cc:1497
IGbE::RxDescCache::writePacket
int writePacket(EthPacketPtr packet, int pkt_offset)
Write the given packet into the buffer(s) pointed to by the descriptor and update the book keeping.
Definition: i8254xGBe.cc:1179
IGbE::interEvent
EventFunctionWrapper interEvent
Definition: i8254xGBe.hh:156
IGbE::TxDescCache::descEnd
uint32_t descEnd
Definition: i8254xGBe.hh:382
Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:320
IGbE::DescCache::cachePnt
int cachePnt
Definition: i8254xGBe.hh:200
IGbE::RxDescCache::pktEvent
EventFunctionWrapper pktEvent
Definition: i8254xGBe.hh:342
IGbE::TxDescCache::nullCallback
void nullCallback()
Definition: i8254xGBe.hh:458
iGbReg::Regs::tdba
TDBA tdba
Definition: i8254xGBe_defs.hh:614
IGbE::DescCache::descUsed
unsigned descUsed() const
Definition: i8254xGBe.hh:278
IGbE::TxDescCache::tsoPktHasHeader
bool tsoPktHasHeader
Definition: i8254xGBe.hh:394
IGbE::DescCache::_name
std::string _name
Definition: i8254xGBe.hh:197
EthPacketPtr
std::shared_ptr< EthPacketData > EthPacketPtr
Definition: etherpkt.hh:87
IGbE::pktOffset
unsigned pktOffset
Definition: i8254xGBe.hh:82
IGbE::rxFifo
PacketFifo rxFifo
Definition: i8254xGBe.hh:67
IGbE::tickEvent
EventFunctionWrapper tickEvent
Definition: i8254xGBe.hh:130
EtherInt::name
const std::string & name() const
Return port name (for DPRINTF).
Definition: etherint.hh:59
IGbE::TxDescCache::tsoMss
Addr tsoMss
Definition: i8254xGBe.hh:388
IGbE::RxDescCache::enableSm
void enableSm() override
Definition: i8254xGBe.cc:1449
IGbE::RxDescCache::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: i8254xGBe.cc:1477
iGbReg::TxDesc
Definition: i8254xGBe_defs.hh:224
ArmISA::t
Bitfield< 5 > t
Definition: miscregs_types.hh:67
IGbE::DescCache::annDescQ
std::string annDescQ
Definition: i8254xGBe.hh:227
SimObject::_params
const SimObjectParams * _params
Cached copy of the object parameters.
Definition: sim_object.hh:110
IGbE::DescCache::usedCache
CacheType usedCache
Definition: i8254xGBe.hh:187
EtherDevice
Definition: etherdevice.hh:45
IGbE::drainResume
void drainResume() override
Resume execution after a successful drain.
Definition: i8254xGBe.cc:2035
IGbE::DescCache::writeback1
void writeback1()
Definition: i8254xGBe.cc:902
IGbE::eeAddr
uint8_t eeAddr
Definition: i8254xGBe.hh:63
IGbE::DescCache::annUnusedCacheQ
std::string annUnusedCacheQ
Definition: i8254xGBe.hh:227
IGbE::TxDescCache::tsoPrevSeq
Addr tsoPrevSeq
Definition: i8254xGBe.hh:391
IGbE::DescCache::~DescCache
virtual ~DescCache()
Definition: i8254xGBe.cc:835
IGbE::DescCache::areaChanged
void areaChanged()
If the address/len/head change when we've got descriptors that are dirty that is very bad.
Definition: i8254xGBe.cc:844
IGbE::chkInterrupt
void chkInterrupt()
Check and see if changes to the mask register have caused an interrupt to need to be sent or perhaps ...
Definition: i8254xGBe.cc:788
IGbE::getPort
Port & getPort(const std::string &if_name, PortID idx=InvalidPortID) override
Get a port with a given name and index.
Definition: i8254xGBe.cc:140
IGbE::rxWriteDelay
Tick rxWriteDelay
Definition: i8254xGBe.hh:87
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
std::deque< T * >
IGbE::DescCache::hasOutstandingEvents
virtual bool hasOutstandingEvents()
Definition: i8254xGBe.hh:291
IGbE::restartClock
void restartClock()
This function is used to restart the clock so it can handle things like draining and resume in one pl...
Definition: i8254xGBe.cc:2004
IGbE::eeOpBits
int eeOpBits
Definition: i8254xGBe.hh:62
IGbE::DescCache::fetchEvent
EventFunctionWrapper fetchEvent
Definition: i8254xGBe.hh:254
IGbE::DescCache::reset
void reset()
Definition: i8254xGBe.cc:1056
IGbE::wbDelay
Tick wbDelay
Definition: i8254xGBe.hh:85
IGbE::DescCache::updateHead
virtual void updateHead(long h)=0
IGbE::TxDescCache::getPacketSize
unsigned getPacketSize(EthPacketPtr p)
Tell the cache to DMA a packet from main memory into its buffer and return the size the of the packet...
Definition: i8254xGBe.cc:1618
IGbE::TxDescCache::headerComplete
void headerComplete()
Definition: i8254xGBe.cc:1593
IGbE::radvEvent
EventFunctionWrapper radvEvent
Definition: i8254xGBe.hh:107
pktfifo.hh
IGbE::TxDescCache::tsoDescBytesUsed
Addr tsoDescBytesUsed
Definition: i8254xGBe.hh:396
etherpkt.hh
IGbE::DescCache::curFetching
int curFetching
Definition: i8254xGBe.hh:206
CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:63
etherdevice.hh
IGbE::TxDescCache::pktDone
bool pktDone
Definition: i8254xGBe.hh:376
IGbE::RxDescCache::descBase
Addr descBase() const override
Definition: i8254xGBe.hh:301
IGbE::eeOpcode
uint8_t eeOpcode
Definition: i8254xGBe.hh:63
IGbE::TxDescCache::pktEvent
EventFunctionWrapper pktEvent
Definition: i8254xGBe.hh:442
IGbE::RxDescCache::splitCount
int splitCount
Variable to head with header/data completion events.
Definition: i8254xGBe.hh:315
IGbE::DescCache::annSmWb
std::string annSmWb
Definition: i8254xGBe.hh:226
IGbE::checkDrain
void checkDrain()
Check if all the draining things that need to occur have occured and handle the drain event if so.
Definition: i8254xGBe.cc:2048
MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:323
ArmISA::s
Bitfield< 4 > s
Definition: miscregs_types.hh:556
inet.hh
IGbE::TxDescCache::tsoPktPayloadBytes
Addr tsoPktPayloadBytes
Definition: i8254xGBe.hh:392
CheckpointIn
Definition: serialize.hh:67
IGbE::TxDescCache::tsoHeader
uint8_t tsoHeader[256]
Definition: i8254xGBe.hh:395
IGbE::~IGbE
~IGbE()
Definition: i8254xGBe.cc:128
IGbE::RxDescCache::fetchAfterWb
void fetchAfterWb() override
Definition: i8254xGBe.hh:307
IGbE::delayIntEvent
void delayIntEvent()
Send an interrupt to the cpu.
Definition: i8254xGBe.cc:725
IGbE::TxDescCache::processContextDesc
void processContextDesc()
Definition: i8254xGBe.cc:1518
IGbE::DescCache::fetchAfterWb
virtual void fetchAfterWb()=0
IGbE::TxDescCache::descHead
long descHead() const override
Definition: i8254xGBe.hh:363
IGbE::TxDescCache::tsoUsedLen
Addr tsoUsedLen
Definition: i8254xGBe.hh:390
IGbE::tadvProcess
void tadvProcess()
Definition: i8254xGBe.hh:110
IGbE::RxDescCache::pktComplete
void pktComplete()
Called by event when dma to write packet is completed.
Definition: i8254xGBe.cc:1287
iGbReg::Regs::rdlen
RDLEN rdlen
Definition: i8254xGBe_defs.hh:554
IGbE::wbCompDelay
Tick wbCompDelay
Definition: i8254xGBe.hh:86
DmaDevice::Params
DmaDeviceParams Params
Definition: dma_device.hh:171
IGbE::DescCache::CacheType
std::deque< T * > CacheType
Definition: i8254xGBe.hh:186
PciDevice::pciToDma
Addr pciToDma(Addr pci_addr) const
Definition: device.hh:194
IGbE::rxDmaPacket
bool rxDmaPacket
Definition: i8254xGBe.hh:79
IGbE::TxDescCache::packetMultiDesc
bool packetMultiDesc()
Ask if this packet is composed of multiple descriptors so even if we've got data, we need to wait for...
Definition: i8254xGBe.hh:437
IGbE::txWire
void txWire()
Definition: i8254xGBe.cc:2289
i8254xGBe_defs.hh
iGbReg::Regs::tdh
TDH tdh
Definition: i8254xGBe_defs.hh:626
iGbReg::EEPROM_SIZE
const uint8_t EEPROM_SIZE
Definition: i8254xGBe_defs.hh:104
eventq.hh

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