impl.hh

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/*
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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 */
 
#ifndef __CPU_O3_IMPL_HH__
#define __CPU_O3_IMPL_HH__
 
#include "config/the_isa.hh"
#include "cpu/o3/cpu_policy.hh"
 
// Forward declarations.
template <class Impl>
class BaseO3DynInst;
 
template <class Impl>
class FullO3CPU;
 
struct O3CPUImpl
{
    typedef TheISA::MachInst MachInst;
 
    typedef SimpleCPUPolicy<O3CPUImpl> CPUPol;
 
    typedef BaseO3DynInst<O3CPUImpl> DynInst;
 
    typedef RefCountingPtr<DynInst> DynInstPtr;
    typedef RefCountingPtr<const DynInst> DynInstConstPtr;
 
    typedef FullO3CPU<O3CPUImpl> O3CPU;
 
    typedef O3CPU CPUType;
 
    enum {
      MaxWidth = 8,
      MaxThreads = 4
    };
};
 
#endif // __CPU_O3_SPARC_IMPL_HH__