gem5  v20.1.0.0
dyn_inst.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2010, 2016 ARM Limited
3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
4  * All rights reserved
5  *
6  * The license below extends only to copyright in the software and shall
7  * not be construed as granting a license to any other intellectual
8  * property including but not limited to intellectual property relating
9  * to a hardware implementation of the functionality of the software
10  * licensed hereunder. You may use the software subject to the license
11  * terms below provided that you ensure that this notice is replicated
12  * unmodified and in its entirety in all distributions of the software,
13  * modified or unmodified, in source code or in binary form.
14  *
15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
16  * All rights reserved.
17  *
18  * Redistribution and use in source and binary forms, with or without
19  * modification, are permitted provided that the following conditions are
20  * met: redistributions of source code must retain the above copyright
21  * notice, this list of conditions and the following disclaimer;
22  * redistributions in binary form must reproduce the above copyright
23  * notice, this list of conditions and the following disclaimer in the
24  * documentation and/or other materials provided with the distribution;
25  * neither the name of the copyright holders nor the names of its
26  * contributors may be used to endorse or promote products derived from
27  * this software without specific prior written permission.
28  *
29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40  */
41 
42 #ifndef __CPU_O3_DYN_INST_HH__
43 #define __CPU_O3_DYN_INST_HH__
44 
45 #include <array>
46 
47 #include "config/the_isa.hh"
48 #include "cpu/o3/cpu.hh"
49 #include "cpu/o3/isa_specific.hh"
50 #include "cpu/base_dyn_inst.hh"
51 #include "cpu/inst_seq.hh"
52 #include "cpu/reg_class.hh"
53 
54 class Packet;
55 
56 template <class Impl>
57 class BaseO3DynInst : public BaseDynInst<Impl>
58 {
59  public:
61  typedef typename Impl::O3CPU O3CPU;
62 
70 
71  enum {
72  MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
73  MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
74  };
75 
76  public:
80  InstSeqNum seq_num, O3CPU *cpu);
81 
83  BaseO3DynInst(const StaticInstPtr &_staticInst,
84  const StaticInstPtr &_macroop);
85 
87 
89  Fault execute();
90 
93 
96 
97  private:
99  void initVars();
100 
101  protected:
106 
108  std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
109 
114  std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
115 
118 
119 
120  public:
121 #if TRACING_ON
122 
123  Tick fetchTick; // instruction fetch is completed.
124  int32_t decodeTick; // instruction enters decode phase
125  int32_t renameTick; // instruction enters rename phase
126  int32_t dispatchTick;
127  int32_t issueTick;
128  int32_t completeTick;
129  int32_t commitTick;
130  int32_t storeTick;
131 #endif
132 
136  RegVal
137  readMiscReg(int misc_reg) override
138  {
139  return this->cpu->readMiscReg(misc_reg, this->threadNumber);
140  }
141 
145  void
146  setMiscReg(int misc_reg, RegVal val) override
147  {
154  for (int idx = 0; idx < _numDestMiscRegs; idx++) {
155  if (_destMiscRegIdx[idx] == misc_reg) {
156  _destMiscRegVal[idx] = val;
157  return;
158  }
159  }
160 
162  _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
165  }
166 
170  RegVal
171  readMiscRegOperand(const StaticInst *si, int idx) override
172  {
173  const RegId& reg = si->srcRegIdx(idx);
174  assert(reg.isMiscReg());
175  return this->cpu->readMiscReg(reg.index(), this->threadNumber);
176  }
177 
181  void
182  setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
183  {
184  const RegId& reg = si->destRegIdx(idx);
185  assert(reg.isMiscReg());
186  setMiscReg(reg.index(), val);
187  }
188 
190  void
192  {
193  // @todo: Pretty convoluted way to avoid squashing from happening when
194  // using the TC during an instruction's execution (specifically for
195  // instructions that have side-effects that use the TC). Fix this.
196  // See cpu/o3/dyn_inst_impl.hh.
197  bool no_squash_from_TC = this->thread->noSquashFromTC;
198  this->thread->noSquashFromTC = true;
199 
200  for (int i = 0; i < _numDestMiscRegs; i++)
201  this->cpu->setMiscReg(
202  _destMiscRegIdx[i], _destMiscRegVal[i], this->threadNumber);
203 
204  this->thread->noSquashFromTC = no_squash_from_TC;
205  }
206 
208  {
209 
210  for (int idx = 0; idx < this->numDestRegs(); idx++) {
211  PhysRegIdPtr prev_phys_reg = this->prevDestRegIdx(idx);
212  const RegId& original_dest_reg =
213  this->staticInst->destRegIdx(idx);
214  switch (original_dest_reg.classValue()) {
215  case IntRegClass:
216  this->setIntRegOperand(this->staticInst.get(), idx,
217  this->cpu->readIntReg(prev_phys_reg));
218  break;
219  case FloatRegClass:
220  this->setFloatRegOperandBits(this->staticInst.get(), idx,
221  this->cpu->readFloatReg(prev_phys_reg));
222  break;
223  case VecRegClass:
224  this->setVecRegOperand(this->staticInst.get(), idx,
225  this->cpu->readVecReg(prev_phys_reg));
226  break;
227  case VecElemClass:
228  this->setVecElemOperand(this->staticInst.get(), idx,
229  this->cpu->readVecElem(prev_phys_reg));
230  break;
231  case VecPredRegClass:
232  this->setVecPredRegOperand(this->staticInst.get(), idx,
233  this->cpu->readVecPredReg(prev_phys_reg));
234  break;
235  case CCRegClass:
236  this->setCCRegOperand(this->staticInst.get(), idx,
237  this->cpu->readCCReg(prev_phys_reg));
238  break;
239  case MiscRegClass:
240  // no need to forward misc reg values
241  break;
242  default:
243  panic("Unknown register class: %d",
244  (int)original_dest_reg.classValue());
245  }
246  }
247  }
249  void trap(const Fault &fault);
250 
252  void syscall() override;
253 
254  public:
255 
256  // The register accessor methods provide the index of the
257  // instruction's operand (e.g., 0 or 1), not the architectural
258  // register index, to simplify the implementation of register
259  // renaming. We find the architectural register index by indexing
260  // into the instruction's own operand index table. Note that a
261  // raw pointer to the StaticInst is provided instead of a
262  // ref-counted StaticInstPtr to redice overhead. This is fine as
263  // long as these methods don't copy the pointer into any long-term
264  // storage (which is pretty hard to imagine they would have reason
265  // to do).
266 
267  RegVal
268  readIntRegOperand(const StaticInst *si, int idx) override
269  {
270  return this->cpu->readIntReg(this->_srcRegIdx[idx]);
271  }
272 
273  RegVal
274  readFloatRegOperandBits(const StaticInst *si, int idx) override
275  {
276  return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
277  }
278 
279  const VecRegContainer&
280  readVecRegOperand(const StaticInst *si, int idx) const override
281  {
282  return this->cpu->readVecReg(this->_srcRegIdx[idx]);
283  }
284 
289  getWritableVecRegOperand(const StaticInst *si, int idx) override
290  {
291  return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
292  }
293 
298  readVec8BitLaneOperand(const StaticInst *si, int idx) const override
299  {
300  return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
301  }
302 
305  readVec16BitLaneOperand(const StaticInst *si, int idx) const override
306  {
307  return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
308  }
309 
312  readVec32BitLaneOperand(const StaticInst *si, int idx) const override
313  {
314  return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
315  }
316 
319  readVec64BitLaneOperand(const StaticInst *si, int idx) const override
320  {
321  return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
322  }
323 
325  template <typename LD>
326  void
327  setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
328  {
329  return cpu->template setVecLane(_destRegIdx[idx], val);
330  }
331  virtual void
332  setVecLaneOperand(const StaticInst *si, int idx,
333  const LaneData<LaneSize::Byte>& val) override
334  {
335  return setVecLaneOperandT(si, idx, val);
336  }
337  virtual void
338  setVecLaneOperand(const StaticInst *si, int idx,
339  const LaneData<LaneSize::TwoByte>& val) override
340  {
341  return setVecLaneOperandT(si, idx, val);
342  }
343  virtual void
344  setVecLaneOperand(const StaticInst *si, int idx,
345  const LaneData<LaneSize::FourByte>& val) override
346  {
347  return setVecLaneOperandT(si, idx, val);
348  }
349  virtual void
350  setVecLaneOperand(const StaticInst *si, int idx,
351  const LaneData<LaneSize::EightByte>& val) override
352  {
353  return setVecLaneOperandT(si, idx, val);
354  }
357  VecElem readVecElemOperand(const StaticInst *si, int idx) const override
358  {
359  return this->cpu->readVecElem(this->_srcRegIdx[idx]);
360  }
361 
362  const VecPredRegContainer&
363  readVecPredRegOperand(const StaticInst *si, int idx) const override
364  {
365  return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
366  }
367 
369  getWritableVecPredRegOperand(const StaticInst *si, int idx) override
370  {
371  return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
372  }
373 
374  RegVal
375  readCCRegOperand(const StaticInst *si, int idx) override
376  {
377  return this->cpu->readCCReg(this->_srcRegIdx[idx]);
378  }
379 
383  void
384  setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
385  {
386  this->cpu->setIntReg(this->_destRegIdx[idx], val);
388  }
389 
390  void
391  setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
392  {
393  this->cpu->setFloatReg(this->_destRegIdx[idx], val);
395  }
396 
397  void
398  setVecRegOperand(const StaticInst *si, int idx,
399  const VecRegContainer& val) override
400  {
401  this->cpu->setVecReg(this->_destRegIdx[idx], val);
403  }
404 
405  void setVecElemOperand(const StaticInst *si, int idx,
406  const VecElem val) override
407  {
408  int reg_idx = idx;
409  this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
411  }
412 
413  void
415  const VecPredRegContainer& val) override
416  {
417  this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
419  }
420 
421  void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
422  {
423  this->cpu->setCCReg(this->_destRegIdx[idx], val);
425  }
426 };
427 
428 #endif // __CPU_O3_ALPHA_DYN_INST_HH__
429 
BaseDynInst::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Records a CC register being set to a value.
Definition: base_dyn_inst.hh:765
BaseDynInst::predPC
TheISA::PCState predPC
Predicted PC state after this instruction.
Definition: base_dyn_inst.hh:200
BaseO3DynInst::setMiscReg
void setMiscReg(int misc_reg, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:146
BaseO3DynInst::readVec16BitLaneOperand
ConstVecLane16 readVec16BitLaneOperand(const StaticInst *si, int idx) const override
Reads source vector 16bit operand.
Definition: dyn_inst.hh:305
BaseO3DynInst::O3CPU
Impl::O3CPU O3CPU
Typedef for the CPU.
Definition: dyn_inst.hh:61
BaseO3DynInst::initVars
void initVars()
Initializes variables.
Definition: dyn_inst_impl.hh:103
VecPredRegContainer
Generic predicate register container.
Definition: vec_pred_reg.hh:47
StaticInst::destRegIdx
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
Definition: static_inst.hh:230
PowerISA::MaxMiscDestRegs
const int MaxMiscDestRegs
Definition: registers.hh:45
ArmISA::VecRegContainer
VecReg::Container VecRegContainer
Definition: registers.hh:71
VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:58
BaseO3DynInst::getWritableVecPredRegOperand
VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
Definition: dyn_inst.hh:369
BaseDynInst::thread
ImplState * thread
Pointer to the thread state.
Definition: base_dyn_inst.hh:161
ArmISA::i
Bitfield< 7 > i
Definition: miscregs_types.hh:63
BaseO3DynInst::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val) override
Record a vector register being set to a value.
Definition: dyn_inst.hh:414
BaseO3DynInst::NumVecElemPerVecReg
static constexpr auto NumVecElemPerVecReg
Definition: dyn_inst.hh:68
StaticInst
Base, ISA-independent static instruction class.
Definition: static_inst.hh:85
BaseDynInst::fault
Fault fault
The kind of fault this instruction has generated.
Definition: base_dyn_inst.hh:164
ArmISA::MachInst
uint32_t MachInst
Definition: types.hh:52
BaseDynInst::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) override
Record a vector register being set to a value.
Definition: base_dyn_inst.hh:787
ArmISA::si
Bitfield< 6 > si
Definition: miscregs_types.hh:766
base_dyn_inst.hh
BaseO3DynInst::MaxInstSrcRegs
@ MaxInstSrcRegs
Definition: dyn_inst.hh:72
BaseO3DynInst
Definition: dyn_inst.hh:57
Tick
uint64_t Tick
Tick count type.
Definition: types.hh:63
ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: registers.hh:77
BaseO3DynInst::setVecLaneOperand
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override
Definition: dyn_inst.hh:350
BaseO3DynInst::setMiscRegOperand
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets a misc.
Definition: dyn_inst.hh:182
BaseO3DynInst::BaseO3DynInst
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu)
BaseDynInst constructor given a binary instruction.
Definition: dyn_inst_impl.hh:48
BaseO3DynInst::readVecElemOperand
VecElem readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
Definition: dyn_inst.hh:357
BaseO3DynInst::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Records an fp register being set to an integer value.
Definition: dyn_inst.hh:391
BaseO3DynInst::readVec32BitLaneOperand
ConstVecLane32 readVec32BitLaneOperand(const StaticInst *si, int idx) const override
Reads source vector 32bit operand.
Definition: dyn_inst.hh:312
X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:87
BaseO3DynInst::updateMiscRegs
void updateMiscRegs()
Called at the commit stage to update the misc.
Definition: dyn_inst.hh:191
BaseDynInst::setVecPredRegOperand
void setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val) override
Record a vector register being set to a value.
Definition: base_dyn_inst.hh:795
ArmISA::MaxInstSrcRegs
const int MaxInstSrcRegs
Definition: registers.hh:57
RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:75
BaseO3DynInst::readIntRegOperand
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
Definition: dyn_inst.hh:268
BaseO3DynInst::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Definition: dyn_inst.hh:384
BaseO3DynInst::readMiscRegOperand
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Reads a misc.
Definition: dyn_inst.hh:171
BaseDynInst::setIntRegOperand
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Records an integer register being set to a value.
Definition: base_dyn_inst.hh:758
BaseO3DynInst::_destMiscRegVal
std::array< RegVal, TheISA::MaxMiscDestRegs > _destMiscRegVal
Values to be written to the destination misc.
Definition: dyn_inst.hh:108
BaseDynInst::_destRegIdx
std::array< PhysRegIdPtr, TheISA::MaxInstDestRegs > _destRegIdx
Physical register index of the destination registers of this instruction.
Definition: base_dyn_inst.hh:259
BaseO3DynInst::readMiscReg
RegVal readMiscReg(int misc_reg) override
Reads a misc.
Definition: dyn_inst.hh:137
BaseO3DynInst::setVecLaneOperand
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override
Definition: dyn_inst.hh:344
ArmISA::VecElem
uint32_t VecElem
Definition: registers.hh:68
BaseO3DynInst::MachInst
TheISA::MachInst MachInst
Binary machine instruction type.
Definition: dyn_inst.hh:64
FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:54
inst_seq.hh
BaseO3DynInst::forwardOldRegs
void forwardOldRegs()
Definition: dyn_inst.hh:207
BaseDynInst::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val) override
Record a vector register being set to a value.
Definition: base_dyn_inst.hh:772
isa_specific.hh
BaseDynInst::_srcRegIdx
std::array< PhysRegIdPtr, TheISA::MaxInstSrcRegs > _srcRegIdx
Physical register index of the source registers of this instruction.
Definition: base_dyn_inst.hh:264
BaseDynInst::pc
TheISA::PCState pc
PC state for this instruction.
Definition: base_dyn_inst.hh:176
VecLaneT
Vector Lane abstraction Another view of a container.
Definition: vec_reg.hh:262
BaseO3DynInst::setVecLaneOperand
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override
Definition: dyn_inst.hh:338
BaseO3DynInst::execute
Fault execute()
Executes the instruction.
Definition: dyn_inst_impl.hh:125
Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:240
BaseO3DynInst::setCCRegOperand
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Records a CC register being set to a value.
Definition: dyn_inst.hh:421
ArmISA::NumVecElemPerVecReg
constexpr unsigned NumVecElemPerVecReg
Definition: registers.hh:66
BaseO3DynInst::~BaseO3DynInst
~BaseO3DynInst()
Definition: dyn_inst_impl.hh:65
BaseDynInst
Definition: base_dyn_inst.hh:76
BaseO3DynInst::setVecLaneOperandT
void setVecLaneOperandT(const StaticInst *si, int idx, const LD &val)
Write a lane of the destination vector operand.
Definition: dyn_inst.hh:327
BaseDynInst::cpu
ImplCPU * cpu
Pointer to the Impl's CPU object.
Definition: base_dyn_inst.hh:156
BaseDynInst::setFloatRegOperandBits
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Records an fp register being set to an integer value.
Definition: base_dyn_inst.hh:780
VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:59
BaseO3DynInst::MaxInstDestRegs
@ MaxInstDestRegs
Definition: dyn_inst.hh:73
X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
BaseO3DynInst::readVec8BitLaneOperand
ConstVecLane8 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
Vector Register Lane Interfaces.
Definition: dyn_inst.hh:298
InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:37
BaseDynInst::numDestRegs
int8_t numDestRegs() const
Returns the number of destination registers.
Definition: base_dyn_inst.hh:667
BaseDynInst::prevDestRegIdx
PhysRegIdPtr prevDestRegIdx(int idx) const
Returns the physical register index of the previous physical register that remapped to the same logic...
Definition: base_dyn_inst.hh:399
BaseO3DynInst::setVecLaneOperand
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
Write a lane of the destination vector operand.
Definition: dyn_inst.hh:332
BaseO3DynInst::readFloatRegOperandBits
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
Definition: dyn_inst.hh:274
IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:53
CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:60
BaseO3DynInst::readCCRegOperand
RegVal readCCRegOperand(const StaticInst *si, int idx) override
Definition: dyn_inst.hh:375
BaseO3DynInst::getWritableVecRegOperand
VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Read destination vector register operand for modification.
Definition: dyn_inst.hh:289
BaseO3DynInst::initiateAcc
Fault initiateAcc()
Initiates the access.
Definition: dyn_inst_impl.hh:143
MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:61
VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:56
BaseO3DynInst::readVec64BitLaneOperand
ConstVecLane64 readVec64BitLaneOperand(const StaticInst *si, int idx) const override
Reads source vector 64bit operand.
Definition: dyn_inst.hh:319
BaseO3DynInst::readVecRegOperand
const VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Vector Register Interfaces.
Definition: dyn_inst.hh:280
BaseDynInst::staticInst
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Definition: base_dyn_inst.hh:153
BaseO3DynInst::completeAcc
Fault completeAcc(PacketPtr pkt)
Completes the access.
Definition: dyn_inst_impl.hh:161
MipsISA::PCState
GenericISA::DelaySlotPCState< MachInst > PCState
Definition: types.hh:41
BaseO3DynInst::setVecElemOperand
void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) override
Record a vector register being set to a value.
Definition: dyn_inst.hh:405
Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:257
reg_class.hh
BaseO3DynInst::syscall
void syscall() override
Emulates a syscall.
Definition: dyn_inst_impl.hh:192
PhysRegId
Physical register ID.
Definition: reg_class.hh:223
BaseDynInst::threadNumber
ThreadID threadNumber
The thread this instruction is from.
Definition: base_dyn_inst.hh:193
BaseO3DynInst::readVecPredRegOperand
const VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
Definition: dyn_inst.hh:363
RefCountingPtr< StaticInst >
RegId::index
const RegIndex & index() const
Index accessors.
Definition: reg_class.hh:173
ExecContext::VecElem
TheISA::VecElem VecElem
Definition: exec_context.hh:75
BaseO3DynInst::_destMiscRegIdx
std::array< short, TheISA::MaxMiscDestRegs > _destMiscRegIdx
Indexes of the destination misc.
Definition: dyn_inst.hh:114
cpu.hh
BaseDynInst::macroop
const StaticInstPtr macroop
The Macroop if one exists.
Definition: base_dyn_inst.hh:203
BaseO3DynInst::_numDestMiscRegs
uint8_t _numDestMiscRegs
Number of destination misc.
Definition: dyn_inst.hh:117
BaseO3DynInst::setVecRegOperand
void setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val) override
Record a vector register being set to a value.
Definition: dyn_inst.hh:398
RegId::classValue
const RegClass & classValue() const
Class accessor.
Definition: reg_class.hh:200
BaseO3DynInst::trap
void trap(const Fault &fault)
Traps to handle specified fault.
Definition: dyn_inst_impl.hh:185
LaneData
LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values ...
Definition: vec_reg.hh:458
RegVal
uint64_t RegVal
Definition: types.hh:168
VecRegContainer
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
Definition: vec_reg.hh:156
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:171
RefCountingPtr::get
T * get() const
Directly access the pointer itself without taking a reference.
Definition: refcnt.hh:219

Generated on Wed Sep 30 2020 14:02:08 for gem5 by doxygen 1.8.17