Go to the documentation of this file.
42 #ifndef __CPU_O3_DYN_INST_HH__
43 #define __CPU_O3_DYN_INST_HH__
47 #include "config/the_isa.hh"
61 typedef typename Impl::O3CPU
O3CPU;
126 int32_t dispatchTick;
128 int32_t completeTick;
174 assert(
reg.isMiscReg());
175 return this->
cpu->readMiscReg(reg.
index(), this->threadNumber);
185 assert(
reg.isMiscReg());
197 bool no_squash_from_TC = this->
thread->noSquashFromTC;
198 this->
thread->noSquashFromTC =
true;
201 this->
cpu->setMiscReg(
204 this->
thread->noSquashFromTC = no_squash_from_TC;
210 for (
int idx = 0; idx < this->
numDestRegs(); idx++) {
212 const RegId& original_dest_reg =
217 this->cpu->readIntReg(prev_phys_reg));
221 this->cpu->readFloatReg(prev_phys_reg));
225 this->cpu->readVecReg(prev_phys_reg));
229 this->cpu->readVecElem(prev_phys_reg));
233 this->cpu->readVecPredReg(prev_phys_reg));
237 this->cpu->readCCReg(prev_phys_reg));
243 panic(
"Unknown register class: %d",
325 template <
typename LD>
428 #endif // __CPU_O3_ALPHA_DYN_INST_HH__
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Records a CC register being set to a value.
TheISA::PCState predPC
Predicted PC state after this instruction.
void setMiscReg(int misc_reg, RegVal val) override
Sets a misc.
ConstVecLane16 readVec16BitLaneOperand(const StaticInst *si, int idx) const override
Reads source vector 16bit operand.
Impl::O3CPU O3CPU
Typedef for the CPU.
void initVars()
Initializes variables.
Generic predicate register container.
const RegId & destRegIdx(int i) const
Return logical index (architectural reg num) of i'th destination reg.
const int MaxMiscDestRegs
VecReg::Container VecRegContainer
@ VecElemClass
Vector Register Native Elem lane.
VecPredRegContainer & getWritableVecPredRegOperand(const StaticInst *si, int idx) override
Gets destination predicate register operand for modification.
ImplState * thread
Pointer to the thread state.
void setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val) override
Record a vector register being set to a value.
static constexpr auto NumVecElemPerVecReg
Base, ISA-independent static instruction class.
Fault fault
The kind of fault this instruction has generated.
void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) override
Record a vector register being set to a value.
uint64_t Tick
Tick count type.
VecPredReg::Container VecPredRegContainer
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::EightByte > &val) override
void setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
Sets a misc.
BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu)
BaseDynInst constructor given a binary instruction.
VecElem readVecElemOperand(const StaticInst *si, int idx) const override
Vector Elem Interfaces.
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Records an fp register being set to an integer value.
ConstVecLane32 readVec32BitLaneOperand(const StaticInst *si, int idx) const override
Reads source vector 32bit operand.
void updateMiscRegs()
Called at the commit stage to update the misc.
void setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer &val) override
Record a vector register being set to a value.
Register ID: describe an architectural register with its class and index.
RegVal readIntRegOperand(const StaticInst *si, int idx) override
Reads an integer register.
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
RegVal readMiscRegOperand(const StaticInst *si, int idx) override
Reads a misc.
void setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
Records an integer register being set to a value.
std::array< RegVal, TheISA::MaxMiscDestRegs > _destMiscRegVal
Values to be written to the destination misc.
std::array< PhysRegIdPtr, TheISA::MaxInstDestRegs > _destRegIdx
Physical register index of the destination registers of this instruction.
RegVal readMiscReg(int misc_reg) override
Reads a misc.
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::FourByte > &val) override
TheISA::MachInst MachInst
Binary machine instruction type.
@ FloatRegClass
Floating-point register.
void setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val) override
Record a vector register being set to a value.
std::array< PhysRegIdPtr, TheISA::MaxInstSrcRegs > _srcRegIdx
Physical register index of the source registers of this instruction.
TheISA::PCState pc
PC state for this instruction.
Vector Lane abstraction Another view of a container.
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::TwoByte > &val) override
Fault execute()
Executes the instruction.
std::shared_ptr< FaultBase > Fault
void setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
Records a CC register being set to a value.
constexpr unsigned NumVecElemPerVecReg
void setVecLaneOperandT(const StaticInst *si, int idx, const LD &val)
Write a lane of the destination vector operand.
ImplCPU * cpu
Pointer to the Impl's CPU object.
void setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
Records an fp register being set to an integer value.
ConstVecLane8 readVec8BitLaneOperand(const StaticInst *si, int idx) const override
Vector Register Lane Interfaces.
int8_t numDestRegs() const
Returns the number of destination registers.
PhysRegIdPtr prevDestRegIdx(int idx) const
Returns the physical register index of the previous physical register that remapped to the same logic...
virtual void setVecLaneOperand(const StaticInst *si, int idx, const LaneData< LaneSize::Byte > &val) override
Write a lane of the destination vector operand.
RegVal readFloatRegOperandBits(const StaticInst *si, int idx) override
Reads a floating point register in its binary format, instead of by value.
@ IntRegClass
Integer register.
@ CCRegClass
Condition-code register.
RegVal readCCRegOperand(const StaticInst *si, int idx) override
VecRegContainer & getWritableVecRegOperand(const StaticInst *si, int idx) override
Read destination vector register operand for modification.
Fault initiateAcc()
Initiates the access.
@ MiscRegClass
Control (misc) register.
@ VecRegClass
Vector Register.
ConstVecLane64 readVec64BitLaneOperand(const StaticInst *si, int idx) const override
Reads source vector 64bit operand.
const VecRegContainer & readVecRegOperand(const StaticInst *si, int idx) const override
Vector Register Interfaces.
const StaticInstPtr staticInst
The StaticInst used by this BaseDynInst.
Fault completeAcc(PacketPtr pkt)
Completes the access.
GenericISA::DelaySlotPCState< MachInst > PCState
void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) override
Record a vector register being set to a value.
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
void syscall() override
Emulates a syscall.
ThreadID threadNumber
The thread this instruction is from.
const VecPredRegContainer & readVecPredRegOperand(const StaticInst *si, int idx) const override
Predicate registers interface.
const RegIndex & index() const
Index accessors.
std::array< short, TheISA::MaxMiscDestRegs > _destMiscRegIdx
Indexes of the destination misc.
const StaticInstPtr macroop
The Macroop if one exists.
uint8_t _numDestMiscRegs
Number of destination misc.
void setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer &val) override
Record a vector register being set to a value.
const RegClass & classValue() const
Class accessor.
void trap(const Fault &fault)
Traps to handle specified fault.
LaneSize is an abstraction of a LS byte value for the execution and thread contexts to handle values ...
Vector Register Abstraction This generic class is the model in a particularization of MVC,...
#define panic(...)
This implements a cprintf based panic() function.
T * get() const
Directly access the pointer itself without taking a reference.
Generated on Wed Sep 30 2020 14:02:08 for gem5 by doxygen 1.8.17