cpu.hh

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/*
 * Copyright (c) 2011-2013, 2016-2020 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * Copyright (c) 2011 Regents of the University of California
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#ifndef __CPU_O3_CPU_HH__
#define __CPU_O3_CPU_HH__
 
#include <iostream>
#include <list>
#include <queue>
#include <set>
#include <vector>
 
#include "arch/generic/types.hh"
#include "arch/types.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/timebuf.hh"
#include "params/DerivO3CPU.hh"
#include "sim/process.hh"
 
template <class>
class Checker;
class ThreadContext;
template <class>
class O3ThreadContext;
 
class Checkpoint;
class Process;
 
struct BaseCPUParams;
 
class BaseO3CPU : public BaseCPU
{
    //Stuff that's pretty ISA independent will go here.
  public:
    BaseO3CPU(BaseCPUParams *params);
 
    void regStats();
};
 
template <class Impl>
class FullO3CPU : public BaseO3CPU
{
  public:
    // Typedefs from the Impl here.
    typedef typename Impl::CPUPol CPUPolicy;
    typedef typename Impl::DynInstPtr DynInstPtr;
    typedef typename Impl::O3CPU O3CPU;
 
    using VecElem =  TheISA::VecElem;
    using VecRegContainer =  TheISA::VecRegContainer;
 
    using VecPredRegContainer = TheISA::VecPredRegContainer;
 
    typedef O3ThreadState<Impl> ImplState;
    typedef O3ThreadState<Impl> Thread;
 
    typedef typename std::list<DynInstPtr>::iterator ListIt;
 
    friend class O3ThreadContext<Impl>;
 
  public:
    enum Status {
        Running,
        Idle,
        Halted,
        Blocked,
        SwitchedOut
    };
 
    BaseTLB *itb;
    BaseTLB *dtb;
    using LSQRequest = typename LSQ<Impl>::LSQRequest;
 
    Status _status;
 
  private:
 
    EventFunctionWrapper tickEvent;
 
    EventFunctionWrapper threadExitEvent;
 
    void scheduleTickEvent(Cycles delay)
    {
        if (tickEvent.squashed())
            reschedule(tickEvent, clockEdge(delay));
        else if (!tickEvent.scheduled())
            schedule(tickEvent, clockEdge(delay));
    }
 
    void unscheduleTickEvent()
    {
        if (tickEvent.scheduled())
            tickEvent.squash();
    }
 
    bool tryDrain();
 
    void drainSanityCheck() const;
 
    bool isCpuDrained() const;
 
  public:
    FullO3CPU(DerivO3CPUParams *params);
    ~FullO3CPU();
 
    void regStats() override;
 
    ProbePointArg<PacketPtr> *ppInstAccessComplete;
    ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
 
    void regProbePoints() override;
 
    void demapPage(Addr vaddr, uint64_t asn)
    {
        this->itb->demapPage(vaddr, asn);
        this->dtb->demapPage(vaddr, asn);
    }
 
    void demapInstPage(Addr vaddr, uint64_t asn)
    {
        this->itb->demapPage(vaddr, asn);
    }
 
    void demapDataPage(Addr vaddr, uint64_t asn)
    {
        this->dtb->demapPage(vaddr, asn);
    }
 
    void tick();
 
    void init() override;
 
    void startup() override;
 
    int numActiveThreads()
    { return activeThreads.size(); }
 
    void activateThread(ThreadID tid);
 
    void deactivateThread(ThreadID tid);
 
    void insertThread(ThreadID tid);
 
    void removeThread(ThreadID tid);
 
    Counter totalInsts() const override;
 
    Counter totalOps() const override;
 
    void activateContext(ThreadID tid) override;
 
    void suspendContext(ThreadID tid) override;
 
    void haltContext(ThreadID tid) override;
 
    void updateThreadPriority();
 
    bool isDraining() const { return drainState() == DrainState::Draining; }
 
    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 
    void addThreadToExitingList(ThreadID tid);
 
    bool isThreadExiting(ThreadID tid) const;
 
    void scheduleThreadExitEvent(ThreadID tid);
 
    void exitThreads();
 
  public:
    void syscall(ThreadID tid);
 
    DrainState drain() override;
 
    void drainResume() override;
 
    void commitDrained(ThreadID tid);
 
    void switchOut() override;
 
    void takeOverFrom(BaseCPU *oldCPU) override;
 
    void verifyMemoryMode() const override;
 
    InstSeqNum getAndIncrementInstSeq()
    { return globalSeqNum++; }
 
    void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
 
    void setVectorsAsReady(ThreadID tid);
 
    void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
 
    Fault getInterrupts();
 
    void processInterrupts(const Fault &interrupt);
 
    void halt() { panic("Halt not implemented!\n"); }
 
    RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 
    RegVal readMiscReg(int misc_reg, ThreadID tid);
 
    void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
 
    void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
 
    RegVal readIntReg(PhysRegIdPtr phys_reg);
 
    RegVal readFloatReg(PhysRegIdPtr phys_reg);
 
    const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
 
    VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
 
    Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
 
    void vecRenameMode(Enums::VecRegRenameMode vec_mode)
    { vecMode = vec_mode; }
 
    template<typename VecElem, int LaneIdx>
    VecLaneT<VecElem, true>
    readVecLane(PhysRegIdPtr phys_reg) const
    {
        vecRegfileReads++;
        return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
    }
 
    template<typename VecElem>
    VecLaneT<VecElem, true>
    readVecLane(PhysRegIdPtr phys_reg) const
    {
        vecRegfileReads++;
        return regFile.readVecLane<VecElem>(phys_reg);
    }
 
    template<typename LD>
    void
    setVecLane(PhysRegIdPtr phys_reg, const LD& val)
    {
        vecRegfileWrites++;
        return regFile.setVecLane(phys_reg, val);
    }
 
    const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
 
    const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
 
    VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
 
    RegVal readCCReg(PhysRegIdPtr phys_reg);
 
    void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
 
    void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
 
    void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
 
    void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
 
    void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
 
    void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
 
    RegVal readArchIntReg(int reg_idx, ThreadID tid);
 
    RegVal readArchFloatReg(int reg_idx, ThreadID tid);
 
    const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
    VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
 
    template<typename VecElem>
    VecLaneT<VecElem, true>
    readArchVecLane(int reg_idx, int lId, ThreadID tid) const
    {
        PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                    RegId(VecRegClass, reg_idx));
        return readVecLane<VecElem>(phys_reg);
    }
 
 
    template<typename LD>
    void
    setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
    {
        PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
                    RegId(VecRegClass, reg_idx));
        setVecLane(phys_reg, val);
    }
 
    const VecElem& readArchVecElem(const RegIndex& reg_idx,
                                   const ElemIndex& ldx, ThreadID tid) const;
 
    const VecPredRegContainer& readArchVecPredReg(int reg_idx,
                                                  ThreadID tid) const;
 
    VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
 
    RegVal readArchCCReg(int reg_idx, ThreadID tid);
 
    void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
 
    void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
 
    void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
                           ThreadID tid);
 
    void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
 
    void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
                        const VecElem& val, ThreadID tid);
 
    void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
 
    void pcState(const TheISA::PCState &newPCState, ThreadID tid);
 
    TheISA::PCState pcState(ThreadID tid);
 
    Addr instAddr(ThreadID tid);
 
    MicroPC microPC(ThreadID tid);
 
    Addr nextInstAddr(ThreadID tid);
 
    void squashFromTC(ThreadID tid);
 
    ListIt addInst(const DynInstPtr &inst);
 
    void instDone(ThreadID tid, const DynInstPtr &inst);
 
    void removeFrontInst(const DynInstPtr &inst);
 
    void removeInstsNotInROB(ThreadID tid);
 
    void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
 
    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
 
    void cleanUpRemovedInsts();
 
    void dumpInsts();
 
  public:
#ifndef NDEBUG
 
    int instcount;
#endif
 
    std::list<DynInstPtr> instList;
 
    std::queue<ListIt> removeList;
 
#ifdef DEBUG
 
    std::set<InstSeqNum> snList;
#endif
 
    bool removeInstsThisCycle;
 
  protected:
    typename CPUPolicy::Fetch fetch;
 
    typename CPUPolicy::Decode decode;
 
    typename CPUPolicy::Rename rename;
 
    typename CPUPolicy::IEW iew;
 
    typename CPUPolicy::Commit commit;
 
    Enums::VecRegRenameMode vecMode;
 
    PhysRegFile regFile;
 
    typename CPUPolicy::FreeList freeList;
 
    typename CPUPolicy::RenameMap renameMap[Impl::MaxThreads];
 
    typename CPUPolicy::RenameMap commitRenameMap[Impl::MaxThreads];
 
    typename CPUPolicy::ROB rob;
 
    std::list<ThreadID> activeThreads;
 
    std::unordered_map<ThreadID, bool> exitingThreads;
 
    Scoreboard scoreboard;
 
    std::vector<TheISA::ISA *> isa;
 
  public:
    enum StageIdx {
        FetchIdx,
        DecodeIdx,
        RenameIdx,
        IEWIdx,
        CommitIdx,
        NumStages };
 
    typedef typename CPUPolicy::TimeStruct TimeStruct;
 
    typedef typename CPUPolicy::FetchStruct FetchStruct;
 
    typedef typename CPUPolicy::DecodeStruct DecodeStruct;
 
    typedef typename CPUPolicy::RenameStruct RenameStruct;
 
    typedef typename CPUPolicy::IEWStruct IEWStruct;
 
    TimeBuffer<TimeStruct> timeBuffer;
 
    TimeBuffer<FetchStruct> fetchQueue;
 
    TimeBuffer<DecodeStruct> decodeQueue;
 
    TimeBuffer<RenameStruct> renameQueue;
 
    TimeBuffer<IEWStruct> iewQueue;
 
  private:
    ActivityRecorder activityRec;
 
  public:
    void activityThisCycle() { activityRec.activity(); }
 
    void activateStage(const StageIdx idx)
    { activityRec.activateStage(idx); }
 
    void deactivateStage(const StageIdx idx)
    { activityRec.deactivateStage(idx); }
 
    void wakeCPU();
 
    virtual void wakeup(ThreadID tid) override;
 
    ThreadID getFreeTid();
 
  public:
    ThreadContext *
    tcBase(ThreadID tid)
    {
        return thread[tid]->getTC();
    }
 
    InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 
    Checker<Impl> *checker;
 
    System *system;
 
    std::vector<Thread *> thread;
 
    std::list<int> cpuWaitList;
 
    Cycles lastRunningCycle;
 
    Tick lastActivatedCycle;
 
    std::map<ThreadID, unsigned> threadMap;
 
    std::vector<ThreadID> tids;
 
    Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
                      unsigned int size, Addr addr, Request::Flags flags,
                      uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
                      const std::vector<bool>& byte_enable =
                          std::vector<bool>())
 
    {
        return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
                flags, res, std::move(amo_op), byte_enable);
    }
 
    Fault read(LSQRequest* req, int load_idx)
    {
        return this->iew.ldstQueue.read(req, load_idx);
    }
 
    Fault write(LSQRequest* req, uint8_t *data, int store_idx)
    {
        return this->iew.ldstQueue.write(req, data, store_idx);
    }
 
    Port &
    getInstPort() override
    {
        return this->fetch.getInstPort();
    }
 
    Port &
    getDataPort() override
    {
        return this->iew.ldstQueue.getDataPort();
    }
 
    Stats::Scalar timesIdled;
    Stats::Scalar idleCycles;
    Stats::Scalar quiesceCycles;
    Stats::Vector committedInsts;
    Stats::Vector committedOps;
    Stats::Formula cpi;
    Stats::Formula totalCpi;
    Stats::Formula ipc;
    Stats::Formula totalIpc;
 
    //number of integer register file accesses
    Stats::Scalar intRegfileReads;
    Stats::Scalar intRegfileWrites;
    //number of float register file accesses
    Stats::Scalar fpRegfileReads;
    Stats::Scalar fpRegfileWrites;
    //number of vector register file accesses
    mutable Stats::Scalar vecRegfileReads;
    Stats::Scalar vecRegfileWrites;
    //number of predicate register file accesses
    mutable Stats::Scalar vecPredRegfileReads;
    Stats::Scalar vecPredRegfileWrites;
    //number of CC register file accesses
    Stats::Scalar ccRegfileReads;
    Stats::Scalar ccRegfileWrites;
    //number of misc
    Stats::Scalar miscRegfileReads;
    Stats::Scalar miscRegfileWrites;
 
  public:
    // hardware transactional memory
    void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
                            HtmFailureFaultCause cause);
};
 
#endif // __CPU_O3_CPU_HH__