gem5  v20.1.0.0
cpu_policy.hh
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29 
30 #ifndef __CPU_O3_CPU_POLICY_HH__
31 #define __CPU_O3_CPU_POLICY_HH__
32 
33 #include "cpu/o3/comm.hh"
34 #include "cpu/o3/commit.hh"
35 #include "cpu/o3/decode.hh"
36 #include "cpu/o3/fetch.hh"
37 #include "cpu/o3/free_list.hh"
38 #include "cpu/o3/iew.hh"
39 #include "cpu/o3/inst_queue.hh"
40 #include "cpu/o3/lsq.hh"
41 #include "cpu/o3/lsq_unit.hh"
42 #include "cpu/o3/mem_dep_unit.hh"
43 #include "cpu/o3/regfile.hh"
44 #include "cpu/o3/rename.hh"
45 #include "cpu/o3/rename_map.hh"
46 #include "cpu/o3/rob.hh"
47 #include "cpu/o3/store_set.hh"
48 
58 template<class Impl>
60 {
66  typedef ::ROB<Impl> ROB;
70  typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
72  typedef ::LSQ<Impl> LSQ;
74  typedef ::LSQUnit<Impl> LSQUnit;
75 
86 
89 
92 
95 
98 
100  typedef ::IssueStruct<Impl> IssueStruct;
101 
104 
105 };
106 
107 #endif //__CPU_O3_CPU_POLICY_HH__
UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:169
commit.hh
SimpleCPUPolicy::DecodeStruct
DefaultDecodeDefaultRename< Impl > DecodeStruct
The struct for communication between decode and rename.
Definition: cpu_policy.hh:91
rename.hh
SimpleCPUPolicy
Struct that defines the key classes to be used by the CPU.
Definition: cpu_policy.hh:59
DefaultDecodeDefaultRename
Struct that defines the information passed from decode to rename.
Definition: comm.hh:67
SimpleCPUPolicy::ROB
::ROB< Impl > ROB
Typedef for the ROB.
Definition: cpu_policy.hh:66
iew.hh
rob.hh
SimpleCPUPolicy::IssueStruct
::IssueStruct< Impl > IssueStruct
The struct for communication within the IEW stage.
Definition: cpu_policy.hh:100
store_set.hh
SimpleCPUPolicy::IEW
DefaultIEW< Impl > IEW
Typedef for Issue/Execute/Writeback.
Definition: cpu_policy.hh:83
SimpleCPUPolicy::FetchStruct
DefaultFetchDefaultDecode< Impl > FetchStruct
The struct for communication between fetch and decode.
Definition: cpu_policy.hh:88
comm.hh
SimpleCPUPolicy::IEWStruct
DefaultIEWDefaultCommit< Impl > IEWStruct
The struct for communication between IEW and commit.
Definition: cpu_policy.hh:97
SimpleCPUPolicy::TimeStruct
TimeBufStruct< Impl > TimeStruct
The struct for all backwards communication.
Definition: cpu_policy.hh:103
SimpleCPUPolicy::MemDepUnit
::MemDepUnit< StoreSet, Impl > MemDepUnit
Typedef for the memory dependence unit.
Definition: cpu_policy.hh:70
SimpleCPUPolicy::IQ
InstructionQueue< Impl > IQ
Typedef for the instruction queue/scheduler.
Definition: cpu_policy.hh:68
SimpleCPUPolicy::Fetch
DefaultFetch< Impl > Fetch
Typedef for fetch.
Definition: cpu_policy.hh:77
SimpleCPUPolicy::FreeList
UnifiedFreeList FreeList
Typedef for the freelist of registers.
Definition: cpu_policy.hh:62
DefaultRenameDefaultIEW
Struct that defines the information passed from rename to IEW.
Definition: comm.hh:77
DefaultCommit
DefaultCommit handles single threaded and SMT commit.
Definition: commit.hh:81
mem_dep_unit.hh
SimpleCPUPolicy::RenameMap
UnifiedRenameMap RenameMap
Typedef for the rename map.
Definition: cpu_policy.hh:64
UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:115
fetch.hh
rename_map.hh
regfile.hh
DefaultFetch
DefaultFetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:71
TimeBufStruct
Struct that defines all backwards communication.
Definition: comm.hh:115
SimpleCPUPolicy::LSQ
::LSQ< Impl > LSQ
Typedef for the LSQ.
Definition: cpu_policy.hh:72
SimpleCPUPolicy::RenameStruct
DefaultRenameDefaultIEW< Impl > RenameStruct
The struct for communication between rename and IEW.
Definition: cpu_policy.hh:94
SimpleCPUPolicy::Commit
DefaultCommit< Impl > Commit
Typedef for commit.
Definition: cpu_policy.hh:85
DefaultIEWDefaultCommit
Struct that defines the information passed from IEW to commit.
Definition: comm.hh:87
SimpleCPUPolicy::Rename
DefaultRename< Impl > Rename
Typedef for rename.
Definition: cpu_policy.hh:81
DefaultDecode
DefaultDecode class handles both single threaded and SMT decode.
Definition: decode.hh:59
InstructionQueue
A standard instruction queue class.
Definition: inst_queue.hh:81
lsq_unit.hh
free_list.hh
SimpleCPUPolicy::LSQUnit
::LSQUnit< Impl > LSQUnit
Typedef for the thread-specific LSQ units.
Definition: cpu_policy.hh:74
inst_queue.hh
SimpleCPUPolicy::Decode
DefaultDecode< Impl > Decode
Typedef for decode.
Definition: cpu_policy.hh:79
decode.hh
lsq.hh
DefaultRename
DefaultRename handles both single threaded and SMT rename.
Definition: rename.hh:68
DefaultIEW
DefaultIEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:78
DefaultFetchDefaultDecode
Struct that defines the information passed from fetch to decode.
Definition: comm.hh:54

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